CN113393790A

CN113393790A - Display panel driving method and device and display device

Info

Publication number: CN113393790A
Application number: CN202110555260.5A
Authority: CN
Inventors: 康志聪; 袁海江
Original assignee: HKC Co Ltd; Beihai HKC Optoelectronics Technology Co Ltd
Current assignee: HKC Co Ltd; Beihai HKC Optoelectronics Technology Co Ltd
Priority date: 2021-05-20
Filing date: 2021-05-20
Publication date: 2021-09-14
Anticipated expiration: 2041-05-20
Also published as: CN113393790B

Abstract

The invention discloses a driving method and a device of a display panel and a display device, wherein the display panel comprises: the pixel array comprises a plurality of pixel groups, wherein each pixel group comprises two rows of adjacent sub-pixel groups, and the storage capacitors of one sub-pixel in each sub-pixel group and two non-adjacent sub-pixels in the other sub-pixel group are respectively connected with a first common electrode line; the storage capacitors of one sub-pixel in each sub-pixel group and two adjacent sub-pixels in the other sub-pixel group are connected with the other first common electrode wire; each sub-pixel group is connected with a data line with the sub-pixel groups of adjacent rows of adjacent columns; the polarities of the voltages on the two adjacent first common electrode lines are opposite; the driving method of the display panel comprises the following steps: controlling the data voltage on each data line to switch the positive polarity and the negative polarity by taking two frames as a driving period; and controlling the common electrode voltage on each first common electrode line to maintain the same polarity as the common electrode voltage of the previous frame.

Description

Display panel driving method and device and display device

Technical Field

The present invention relates to the field of display device technologies, and in particular, to a method and an apparatus for driving a display panel, and a display device.

Background

At present, a large-sized display panel needs a large viewing angle, and during a pixel driving process, the large viewing angle brightness is rapidly saturated with voltage, so that the viewing angle image quality contrast and the color cast are seriously deteriorated compared with the front-view image quality. The common way to solve the color shift of the viewing angle is to divide each sub-pixel of the display panel into a main pixel and a sub-pixel, and to apply different driving voltages to the main pixel and the sub-pixel, such a design usually needs to design a metal trace or a TFT element to drive the sub-pixel, which results in the sacrifice of the light-permeable opening area, the influence on the panel transmittance, and the direct increase of the backlight cost.

Disclosure of Invention

The invention provides a driving method and a driving device of a display panel and a display device, and aims to solve the problem of image quality color cast caused by visual angle deviation.

To achieve the above object, the present invention provides a driving method of a display panel, the display panel including:

each pixel group comprises two rows of adjacent sub-pixel groups, each two rows of adjacent sub-pixel groups are respectively connected with one scanning line, each sub-pixel group comprises two sub-pixels, and the two sub-pixels are connected with the same scanning line;

in two sub-pixel groups in adjacent rows, the storage capacitors of two adjacent sub-pixels are connected with the same first common electrode wire, and the storage capacitors of two non-adjacent sub-pixels are respectively connected with the other two first common electrode wires in a one-to-one correspondence manner;

two data lines which are positioned in the same row and are respectively connected with two adjacent sub-pixel groups are adjacent, and two data lines which are positioned in the adjacent row and are respectively connected with two adjacent sub-pixel groups are adjacent;

the polarities of the voltages on the two adjacent first common electrode lines are opposite; the driving method of the display panel includes the steps of:

controlling the data voltage on each data line to switch the positive polarity and the negative polarity by taking two frames as a driving period;

and controlling the common electrode voltage on each first common electrode line to be the same as the common electrode voltage of the previous frame in polarity.

Optionally, the scanning signal on each scanning line in each frame comprises an on phase and an off phase;

when the scanning signal of each scanning line is in a starting stage, controlling the common electrode voltage on the first common electrode line to perform high-low level turnover switching;

and when the scanning signal of each scanning line is in a closing stage, controlling the voltage of the common electrode on the first common electrode line to carry out secondary high-low level turnover switching.

Optionally, the step of controlling the common electrode voltage on the first common electrode line to perform secondary high-low level flip switching when the scanning signal of each scanning line is in the off phase includes:

two rows of sub-pixels in the same group are respectively an nth row of sub-pixels and an n +1 th row of sub-pixels;

when the data voltage of the sub-pixels in the nth row and the sub-pixels in the (n +1) th row are positive, controlling the voltage of the common electrode of the sub-pixels in the nth row to be switched from a low level to a high level, and controlling the voltage of the common electrode of the sub-pixels in the (n +1) th row to be switched from the high level to the low level;

when the data voltage of the sub-pixels in the nth row and the sub-pixels in the (n +1) th row are controlled to be negative, the voltage of the common electrode of the sub-pixels in the nth row is controlled to be switched from a low level to a high level, and the voltage of the common electrode of the sub-pixels in the (n +1) th row is controlled to be switched from the high level to the low level.

Optionally, the step of controlling the common electrode voltage on the first common electrode line to perform the second high-low level flip switching when the scanning signal of each scanning line is in the off phase specifically includes:

when the data voltage of the sub-pixels in the nth row and the sub-pixels in the (n +1) th row are controlled to be positive, the voltage of the common electrode of the sub-pixels in the nth row is controlled to be switched from a high level to a low level, and the voltage of the common electrode of the sub-pixels in the (n +1) th row is controlled to be switched from the low level to the high level;

when the data voltage of the sub-pixels in the nth row and the sub-pixels in the (n +1) th row are controlled to be negative, the voltage of the common electrode of the sub-pixels in the nth row is controlled to be switched from high level to low level, and the voltage of the common electrode of the sub-pixels in the (n +1) th row is controlled to be switched from low level to high level.

Optionally, the driving method of the display panel further includes:

and in the same frame, controlling the data voltages on the data lines of two adjacent groups of the sub-pixels to switch the positive polarity and the negative polarity.

Optionally, the polarities of the data voltages on the data lines of two adjacent columns are opposite.

Optionally, the driving method of the display panel further includes:

and performing column inversion driving on each sub-pixel.

The present invention also provides a driving apparatus of a display panel, the display panel including:

the polarities of the voltages on the two adjacent first common electrode lines are opposite, and the polarities of the data voltages on the data lines of the sub-pixels in each group positioned in the same column are the same; the driving device of the display panel includes:

the source driving circuit is configured to output data voltages with positive and negative polarities switched to the data lines by taking two frames as a driving period;

a common electrode voltage circuit, an output terminal of the common electrode voltage circuit and each of the first common electrode lines, the common electrode voltage circuit being configured to output a common electrode voltage having the same polarity as a common electrode voltage of a previous frame to each of the first common electrode lines with two frames as one driving period;

the driving device of the display panel is further provided with a processor, a memory and a driving program of the display panel, which is stored on the memory and can run on the processor, wherein the driving program of the display panel is configured to realize the steps of the driving method of the display panel.

Optionally, the driving apparatus of the display panel further includes a gate driving circuit, and the gate driving circuit is connected to the gate of each of the sub-pixels; the gate driving circuit is configured to output a gate driving signal to each row of sub-pixels, so that corresponding voltages are applied to the second common electrode and the data line, and the sub-pixel capacitors in the corresponding row are charged.

Optionally, the driving apparatus of the display panel further includes a timing controller, and the timing controller is respectively connected to the gate driving circuit and the source driving circuit; the timing controller is configured to output a timing control signal to the gate driving circuit and the source driving circuit.

The invention also provides a display device, which comprises a display panel and the driving device of the display panel, wherein the driving device of the display panel is connected with each sub-pixel of the display panel.

In the driving method of the display panel, in each sub-pixel group in one frame, because the same column of data voltage has the same polarity and the common electrode voltage on the first common electrode has different levels, the brightness displayed by the two sub-pixels is different. And when two frames are used as a driving period, the positive polarity and the negative polarity are switched by controlling the data voltage on each data line by using two frames as one driving period, and then the positive polarity and the negative polarity are switched by controlling the data voltage on each data line by using two frames as one driving period. The arrangement is that in the same group, the display brightness of two sub-pixels in the same column is switched between brighter and darker in a frame, the display brightness of two sub-pixels in adjacent columns is switched between brighter and darker in a frame, and the brightness of two adjacent sub-pixels is changed. When the whole display panel shows the brightness difference, the display panel is displayed with relatively uniform brightness, so that the problem of image quality color cast caused by visual angle deviation is solved; in addition, the number of the scanning lines and the number of the common electrode lines are reduced by half through the common scanning lines and the first common electrode lines, so that the effective aperture opening ratio of the display panel is increased, the penetration rate is improved, and the cost is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.

FIG. 1 is a schematic circuit diagram of one embodiment of a plurality of sub-pixel groups of a display panel according to the present invention;

FIG. 2 is a flowchart illustrating a driving method of a display panel according to an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating a display effect of the display panel in the first frame1 and the second frame2 of the current driving period according to the present invention;

FIG. 4 is a schematic diagram of a driving timing relationship corresponding to the mth row scanning line according to the present invention;

FIG. 5 is a schematic diagram of a driving timing relationship corresponding to the mth row and the (n +1) th row of scan lines according to the present invention;

FIG. 6 is a schematic diagram illustrating another display effect of the display panel in the first frame1 and the second frame2 of the current driving period according to the present invention;

FIG. 7 is a schematic diagram of another driving timing relationship corresponding to the mth row scanning line according to the present invention;

FIG. 8 is a schematic diagram illustrating another driving timing relationship corresponding to the n +1 th row of the scan line in the mth column according to the present invention;

FIG. 9 is a schematic circuit diagram of a driving apparatus for a display panel according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the invention.

The reference numbers illustrate:

reference numerals	Name (R)	Reference numerals	Name (R)
				10	Time sequence controller	101	Sub-pixel group
20	Source electrode driving circuit	110	First substrate
				30	Gate drive circuit	120	Second substrate
40	Power management integrated circuit	130	Liquid crystal layer
				50	Common electrode voltage circuit	140	Pixel array
100	Display panel	150	Frame glue

The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.

In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.

The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

The invention provides a driving method of a display panel, which is suitable for a display device provided with the display panel.

At present, most of large-sized liquid crystal display panels adopt a negative VA (Vertical Alignment) liquid crystal or IPS (In-Plane Switching) liquid crystal technology, the VA liquid crystal technology has the advantages of higher production efficiency and lower manufacturing cost compared with the IPS liquid crystal technology, but the VA liquid crystal technology has the defect of more obvious optical properties compared with the IPS liquid crystal technology, especially the large-sized panels need a larger viewing angle In the aspect of commercial application, and the VA liquid crystal driving causes the contrast of the viewing angle image quality and the color cast to be seriously deteriorated compared with the front-view image quality due to the rapid saturation of the large-viewing angle brightness along with the voltage. The VA-mode liquid crystal technology solves the color shift of the viewing angle by subdividing each RGB sub-pixel into main/sub-pixels, so that the overall brightness of the large viewing angle is closer to the front view with the voltage variation, and this solves the color shift of the viewing angle by spatially providing different driving voltages to the main and sub-pixels, such a pixel design often needs to redesign a metal trace or a TFT element to drive the sub-pixels, which results in the sacrifice of a light-permeable opening area, affects the transmittance of the panel, and easily causes the increase of the backlight cost.

In order to achieve the purpose of compensating color shift without sacrificing the aperture ratio in pixel design, the invention realizes spatial high-low voltage adjacent arrangement by adjusting the driving signal, maintains the original brightness signal, achieves the optical effect that the brightness of a large visual angle is close to a positive visual angle, improves the color shift of the large visual angle, and further achieves the improvement of the color shift of the visual angle while maintaining the panel characteristic of higher penetration rate. And only through the difference of the driving signals, the switching can be realized on the original display without changing the pixel design under the use environment (doing high-low voltage adjacent driving) that the common display (doing high-low voltage adjacent driving) and the viewing angle color cast need to be emphasized.

Referring to fig. 1, in an embodiment of the present invention, the display panel includes:

a plurality of pixel groups 101, each pixel group comprises two rows of adjacent sub-pixel groups (101n, 101n ', 101n + 1'), the two rows of adjacent sub-pixel groups (101n, 101n '), (101n +1, 101n + 1') are respectively connected with one scanning line (Gn, Gn +1), each sub-pixel group comprises two sub-pixels, and the two sub-pixels are connected with the same scanning line;

in two sub-pixel groups in adjacent rows, the storage capacitors of two adjacent sub-pixels are connected with the same first common electrode wire, and the storage capacitors of two non-adjacent sub-pixels are correspondingly connected with the other two first common electrode wires one by one;

two data lines which are positioned in the same row and are respectively connected with two adjacent sub-pixel groups are adjacent, and two data lines which are positioned in the adjacent row and are respectively connected with two adjacent sub-pixel groups are adjacent; and the polarities of the voltages on the two adjacent first common electrode lines are opposite. The data voltage polarities of the data lines (Dm-1, Dm +1) of the two sub-pixels positioned in the same column in each group are the same, and the voltage polarities of the data lines (Dm-1, Dm +1) of the two sub-pixels positioned in the adjacent columns in the same row are opposite.

In this embodiment, the display panel is provided with a pixel array (not shown), a scan line (Gn, Gn +1), a data line (Dm-1, Dm +1), a first common electrode line Vst1 and a second common electrode line Vcom, and the pixel array includes a plurality of sub-pixels. Each sub-pixel comprises an active switch (thin film transistor), a pixel capacitor Clc and a storage capacitor Cst, wherein the gate of the active switch is electrically connected to the corresponding scan line (Gn, Gn +1) of the sub-pixel, the source of the active switch is electrically connected to the corresponding data line (Dm-1, Dm +1) of the sub-pixel, the drain of the active switch is electrically connected to one end of the pixel capacitor Clc and the storage capacitor Cst of the sub-pixel through the data line (Dm-1, Dm +1), and the other end of each pixel capacitor Clc is electrically connected to the second common electrode line Vcom. In the present embodiment, two rows of sub-pixels are defined as a sub-pixel group 101, and the other ends of the storage capacitors Cst of the two sub-pixel groups 101 are respectively connected to a first common electrode line Vst 1. Wherein, each sub-pixel is divided into red, green and blue sub-pixels. Every three sub-pixels of red, green and blue form a pixel. A plurality of thin film transistors constitute the thin film transistor array of the present embodiment. It should be noted that the number of the scan lines and the number of the data lines may be set according to the size, the resolution, and the like of the display panel, the embodiment of the present invention is described by taking two rows of scan lines and scan lines (Gn, Gn +1) and two columns of data lines (Dm-1, Dm +1) as an example, and the pixel driving of other rows may refer to each embodiment of the present invention, which is not described herein again.

Referring to FIG. 1, in FIG. 1, Gn and Gn +1 are illustrated as two adjacent rows of scan lines, Dm-1, Dm and Dm +1 are illustrated as three adjacent columns of data lines, and n^stVst1、(n+1)^stVst2、(n+2)^stThree adjacent first common electrode lines Vst1, Clc1 and Clc2, which represent pixel capacitances connected to the same scan line in the same group, and Cst1 and Cst2, which represent storage capacitances connected to different first common electrode lines in the same group, respectively.

Referring to fig. 2, the driving apparatus of the display panel includes a timing controller 10, a source driving circuit 20, a gate driving circuit 30, a power management integrated circuit 40, and a common electrode voltage circuit 50, and thin film transistors located in the same column are connected to the source driving circuit 20 through a data line (Dm-1, Dm +1), and thin film transistors located in two rows in each group are connected to the gate driving circuit 30 through a scan line (Gn, Gn +1), thereby forming a thin film transistor array. These thin film transistors may be a-Si (non-Silicon) thin film transistors or Poly-Si (polysilicon) thin film transistors, which may be formed using LTPS (Low Temperature polysilicon) or the like. The other end of the storage capacitor Cst is connected to the common electrode voltage circuit 50 via a second common electrode line Vcom.

The timing controller 10 receives data signals, control signals and timing signals output from an external control circuit, such as a control system SOC of a television, and converts the data signals, control signals and timing signals into data signals, control signals and timing signals suitable for the gate driving circuit 30 and the source driving circuit 20, the gate driving circuit 30 outputs gate-on signals and gate-off signals according to the timing signals to scan the sub-pixels of each row line by line, and when the thin film transistors in the sub-pixels of the corresponding row are turned on, the source driving circuit 20 outputs the data signals to the corresponding sub-pixels through the data lines (Dm-1, Dm +1), thereby realizing image display of the display panel. The number of the source driving circuits 20 is plural, and the source driving circuits can be specifically set according to the size of the display panel, and the embodiment is described by taking two examples. The output end of the power management integrated circuit 40 is connected with the gate drive circuit 30 and the source drive circuit 20; the power management integrated circuit 40 integrates a plurality of dc-dc conversion circuits of different circuit functions, each of which outputs a different voltage value. The input terminal of the power management integrated circuit 40 inputs a voltage of typically 5V or 12V, and outputs a voltage including an operating voltage DVDD supplied to the timing controller 10 and an operating voltage supplied to the gate driving circuit 30.

Referring to fig. 2, based on the display panel and the driving apparatus of the display panel, the driving method of the display panel includes the steps of:

step S100, controlling the data voltage on each data line to switch the positive polarity and the negative polarity by taking two frames as a driving period;

it is understood that, in the case where the potential of the second common electrode is kept constant, the ac driving of the liquid crystal molecules is realized as if the potential of the pixel capacitor connected to the second common electrode line is constant, and the potential of the other electrode of the pixel capacitor connected to the drain electrode is changed to be higher or lower than the potential of the common electrode reference voltage Vcom on the second common electrode. That is, the data voltage outputted by the source driver is increased or decreased relative to the common electrode reference voltage Vcom, and the polarity of the data voltage in this embodiment is determined by the voltage value of the data voltage and the common electrode reference voltage Vcom: the positive polarity of the data voltage means that the voltage value of the data voltage loaded by the data line is greater than the common electrode reference voltage Vcom on the second common electrode line; the negative polarity driving means that the voltage value of the data voltage loaded on the data line is smaller than the voltage value of the common electrode reference voltage Vcom on the second common electrode line. When the voltage difference between the two is greater than 0, the polarity is positive, generally indicated by a "+" sign; when the voltage difference between the two is less than 0, the polarity is negative, usually indicated by a "-" sign. Therefore, in this embodiment, controlling the data voltage on each data line to switch the positive and negative polarities in one driving period of two frames can be understood as: the voltage on the data line is switched to a negative polarity in a second frame when the voltage is positive in a first frame. In the driving process taking two frames as one driving period, the data voltage of each sub-pixel is controlled to be changed alternately in high and low, so that the same sub-pixel can not maintain high voltage or low voltage all the time, and the problems that the particle sense is easy to see and the resolution is reduced in the image quality because the high voltage or low voltage signal is maintained at the same sub-pixel position in space are avoided.

Taking two frames as the driving period, it can be understood that the pixel driving process of the current frame is completed, and the switching can be performed to the pixel driving of the next frame, and the pixel driving process of the next frame is also sequentially switched as the driving process of the current frame until the pixel driving of all frames is completed.

And step 200, controlling the common electrode voltage on each first common electrode line to be the same as the common electrode voltage of the previous frame in polarity.

In this embodiment, one end of the storage capacitor is connected to the thin film transistor through the pixel electrode, and the other end of the storage capacitor is connected to one first common electrode line, that is, the storage capacitor is formed by overlapping the pixel electrode and the second common electrode line. The voltage on the first common electrode line can realize high-low level switching, and can be specifically controlled by a common electrode voltage circuit, and a memory, a digital-to-analog converter, a signal amplifier and the like are usually integrated in the common electrode voltage circuit. In this embodiment, the voltage required to switch between high and low levels in each frame may be stored in the memory, specifically, may be in communication connection with the upper computer through the communication interface and the communication circuit, and stores the common voltage output by the upper computer. When the display device works, the digital-to-analog converter converts the digital common voltage into the analog common voltage, and the analog common voltage is amplified by the signal amplifier and then output to the corresponding first common electrode line, so that the common electrode line is applied with the high-level common electrode voltage or applied with the low-level common electrode voltage.

It is understood that the storage capacitor and the pixel capacitor are electrically connected through the pixel electrode, and parasitic capacitance, such as pixel parasitic capacitance, may exist on each sub-pixel. Therefore, when the common electrode voltage applied to the first common electrode connected to the storage capacitor is changed, the voltage across the storage capacitor is changed. The voltage is coupled among the pixel capacitor, the storage capacitor and the parasitic capacitor, so that the voltage on the pixel electrode connected with the storage capacitor and the pixel capacitor is changed, and under the condition that the common voltage on the second common electrode wire is not changed, the voltage on the pixel electrode is changed, so that the voltages at two ends of the pixel capacitor are changed, and further the brightness of the sub-pixel corresponding to the pixel capacitor is changed. In this embodiment, the common electrode voltage applied to the first common electrode is not changed between frames, for example, when the common electrode voltage on one first common electrode of a current frame is at a low level, the common electrode voltage on the first common electrode is still at the low level when scanning to a next frame. When the common voltage applied to another adjacent first common electrode is at a high level, the scanning is performed to the next frame, and the voltage on the first common electrode is still at the high level.

In one embodiment, the scan signal on each scan line in each frame comprises an on phase and an off phase;

when the scanning signal of each scanning line is in a starting stage, controlling the common electrode voltage on the first common electrode line to perform high-low level turnover switching or low-high level turnover switching;

and when the scanning signal of each scanning line is in a closing stage, controlling the voltage of the common electrode on the first common electrode line to perform secondary low-high level switching or secondary high-low level switching.

In this embodiment, in the same frame with two frames as the driving period, the scanning signal of each scanning line includes an on-phase and an off-phase, in the on-phase, the sub-pixels of the corresponding row are driven to be charged, and after the charging is completed, the gate driving circuit 30 outputs the gate off-signal, so that the sub-pixels are driven to stop charging. In this embodiment, during the on-phase, that is, during the charging of the sub-pixels in the corresponding row, the voltage of one of the two adjacent first common electrode lines is controlled to be switched from the low level to the high level, and during the off-phase, the voltage on the first common electrode line is switched from the high level to the low level, so as to implement the secondary inversion of the level. And controlling the voltage of the other one of the two adjacent first common electrode lines to be switched from high level to low level in the opening stage, and switching the voltage on the first common electrode line from low level to high level in the closing stage, thereby realizing the secondary turnover of the level.

In an embodiment, when the scan signal of each scan line is in the off phase, controlling the common electrode voltage on the first common electrode line to perform the second low-high level flip switching, or the second high-low level flip switching includes:

Or when the data voltage of the sub-pixels in the nth row and the sub-pixels in the (n +1) th row are controlled to be positive, the voltage of the common electrode of the sub-pixels in the nth row is controlled to be switched from high level to low level, and the voltage of the common electrode of the sub-pixels in the (n +1) th row is controlled to be switched from low level to high level;

Referring to fig. 1, for convenience of understanding, the principle thereof is described in detail in conjunction with the above-described embodiments. In order to describe the voltage variation and the pixel brightness variation in this embodiment in more detail, the embodiment uses the m-th row data line Dm, the n-th row and the n + 1-th row (G) scan lines_n、G_n+1) And three first common electrode wires (n) with opposite polarities^stVst1、(n+1)^stVst2、(n+2)^stVst1), the pixel driving of the entire display panel is described with reference to the present embodiment, which is not repeated herein.

Referring to fig. 3 and 5, in the first frame1 of the current driving period, when scanning to the nth row, the nth row scanning line G_nStart to operate with the scanning line G_nData voltage Data of Data line of connected sub-pixel_m-nIs positive polarity, i.e. Data voltage Data_m-n>Common electrode reference voltage Vcom, and the scan line G_m-nAfter the pixel capacitors of two adjacent rows of sub-pixels are charged, the scanning line G_nThe scanning signal of (2) is turned off; referring to the current frame pixel frame1 driving timing, the pixel holding voltage Vp at the sub-pixel connected to the mth column data line Dm and the nth row scanning line Gn is illustrated_{m-n_1}: at this time, the first common electrode line n connected to the sub-pixel^stApplied common electrode voltage Vst of Vst1_nSwitching from relatively low level to high level, wherein the pixel has parasitic capacitance, and the parasitic capacitance, the storage capacitance, and the pixel capacitance are connectedCoupling effect, so that the pixel holding voltage Vpm-n _1 of the sub-pixel is caused by the common electrode voltage Vst loaded by the first common electrode line_nBy increasing the voltage Δ V, i.e. the pixel holding voltage Vp, from a relatively low level to a high level_{m-n_1}The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x + Δ V, and the increase of the positive polarity voltage increases the luminance of the sub-pixel.

Referring to fig. 3 and 6, the scan line G_nThe pixel holding voltage Vp of another row of connected sub-pixels_{m-n_2}A first common electrode line (n +1) connected to the sub-pixel^stVst2 applied voltage signal Vst_n+1Adjacent first common electrode line n^stVst1 applied voltage signal Vst_nIs opposite, the first common electrode line (n +1)^stVst2 applied voltage signal Vst_n+1Switching from relatively high level to low level, wherein the pixel has parasitic capacitance, and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance makes the pixel holding voltage Vp of the sub-pixel_{m-n_2}Will be due to the first common electrode line (n +1)^stVst2 applied voltage signal Vst_n+1By a decrease Δ V, i.e. the pixel holding voltage Vp, from a relatively high level to a low level_{m-n_2}The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x- Δ V, and the decrease of the positive polarity voltage decreases the luminance of the sub-pixel.

Referring to fig. 3 and 7, when progressive scanning is performed to the (n +1) th row, the (n +1) th row scans a line G_n+1Start to operate with the scanning line G_n+1Data lines of connected sub-pixels_m-n+1Is positive polarity, i.e. the Data voltage Data_m-n+1>Common electrode reference voltage Vcom, and the scan line G_n+1And after the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signals are closed. Referring to the current frame pixel frame1 driving timing, the m-th column data line Dm n +1 th row scanning line G is illustrated_n+1Pixel holding voltage Vp of connected sub-pixels_{m-n+1_1}: at this time, the first common line connected to the sub-pixelElectrode line (n +1)^stThe applied voltage signal Vstn +1 of Vst2_{_1}And the last adjacent sub-pixel Vp_{m-n_2}One first common electrode line is shared. The first common electrode voltage Vstn +1 is switched from a relatively high level to a low level, and the pixel holding voltage Vp of the sub-pixel is caused by the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance_{m-n+1_1}The voltage signal Vst loaded by the common electrode line_n+1By a decrease Δ V, i.e. Vp, from a relatively high level to a low level_{m-n+1_1}The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x- Δ V, and the decrease of the positive polarity voltage decreases the luminance of the sub-pixel.

Referring to fig. 3 and 8, the scanning line G_n+1The pixel holding voltage Vp of another row of connected sub-pixels_{m-n+1_2}A first common electrode line (n +2) connected to the sub-pixel^stVst1 applied voltage signal Vst_n+2Adjacent first common electrode line (n +1)^stVst2 applied voltage signal Vst_n+1Is opposite, the first common electrode line (n +2)^stVst1 applied voltage signal Vst_n+2Switching from relatively low level to high level, wherein the pixel holding voltage Vp of the sub-pixel is caused by coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance due to the parasitic capacitance of the pixel_{m-n+1_2}Will be due to the first common electrode line (n +2)^stVst1 applied voltage signal Vst_n+2By an increase of Δ V, i.e. Vp, from a relatively low level to a high level_m-n+2The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x + Δ V, and the increase of the positive polarity voltage increases the luminance of the sub-pixel.

Referring to fig. 4 and 5, in the second frame2 of the current driving period, when scanning to the nth row, the nth row scanning line G_nStart to operate with the scanning line G_nData lines of connected sub-pixels_m-nHas a negative polarity, i.e. the Data voltage Data_m-n<The common electrode reference voltage Vcom is set to a common electrode reference voltage Vcom,and the scanning line G_m-nAfter the pixel capacitors of two adjacent rows of sub-pixels are charged, the scanning line G_nThe scanning signal of (2) is off. Referring to the current frame pixel frame2 driving timing, the pixel holding voltage Vp at the sub-pixel connected to the nth row of the mth column data line is illustrated_{m-n_1}: at this time, the common electrode voltage on the first common electrode line of the current frame has the same polarity as the common electrode voltage of the previous frame, and thus, at the scan line G_mWhen the scanning signal is turned off, the first common electrode line n connected with the sub-pixel^stApplied common electrode voltage Vst of Vst1_nFrom a relatively low level to a high level. The pixel holding voltage Vp of the sub-pixel is caused by the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance_{m-n_1}Will be caused by the first common electrode line n^stThe common electrode voltage Vstn applied by Vst1 is switched from a relatively low level to a high level and increases by Δ V, i.e. the pixel holding voltage Vp_{m-n_1}The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x + Δ V, and the increase of the negative polarity voltage decreases the luminance of the sub-pixel.

Referring to fig. 4 and 6, the scanning line G_nThe pixel holding voltage Vp of another row of connected sub-pixels_{m-n_2}A first common electrode line (n +1) connected to the sub-pixel^stVst2 applied voltage signal Vst_{m-n_2}Adjacent first common electrode line n^stVst1 applied voltage signal Vst_nAnd the common electrode voltage on the first common electrode line of the current frame has the same polarity as the common electrode voltage of the previous frame, so the first common electrode line (n +1)^stVst2 applied voltage signal Vst_n+1From a relatively low level to a high level. At this time, the pixel holding voltage Vp of the sub-pixel is also due to the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance_{m-n_2}The voltage signal Vst loaded by the second common electrode line_n+1By a decrease of a from a relatively high level to a low levelV, i.e. Vp_{m-n_2}The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x- Δ V, and the increase of the negative polarity voltage increases the brightness of the sub-pixel.

Referring to fig. 4 and 7, when progressive scanning is performed to the (n +1) th row, the (n +1) th row scans a line G_n+1Start to operate with the scanning line G_n+1Data lines of connected sub-pixels_m-n+1Is a negative polarity, i.e. the Data voltage Data_m-n+1<Common electrode reference voltage Vcom, and the scan line G_n+1After the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signal is turned off, and the timing sequence is driven by referring to the current frame pixel frame2, which indicates the n +1 th row of scanning line G of the m column data line Dm_n+1Pixel holding voltage Vp of connected sub-pixels_{m-n+1_1}The sub-pixel and the previous adjacent sub-pixel share a first common electrode line (n +1)^st Vst 2. The first common electrode voltage Vst_{n+1_1}When the voltage level is switched from a relatively high level to a low level, the pixel holding voltage Vp of the sub-pixel is caused by the parasitic capacitance of the sub-pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance_{m-n+1_1}The voltage signal Vst loaded by the common electrode line_n+1By Δ V, i.e. Vp, decreasing from a relatively low level to a high level_{m-n+1_1}The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x- Δ V, and the decrease of the negative polarity voltage increases the brightness of the sub-pixel.

Referring to fig. 4 and 8, the scanning line G_n+1The pixel holding voltage Vp of another row of connected sub-pixels_{m-n+1_2}A first common electrode line (n +2) connected to the sub-pixel^stVst1 applied voltage signal Vst_n+2Adjacent first common electrode line (n +1)^stVst2 applied voltage signal Vst_n+1Is opposite, the first common electrode line (n +2)^stVst1 applied voltage signal Vst_n+2Switching from relatively high level to low level due to parasitic capacitance of pixel and coupling effect among parasitic capacitance, storage capacitance and pixel capacitanceThe pixel holding voltage Vp of the sub-pixel_{m-n+1_2}Will be due to the first common electrode line (n +2)^stVst1 applied voltage signal Vst_n+2By increasing Δ V, i.e. Vp, from a relatively high level to a low level_{m-n+1_2}The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x + Δ V, and the increase of the negative polarity voltage decreases the luminance of the sub-pixel.

In one embodiment, the polarities of the data voltages on the two adjacent columns of data lines are opposite.

In this embodiment, the sub-pixels in adjacent rows can be arranged in positive and negative polarities, and the two sub-pixels in the same row and the two sub-pixels in adjacent rows in each pixel group are connected to a data line, so that the polarities of the two sub-pixels in the same row are different, and the polarities of the two adjacent sub-pixels in the same row are also different. By the arrangement, the display of the resolution in the display panel space is increased, and the defect of color cast of the display panel visual angle is improved. In addition, the invention adopts the design of sharing the scanning lines and the common electrode lines, reduces half of the scanning driving electrodes and the common electrode driving electrodes, increases the effective aperture opening rate of the display panel and improves the penetration rate.

In an embodiment, the driving method of the display panel further includes:

In this embodiment, it can be understood that the scanning manner of the gate driving circuit to the display panel is generally progressive scanning to complete pixel scanning of the sub-pixels in all rows, and when the sub-pixels in the current row are scanned, the pixel capacitance of each sub-pixel is charged. The polarity of the data voltage of the two rows of sub-pixels in the current group is opposite to that of the data voltage of the two rows of sub-pixels in the next group and the data voltage of the two rows of sub-pixels in the next group. For example, when the polarity of the data voltage of the two rows of sub-pixels of the previous group is positive (or negative), the data voltage of the two rows of sub-pixels of the next group is switched to negative (or positive) when the two rows of sub-pixels of the next group are scanned.

Referring to fig. 3 and 5, in the first frame1 of the current driving period, when scanning to the nth row, the nth row scanning line G_nStart to operate with the scanning line G_nData lines of connected sub-pixels_m-nIs positive polarity, i.e. Data voltage Data_m-n>Common electrode reference voltage Vcom, and the scan line G_m-nAfter the pixel capacitors of two adjacent rows of sub-pixels are charged, the scanning line G_nThe scanning signal of (2) is turned off; referring to the current frame pixel frame1 driving timing, the pixel holding voltage Vp at the sub-pixel connected to the mth column data line Dm and the nth row scanning line Gn is illustrated_{m-n_1}: at this time, the first common electrode line n connected to the sub-pixel^stApplied common electrode voltage Vst of Vst1_nWhen the pixel voltage is switched from a relatively low level to a high level, due to the existence of parasitic capacitance of the pixel, the parasitic capacitance, the storage capacitance and the pixel capacitance are coupled, so that the pixel holding voltage Vpm-n _1 of the sub-pixel is boosted up by Δ V due to the switching of the common electrode voltage Vstn loaded by the first common electrode line from a relatively low level to a high level, i.e. the pixel holding voltage Vp_{m-n_1}The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x + Δ V, and the increase of the positive polarity voltage increases the luminance of the sub-pixel.

Referring to fig. 3 and 6, the scan line G_nThe pixel holding voltage Vp of another row of connected sub-pixels_{m-n_2}A first common electrode line (n +1) connected to the sub-pixel^stVst2 applied voltage signal Vst_n+1Adjacent first common electrode line n^stVst1 applied voltage signal Vst_nIs opposite, the voltage signal Vst applied to the first common electrode line Vst2 is_n+1Switching from relatively high level to low level, wherein the pixel holding voltage Vp of the sub-pixel is caused by coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance due to the parasitic capacitance of the pixel_{m-n_2}Will be due to the first common electrode line (n +1)^stVst2 applied voltage signal Vst_n+1By a decrease Δ V, i.e. the pixel holding voltage Vp, from a relatively high level to a low level_{m-n_2}The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x- Δ V, and the decrease of the positive polarity voltage decreases the luminance of the sub-pixel.

Referring to fig. 3 and 7, when progressive scanning is performed to the (n +1) th row, the (n +1) th row scans a line G_n+1Starting to work, the scanning line is connected with a group of sub-pixel groups, the polarities of the data voltages of the sub-pixel groups and the sub-pixel groups of the previous group are switched, so that the scanning line is connected with the scanning line G_n+1Data lines of connected sub-pixels_m-n+1Is a negative polarity, i.e. the Data voltage Data_m-n+1<Common electrode reference voltage Vcom, and the scan line G_n+1And after the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signals are closed. Referring to the current frame pixel frame1 driving timing, the m-th column data line Dm n +1 th row scanning line G is illustrated_n+1Pixel holding voltage Vp of connected sub-pixels_{m-n+1_1}: at this time, the first common electrode line (n +1) is shared with the sub-pixel and the previous adjacent sub-pixel^stVst 2. The first common electrode voltage Vst_n+1Switching from relatively high level to low level, due to existence of parasitic capacitance of pixel and coupling effect among parasitic capacitance, storage capacitance and pixel capacitance, the pixel holding voltage Vp of the sub-pixel is enabled_{m-n+1_1}The voltage signal Vst loaded by the common electrode line_{m-n+1_1}By a decrease Δ V, i.e. Vp, from a relatively high level to a low level_{m-n+1_1}Common electrode reference voltage Vcom on the side of the second common electrode lineThe voltage difference between the positive and negative polarities is changed from-x to-x- Δ V, and the decrease of the negative polarity voltage increases the brightness of the sub-pixel.

Referring to fig. 3 and 8, the scanning line G_n+1The pixel holding voltage Vp of another row of connected sub-pixels_{m-n+1_2}A first common electrode line (n +2) connected to the sub-pixel^stVst1 applied voltage signal Vst_n+2Adjacent first common electrode line (n +1)^stVst2 applied voltage signal Vst_n+1Is opposite, the first common electrode line (n +2)^stVst1 applied voltage signal Vst_n+2From a relatively low level to a high level. At this time, due to the existence of parasitic capacitance of the pixel, the pixel holding voltage Vp of the sub-pixel is caused by the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance_{m-n+1_2}The voltage signal Vst loaded by the common electrode line_n+2By an increase of Δ V, i.e. Vp, from a relatively low level to a high level_{m-n+1_2}The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from x to-x + Δ V, and the increase of the negative polarity voltage decreases the luminance of the sub-pixel.

Referring to fig. 4 and 5, in the second frame2 of the current driving period, when scanning to the nth row, the nth row scanning line G_nStart to operate with the scanning line G_nData lines of connected sub-pixels_m-nHas a negative polarity, i.e. the Data voltage Data_m-n<Common electrode reference voltage Vcom, and the scan line G_m-nAfter the pixel capacitors of two adjacent rows of sub-pixels are charged, the scanning line G_nThe scanning signal of (2) is turned off; referring to the current frame pixel frame1 driving timing, the nth row scanning line G is illustrated as being connected to the mth column data line Dm_nPixel holding voltage Vp across connected subpixels_{m-n_1}: at this time, the first common electrode line n connected to the sub-pixel^stVst1 applied common electrode voltage Vst_nFrom a relatively low level to a high level. Due to the existence of parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance, the pixel holding voltage Vp of the sub-pixel is enabled to be_{m-n_1}Will be caused by the first common electrode line n^stVst1 applied common electrode voltage Vst_nBy an increase Δ V from a relatively low level to a high level, i.e. the pixel holding voltage Vp_{m-n_1}The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x + Δ V, and the increase of the negative polarity voltage decreases the brightness of the sub-pixel.

Referring to fig. 4 and 6, the scanning line G_m-nThe pixel holding voltage Vp of another row of connected sub-pixels_{m-n_2}A first common electrode line (n +1) connected to the sub-pixel^stVst2 applied voltage signal Vst_n+1Adjacent first common electrode line n^stVst1 applied voltage signal Vst_nAnd the common electrode voltage on each first common electrode line of the current frame has the same polarity as the first common electrode voltage of the previous frame, so the first common electrode line (n +1)^stVst2 applied voltage signal Vst_n+1From a relatively low level to a high level. Due to the existence of parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance, the pixel holding voltage Vp of the sub-pixel_{m-n_2}Will be due to the first common electrode line (n +1)^stVst2 applied voltage signal Vst_n+1By a decrease Δ V, i.e. Vp, from a relatively high level to a low level_{m-n_2}The voltage difference between the common electrode reference voltage Vcom and the second common electrode line side becomes x + Δ V from x, and the increase of the negative polarity voltage increases the luminance of the sub-pixel.

Referring to fig. 4 and 7, when progressive scanning is performed to the (n +1) th row, the (n +1) th row scans a line G_n+1Starting to work, the scanning line is connected with a group of sub-pixel groups, the polarities of the data voltages of the sub-pixel groups and the sub-pixel groups of the previous group are switched, so that the scanning line is connected with the scanning line G_n+1Data lines of connected sub-pixels_m-n+1Is positive polarity, i.e. the Data voltage Data_m-n+1>The common electrode reference voltage Vcom. Referring to the current frame pixel frame2 driving timing, the m-th column data line Dm n +1 th row scanning line G is illustrated_n+1Connected byPixel holding voltage Vp of sub-pixel_{m-n+1_1}At the scanning line G_n+1And after the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signals are closed. The sub-pixel and the previous adjacent sub-pixel share a first common electrode line (n +1)^stVst2, the common electrode voltage on the first common electrode line of the current frame has the same polarity as the common electrode voltage of the previous frame, and the first common electrode voltage Vst_{m-n+1_1}Switching from a relatively high level to a low level. Due to the existence of parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance, the pixel holding voltage Vp of the sub-pixel is enabled to be_{m-n+1_1}Will be due to the first common electrode line (n +1)^stVst2 applied voltage signal Vst_{m-n+1_1}By a decrease Δ V, i.e. Vp, from a relatively high to low level_{m-n+1_1}The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x- Δ V, and the decrease of the positive polarity voltage decreases the luminance of the sub-pixel.

Referring to fig. 4 and 8, the scanning line G_n+1The pixel holding voltage Vp of another row of connected sub-pixels_{m-n+1_2}A first common electrode line (n +2) connected to the sub-pixel^stVst1 applied voltage signal Vst_n+2Adjacent first common electrode line (n +2)^stVst1 applied voltage signal Vst_n+2Is opposite, the first common electrode line (n +1)^stVst2 applied voltage signal Vst_n+1Switching from relatively low level to high level, wherein the pixel holding voltage Vp of the sub-pixel is generated due to the existence of parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance_{m-n+1_2}Will be due to the first common electrode line (n +2)^stVst1 applied voltage signal Vst_n+2By increasing Δ V, i.e. Vp, from a relatively high level to a low level_{m-n+1_2}The voltage difference between the common electrode reference voltage Vcom and the second common electrode line side becomes x + Δ V from x, and increasing the increase of the polarity voltage increases the luminance of the sub-pixel.

In an embodiment, the driving method of the display panel further includes:

and performing column inversion driving on each sub-pixel.

In this embodiment, each of the sub-pixel groups includes two rows of sub-pixels, the two rows of sub-pixels are connected to a scan line, the storage capacitors of the two rows of sub-pixels are respectively connected to a driving structure of a first common electrode line Vstn, Vstn +1, and the data signals are driven by dot inversion in a column inversion manner, so that the application also avoids the need of switching the positive and negative polarities when the data voltages on the same data line are scanned line by line, so that the distortion of the data voltage signal due to the existence of the pixel parasitic capacitance is reduced, and solves the problem that the data voltage of the source driver needs to be switched between positive polarity and negative polarity continuously when the line-by-line scanning is performed, the display device generates large power consumption due to the large voltage switching frequency, and the driving chip may be damaged due to the high temperature in severe cases.

In an embodiment, the specific step of controlling the common electrode voltage level on the first common electrode line to switch between high and low after the charging of the pixel capacitors of the sub-pixels in the corresponding row is completed includes:

in a first frame of a current driving period, after pixel capacitance charging of the sub-pixels of a corresponding row is completed, setting the first common electrode voltage as a first level common electrode voltage; setting the common electrode voltage to a second level common electrode voltage in a second frame of a current driving period.

The first level common electrode voltage is a high level common electrode voltage, and the second level common electrode voltage is a low level common electrode voltage; or, the first level common electrode voltage is a low level common electrode voltage, and the second level common electrode voltage is a high level common electrode voltage.

In one embodiment, the data line voltages of two adjacent columns are opposite in polarity.

In this embodiment, the sub-pixels in adjacent rows may be arranged in positive and negative polarities, and the two sub-pixels in the same row and the two sub-pixels in adjacent rows in each pixel group are connected to a data line, so that the polarities of the two sub-pixels in the same row are different, and the polarities of the two adjacent sub-pixels in the same row are also different. By the arrangement, the display of the resolution in the display panel space is increased, and the defect of color cast of the display panel visual angle is improved. In addition, the invention adopts the design of sharing the scanning lines and the common electrode lines, reduces half of the scanning driving electrodes and the common electrode driving electrodes, increases the effective aperture opening rate of the display panel and improves the penetration rate.

In an embodiment, the driving method of the display panel further includes:

and performing column inversion driving on each sub-pixel.

In this embodiment, each of the sub-pixel groups includes two rows of sub-pixels, the two rows of sub-pixels are connected to a scan line, the storage capacitors of the two rows of sub-pixels are respectively connected to a driving structure of a first common electrode line Vstn, Vstn +1, and the data signal Datam is driven by dot inversion in a column inversion manner, which avoids the need of switching the positive and negative polarities during the line-by-line scanning of the data voltage on the same data line, so that the distortion of the data voltage signal due to the existence of the pixel parasitic capacitance is reduced, and solves the problem that the data voltage of the source driver needs to be switched between positive polarity and negative polarity continuously when the line-by-line scanning is performed, the display device generates large power consumption due to the large voltage switching frequency, and the driving chip may be damaged due to the high temperature in severe cases.

two data lines which are positioned in the same row and are respectively connected with two adjacent sub-pixel groups are adjacent, and two data lines which are positioned in the adjacent row and are respectively connected with two adjacent sub-pixel groups are adjacent; and the polarities of the voltages on the two adjacent first common electrode lines are opposite.

Wherein the voltage polarity on the first common electrode lines (Vst1, Vst2) respectively connected to the storage capacitances (Cst1, Cst2) of the two rows of the sub-pixels is opposite; the data voltage polarities of the data lines (Dm-1, Dm +1) of the two sub-pixels positioned in the same column in each group are the same, and the voltage polarities of the data lines (Dm-1, Dm +1) of the two sub-pixels positioned in the adjacent columns in the same row are opposite.

In this embodiment, the display panel is provided with a pixel array (not shown), a scan line (Gn, Gn +1), a data line (Dm-1, Dm +1), a first common electrode line Vst1 and a second common electrode line Vcom, and the pixel array includes a plurality of sub-pixels. Each sub-pixel comprises an active switch (thin film transistor), a pixel capacitor Clc and a storage capacitor Cst, the gate of the active switch is electrically connected to the corresponding scan line (Gn, Gn +1) of the sub-pixel, the source of the active switch is electrically connected to the corresponding data line D of the sub-pixel, the drain of the active switch is electrically connected to one end of the pixel capacitor Clc and the storage capacitor Cst of the sub-pixel through the data line D, and the other end of each pixel capacitor Clc is electrically connected to the second common electrode line Vcom. In the present embodiment, two rows of sub-pixels are defined as a sub-pixel group 10, and the other ends of the storage capacitors Cst of the two sub-pixel groups 10 are respectively connected to a first common electrode line Vst 1. Wherein each sub-pixel is divided into three sub-pixel groups 10 of red, green and blue. Every three sub-pixels of red, green and blue form a pixel. A plurality of thin film transistors constitute the thin film transistor array of the present embodiment.

Referring to FIG. 1, in FIG. 1, Gn and Gn +1 are schematically shown as two adjacent rows of scan lines, Dm-1, Dm,Dm +1 is illustrated as three adjacent columns of data lines, n^stVst1、(n+1)^stVst2、(n+2)^stThree first common electrode lines adjacent to Vst1, Clc1 and Clc2, which represent pixel capacitances connected to the same scan line in the same group, and Cst1 and Cst2, which represent storage capacitances connected to different first common motor lines in the same group, respectively.

The driving device of the display panel further includes:

a source driver circuit 20, a plurality of output terminals of the source driver circuit 20 being connected to each of the data lines, the source driver circuit 20 being configured to output a data voltage with positive and negative polarities switched to each of the data lines in a driving cycle of two frames;

a common electrode voltage circuit 50, an output terminal of the common electrode voltage circuit 50 being connected to each of the first common electrode lines, the common electrode voltage circuit 50 being configured to output a common electrode voltage having a same polarity as a common electrode voltage of a previous frame to each of the first common electrode lines;

the driving apparatus of the display panel is further provided with a processor, a memory (not shown in the figure), and a driver of the display panel stored on the memory and operable on the processor, the driver of the display panel being configured to implement the steps of the driving method of the display panel as described above.

In this embodiment, the processor may be a timing controller 10, the timing controller 10 is connected to the source driving circuit 20 and the gate driving circuit 30 respectively to provide timing control signals for the source driving circuit 20 and the gate driving circuit 30, in this embodiment, timing signals for controlling the data voltages on the data lines to switch the positive and negative polarities in a driving period of two frames are stored in the timing controller 10, in the driving of each frame, the timing controller 10 receives image data of a picture to be displayed sent from the front end, and the timing controller 10 converts the image data and the control signals received from the front end into data signals, control signals and clock signals suitable for the source driver 20 and the gate driver 30. The source driver 20 converts the received digital signals into corresponding gray scale voltage signals, when the gate driver 30 scans line by line, all the column data signal lines transmit data signals to the pixel row, and charge the capacitors of the sub-pixels in the pixel row, so as to implement writing and maintaining of the signal voltage of the pixel, and the liquid crystal molecules of the sub-pixels rotate under the voltage, so that the transmittance of incident light passing through the liquid crystal molecules is changed, that is, the light valve effect on the incident light is implemented, the change of the brightness of the incident light is implemented, and finally, the image display of the display panel 100 is implemented. The signals Output to the gate driver include a Start Vertical (STV) signal, a Clock Pulse Vertical (CPV) signal, an Enable signal (OE), and the like.

Common electrode voltage circuit 50 and first common electrode line (n)^stVst1、(n+1)^stVst2、(n+2)^stVst1) and a second common electrode line Vcom to provide a common electrode reference voltage for the second common electrode line Vcom, and the common electrode voltage circuit 50 also provides two adjacent first common electrode lines (n)^stVst1、(n+1)^stVst2、(n+2)^stVst1) and the common electrode voltage circuit 50 controls the common electrode voltages on the adjacent two first common electrode lines to perform polarity inversion with two frames as a driving period.

Referring to fig. 2, in some embodiments, the memory may be implemented using an EEPROM (Electrically Erasable Programmable read only memory) or a Flash memory Flash. The memory, the Timing Controller 10 and the common electrode circuit 50 may be disposed on a Timing Controller (TCON) PCB, the memory may store control signals for driving the gate driver 20 and the source driver 30 to operate, and is in communication connection with the Timing Controller 10 through a serial communication bus, and when the display device is powered on and operated, the Timing Controller 10 reads the control signals in the memory and performs initial setting on other set data to generate corresponding Timing control signals, so as to drive the display panel 100 in the display device to operate, that is, the data stored in the memory is the initialization data of the display panel 100.

In an embodiment, the driving apparatus of the display panel further includes a gate driving circuit 30, and the gate driving circuit 30 is connected to the gate of each of the sub-pixels; the gate driving circuit 30 is configured to output a gate driving signal to each row of sub-pixels, so that corresponding voltages are applied to the second common electrode and the data line, and charging of the sub-pixel capacitors in the corresponding row is achieved.

Referring to fig. 2, in an embodiment, the driving circuit of the display panel further includes a gamma circuit 60 configured to generate a plurality of gamma voltages and output the gamma voltages to the source driver 30, and the source driver 30 charges corresponding pixels according to the timing control signal and the gamma voltages output by the timing controller 10, so that the source driver 30 outputs data signals to the corresponding pixels to display an image to be displayed. The gamma circuit 60 may be implemented by a programmable gamma chip, or by discrete components such as a resistor string and a memory, and may generate a set of gamma voltages (V γ 1 to V γ 14) that can be used as pixel grayscale reference voltages.

Referring to fig. 5, in an embodiment, the display panel 100 further includes:

a first substrate 110 having a display area AA and a peripheral area, i.e., a non-display area BB; the pixel array 140 is disposed on the first substrate 110 and located in the display area AA; the N array substrate row driving circuits 10 and the auxiliary circuits 20 arranged in cascade are arranged on the first substrate 110 and located in the peripheral region;

a second substrate 120 disposed opposite to the first substrate 110;

the liquid crystal layer 130 is disposed between the first substrate 110 and the second substrate, the liquid crystal layer 130 includes a plurality of liquid crystal molecules, and the pixel array 140 is configured to control the actions of the plurality of liquid crystal molecules.

In this embodiment, the first substrate 110 and the second substrate are both generally transparent substrates such as glass substrates or plastic substrates. The second substrate is disposed opposite to the first substrate 110, and a corresponding circuit may be disposed between the first substrate 110 and the second substrate. The first substrate 110 is an array substrate, the second substrate is a color film substrate, and the first substrate 110 and the second substrate may be flexible transparent substrates. The pixel array 140 is disposed on the first substrate 110 and located in the display area AA.

It is understood that, in the above embodiment, the display panel 100 further includes the sealant 150 disposed in the display area BB between the first substrate 110 and the second substrate 120 and surrounding the liquid crystal layer 130, and the array substrate row driving circuit 10 is located between the sealant 150 and the display area AA. The sealant 150 may be coated on the first substrate 110 or the second substrate 120 by using a sealant to connect the first substrate 110 and the second substrate 120, so as to implement the assembling process of the display panel 100.

The display panel is divided into a System On Chip (SOC) type and a Gate On Array (GOA) type by a Gate driver design (Gate driver design). The GOA directly manufactures a Gate driver IC (Gate driver IC) on an Array substrate of a display device, instead of a process technology of manufacturing a driver chip from an external silicon chip. The application of the technology can reduce the production process procedures, reduce the product process cost and improve the integration level of the display panel. With the development of liquid crystal televisions and computers towards the direction of super-large size and high resolution, more and more liquid crystal display panels adopt narrow-frame design to increase the display area of the display screen.

The GOA is generally disposed at a side frame of the display panel, and a gate line scanning driving signal circuit is fabricated on an array substrate of the display panel by using a Thin Film Transistor (TFT) liquid crystal display array process to realize a driving method of scanning a gate line by line, which has the advantages of reducing production cost and realizing a narrow frame design of the panel, and is used for various displays. In an exemplary architecture of the GOA-type display panel, LC (Liquid Crystal) molecules are filled between upper and lower glass substrates and sealed with a sealing material at the periphery; among them, liquid crystal is a polymer material, and is widely used in light and thin display technologies due to its special physical, chemical and optical properties. According to the size of the display panel, the GOA circuits may be disposed on one side of the display panel, or on both sides of the display panel, and when disposed on both sides of the display panel, the GOA circuits on both sides may simultaneously drive one row of sub-pixels to be turned on, or alternatively control each row of sub-pixels to be turned on.

The invention also comprises a display device, which comprises a display panel and the driving device of the display panel, wherein the driving device of the display panel is connected with each sub-pixel of the display panel. The detailed structure of the driving device of the display panel can refer to the above embodiments, and is not described herein again; it can be understood that, since the display device of the present invention uses the driving device of the display panel, the embodiment of the display device of the present invention includes all the technical solutions of all the embodiments of the driving device of the display panel, and the achieved technical effects are also completely the same, and are not described herein again.

In the above embodiments, the display panel includes, but is not limited to, a liquid crystal display panel, an organic light emitting diode display panel, a field emission display panel, a plasma display panel, a curved panel, and the liquid crystal panel includes a thin film transistor liquid crystal display panel, a TN panel, a VA panel, an IPS panel, and the like.

The above description is only an alternative embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. A driving method of a display panel, the display panel comprising:

and controlling the common electrode voltage on each first common electrode line and the common electrode voltage of the previous frame to be switched in a high-low level driving mode to maintain the same polarity.

2. The method for driving a display panel according to claim 1, wherein the scanning signal on each of the scanning lines in each frame comprises an on phase and an off phase;

3. The method according to claim 2, wherein the step of controlling the common electrode voltage on the first common electrode line to perform the second high-low level inversion switching when the scan signal of each scan line is in the off phase comprises:

4. The method according to claim 2, wherein the step of controlling the common electrode voltage on the first common electrode line to perform the second high-low level inversion switching when the scan signal of each scan line is in the off phase specifically comprises:

5. The display panel driving method according to claim 2, wherein the display panel driving method further comprises:

6. The method for driving a display panel according to claim 1, wherein the data voltages on the data lines of two adjacent columns have opposite polarities.

7. The method of driving a display panel according to any one of claims 1 to 5, further comprising:

and driving the same data line with the same polarity to form point inversion driving on each group of sub-pixels of the display panel.

8. A driving apparatus of a display panel, the display panel comprising:

the polarities of the voltages on the two adjacent first common electrode lines are opposite, and the polarities of the data voltages on the data lines of the sub-pixels in each group on the same data line are the same; the driving device of the display panel includes:

the driving apparatus of a display panel is further provided with a processor, a memory, and a driver of a display panel stored on the memory and operable on the processor, the driver of the display panel being configured to implement the steps of the driving method of a display panel according to any one of claims 1 to 7.

9. The driving apparatus of a display panel according to claim 8, further comprising a gate driving circuit connected to a gate of each of the sub-pixels; the gate driving circuit is configured to output a gate driving signal to each row of sub-pixels, so that corresponding voltages are applied to the second common electrode and the data line, and the sub-pixel capacitors in the corresponding row are charged;

the driving device of the display panel further comprises a time sequence controller, and the time sequence controller is respectively connected with the grid driving circuit and the source driving circuit; the timing controller is configured to output a timing control signal to the gate driving circuit and the source driving circuit.

10. A display device comprising a display panel and a driving device of the display panel according to any one of claims 8 or 9, the driving device of the display panel being connected to each sub-pixel of the display panel.