CN113377584B

CN113377584B - Electronic control device

Info

Publication number: CN113377584B
Application number: CN202110235913.1A
Authority: CN
Inventors: 古桥里志
Original assignee: Honda Motor Co Ltd
Current assignee: Honda Motor Co Ltd
Priority date: 2020-03-10
Filing date: 2021-03-03
Publication date: 2024-05-03
Anticipated expiration: 2041-03-03
Also published as: CN113377584A; JP2021144261A

Abstract

The present invention provides an electronic control device (10A) mounted on a vehicle (1), comprising: a plurality of cores (11, 12, 13) each performing an arithmetic process; a shared memory (14) which is accessible by a plurality of cores (11, 12, 13); and a communication unit (114) that communicates with an external device via a communication network. A plurality of types of data are transmitted and received between the communication unit (114) and the external devices (10B, 10C). The shared memory (14) stores data corresponding to any of a plurality of types among data obtained by the arithmetic processing of a plurality of cores (11, 12, 13).

Description

Electronic control device

Technical Field

The present invention relates to an electronic control device for controlling a vehicle.

Background

As such a device, a device having a processor (hereinafter referred to as a multi-core processor) with a plurality of cores mounted therein is known in order to improve processing performance (see, for example, patent document 1). In the device described in patent document 1, each core transfers data via a shared memory provided in a processor.

However, as in the device described in patent document 1, if a single core is configured to use data stored in the shared memory for processing by another core, if an abnormality occurs in the single core, the processing by the other core may not be performed normally.

Prior art literature

Patent literature

Patent document 1: japanese patent application laid-open No. 2008-123031.

Disclosure of Invention

An electronic control device according to an aspect of the present invention is an electronic control device mounted on a vehicle, comprising: a plurality of cores each performing an operation process; a shared memory that is accessible by a plurality of cores; and a communication unit that communicates with an external device via a communication network. The communication unit transmits and receives a plurality of types of data to and from the external device, and the shared memory stores data corresponding to any of the plurality of types of data obtained by the arithmetic processing of the plurality of cores.

Drawings

The objects, features and advantages of the present invention are further elucidated by the following description of embodiments in connection with the accompanying drawings.

Fig. 1A is a diagram schematically showing an example of a configuration of a vehicle control device to which an electronic control device according to an embodiment of the present invention is applied.

Fig. 1B is a diagram showing a schematic configuration of the electronic control device of fig. 1A.

Fig. 2 is a diagram showing a functional configuration of each core of the electronic control device of fig. 1B.

Fig. 3 is a diagram schematically illustrating an example of the operation of each core of the electronic control device of fig. 1B.

Fig. 4 is a flowchart showing the operation of each core of the electronic control device according to the embodiment of the present invention.

Detailed Description

Embodiments of the present invention will be described below with reference to fig. 1A to 4. The electronic control device according to the embodiment of the invention is applied to a vehicle control device that controls a vehicle.

First, the configuration of a vehicle control device to which the electronic control device of the present embodiment is applied will be described. Fig. 1A is a diagram schematically showing an example of a configuration of a vehicle control device to which an electronic control device according to an embodiment of the present invention is applied. As shown in fig. 1A, the vehicle control device 100 is mounted on the vehicle 1. The vehicle control device 100 is connected to an engine 3, a transmission 4, and an Electric Power Steering (EPS) device 5 mounted on the vehicle 1, and controls these devices. The vehicle 1 may be equipped with devices other than the engine 3, the transmission 4, and the EPS device 5, and those devices may be connected to the vehicle control device 100.

The vehicle control device 100 includes a plurality of electronic control devices 10A, 10B, and 10C that are communicably connected to each other via the in-vehicle communication network 2. In the present embodiment, the electronic control devices 10A, 10B, and 10C are ECUs (Electric Control Unit: electronic control unit).

The in-vehicle communication network 2 is a CAN (Controller Area Network: controller area network). Hereinafter, the electronic control devices 10A, 10B, 10C are labeled as ECU10A, ECU10B, ECU C. The in-vehicle communication network 2 is denoted as CAN2.

Next, a schematic configuration of the ECU10A, ECU10B, ECU C of fig. 1A will be described. The configuration of the ECU10A, ECU10B, ECU C is the same, and therefore, the configuration of the ECU10A will be described here. Fig. 1B is a diagram showing a schematic configuration of the ECU10A of fig. 1A.

As shown in fig. 1B, the ECU10A mounts a multicore processor 15 having a plurality of cores 11 to 13 and a shared memory 14 that is accessible to the plurality of cores 11 to 13, respectively. In the present embodiment, the processing required for the control of the transmission 4 is executed by the core 11, the processing required for the control of the engine 3 is executed by the core 12, and the processing required for the control of the EPS device 5 is executed by the core 13. The cores may share processing required for performing control of a single device.

Next, the functional configuration of the cores 11 to 13 of the ECU10A will be described. Fig. 2 is a diagram showing the functional configuration of each core of the ECU10A of fig. 1B. First, the functional structure of the core 11 is explained.

As shown in fig. 2, the core 11 includes an arithmetic unit 111, an abnormality determination unit 112, a control unit 113, and a communication unit 114. The core 11 includes a storage unit (not shown) such as a ROM or a RAM, and functions as the arithmetic unit 111, the abnormality determination unit 112, the control unit 113, and the communication unit 114 by executing a program stored in the storage unit.

The calculation unit 111 performs calculation processing using parameters acquired from an external sensor (a sensor group 20 shown in fig. 3 described later) connected to the vehicle control device 100 and parameters stored in the shared memory 14. The arithmetic unit 111 stores data (arithmetic result data) indicating the arithmetic result obtained by the arithmetic processing in the shared memory 14. The external sensors are various sensors mounted on the vehicle 1, such as a rudder angle sensor, a vehicle speed sensor, and a yaw rate sensor.

The anomaly determination unit 112 determines whether or not an anomaly has occurred in another core. In the present embodiment, the cores 12 and 13 have an abnormality detection function, and when an abnormality occurs in their own cores, a signal indicating the occurrence of the abnormality (hereinafter referred to as an abnormality occurrence signal) is output to the core 11 via a dedicated bus (not shown). When the abnormality occurrence signals from the cores 12 and 13 are inputted, the abnormality determination unit 112 determines that an abnormality has occurred in the core of the input source.

The abnormality determination unit 112 determines whether or not an abnormality has occurred in its own core. As a method for detecting an abnormality of the core itself by the abnormality determination unit 112, a method in which a core (not shown) that performs the same processing as the core 11 is mounted in advance in the ECU10A, and an abnormality of the core 11 is detected by a Lock Step (Lock Step), or the like, may be considered, but other methods may be used.

When it is determined that an abnormality has occurred in the core itself or another core, the abnormality determination unit 112 outputs a signal indicating that the abnormality has occurred to the other core via a dedicated bus not shown. Hereinafter, this signal will be referred to as an abnormality notification signal.

The control unit 113 controls the transmission 4 based on data acquired from an external sensor and calculation result data of the calculation unit 111.

When the calculation unit 111 saves the calculation result data in the shared memory 14, the communication unit 114 reads the calculation result data from the shared memory 14 and transmits the calculation result data to the other ECU via the CAN 2. The communication unit 114 reads out the calculation result data from the shared memory 14 and transmits the calculation result data to the other ECU via the CAN2 even when the calculation unit 121 of the core 12 and the calculation unit 13 of the core 13 store the calculation result data in the shared memory 14. The communication unit 114 stores data received from the other ECU via the CAN2 in the shared memory 14.

Next, the functional structure of the cores 12, 13 will be described. Since the functional structure of the core 12 is the same as that of the core 13, only the functional structure of the core 12 will be described below.

The core 12 includes an arithmetic unit 121, an abnormality determination unit 122, and a control unit 123. The core 12 includes a storage unit (not shown) such as a ROM or a RAM, and functions as the arithmetic unit 121, the abnormality determination unit 122, and the control unit 123 by executing a program stored in the storage unit. The operation unit 121 and the control unit 123 are the same as the operation unit 111 and the control unit 113 of the core 11, and therefore, the description thereof is omitted.

The abnormality determination unit 122 determines whether or not an abnormality has occurred in another core. When the abnormality determination unit 112 of the core 11 receives the abnormality notification signal, the abnormality determination unit 122 determines that an abnormality has occurred in another core.

Next, the operation of each core of the ECU10A will be described. Fig. 3 is a diagram schematically showing an example of the operation of each core of the ECU10A of fig. 1B. For simplicity of explanation, the ECU10C is omitted in fig. 3.

In the example shown in fig. 3, the core 11 calculates a parameter pX ₁ necessary for controlling the transmission 4 from the parameter ps obtained based on the sensor output of the sensor group 20 and the parameter pY ₁ stored in the shared memory 14. The core 11 then controls the transmission 4 based on the calculated pX ₁. Ps and pY ₁ are parameters stored in the shared memory 14 by the core 12 as described later. The core 11 stores ps and pX ₁ in a CAN frame and outputs the result to CAN2. At that time, the core 11 saves ps and pX ₁ in the shared memory 14 in such a manner that each core can use ps and pX ₁.

The core 12 calculates pY ₁, which is a parameter necessary for controlling the transmission 4, from the parameters pt and pu obtained based on the sensor outputs of the sensor group 20. The core 12 then controls the transmission 4 based on the calculated pY ₁. The core 12 stores pt, pu, and pY ₁ in the shared memory 14 so that each core can use pt, pu, and pY ₁. The pt, pu, and pY ₁ stored in the shared memory 14 are stored in the CAN frame by the communication unit 114 of the core 11, and output to CAN2.

The core 13 calculates a parameter pZ ₁ necessary for control of the EPS device 5 from the parameter pv obtained based on the sensor output of the sensor group 20 and the pX ₁ stored in the shared memory 14. Then, the core 13 controls the EPS device 5 based on the calculated pZ ₁. Also, the core 13 saves pv and pZ ₁ in the shared memory 14 in such a manner that each core can use pv and pZ ₁. The pv and pZ ₁ stored in the shared memory 14 are stored in the CAN frame by the communication unit 114 of the core 11, and output to CAN2.

Ps, pt, pu, and pv are parameters calculated from sensor outputs of the sensor group 20, and are parameters converted into digital values so as to be stored in CAN frames for transmission and reception. As an example of such a parameter, there is a parameter that converts a temperature converted from an analog voltage output from a temperature sensor into a digital value so that the temperature CAN be transmitted and received in a CAN frame. As described above, in the present embodiment, each core stores not only the parameters for controlling each device, but also the values calculated from the sensor outputs of the sensor group 20 in the CAN frame, and converts the values into digital values that CAN be transmitted and received, and sequentially stores the digital values in the shared memory 14.

In CAN communication, CAN frames sent from a single ECU to the CAN are broadcast to all ECUs on the CAN. Therefore, each ECU on the CAN share data via CAN communication, and the ECUs 10A, 10B, 10C of the present embodiment also transmit data of wide use usable in other ECUs to the CAN for sharing with other ECUs. Thus, even when, for example, an abnormality occurs in the core 12 and the core 11 cannot acquire the pY ₁, the core 11 CAN continue the arithmetic processing by replacing the pY ₁ with the data stored in the CAN frame received from the other ECU.

As a more specific example, assume a case where the core 12 calculates the engine rotational speed Ne from the rotational speed Vc of the crankshaft, and the core 11 performs control of the transmission 4 using the engine rotational speed Ne calculated by the core 12. In this case, when an abnormality occurs in the core 12, the core 11 cannot obtain the latest value of the engine rotation speed Ne, and therefore there is a possibility that the control of the transmission 4 cannot be continued. However, the ECU10B calculates the engine rotation speed Ne ' from the motor rotation speed Vm, and if the engine rotation speed Ne ' is transmitted to the CAN2, the core 11 CAN acquire the engine rotation speed Ne '. The core 11 can continue the control of the transmission 4 using the engine rotational speed Ne'.

In the present embodiment, each core of the ECU10A, ECU 10B, ECU C does not share data (hereinafter referred to as intermediate data), various correction values, learning values, and the like during calculation, which are generated when various data is calculated in the calculation process, with other cores.

That is, the respective cores store the final data obtained by the arithmetic processing and the digital value which is obtained from the output of the sensor, i.e., which can be shared by the respective ECUs, in the shared memory 14. On the other hand, the cores are not configured to store data such as intermediate data, various correction values, and learning values (hereinafter, referred to as intermediate data or the like) in the shared memory 14. The intermediate data and the like are not shared between the ECUs via the CAN, and therefore, the substitute data cannot be acquired from the other ECU. Therefore, when intermediate data or the like is shared between cores, and intermediate data or the like of another core is used in the operation processing of each core, if any core is abnormal, the substitute data cannot be obtained and the operation processing cannot be continued.

Next, detailed operations of each core of the ECU10A will be described in detail. Fig. 4 is a flowchart showing the operation of each core. The process shown in fig. 4 is repeatedly executed at a predetermined cycle during the period in which the ECU10A is activated. Since the operations of the cores are the same, the detailed operation of the core 11 will be described here.

First, in step S101, the arithmetic unit 111 determines whether or not the data stored in the shared memory 14 is used for the arithmetic processing in step S108 described later. When step S101 is negative (S101: no), the process advances to step S108.

When step S101 is affirmative (yes in S101), in step S102, the abnormality determination unit 112 determines whether or not an abnormality has occurred in the core 11, which is the core itself. When step S102 is affirmative (S102: yes), the process advances to step S106. If step S102 is negative (no in S102), in step S103, the abnormality determination unit 112 determines whether or not an abnormality has occurred in the cores 12 and 13, which are other cores.

When step S103 is affirmative (S103: yes), the process proceeds to step S106. When step S103 is negative (S103: no), in step S104, the arithmetic unit 111 reads out the data (pY ₁ shown in fig. 3) used for the arithmetic processing in step S108 from the shared memory 14. Next, in step S105, the arithmetic unit 111 determines whether or not the data read out in step S104 has an abnormality. When step S105 is affirmative (S105: yes), the process advances to step S107. When step S105 is negative, the process advances to step S108.

In the present embodiment, the arithmetic unit 111 determines that the data read out in step S104 is abnormal when the data is not the latest value. For example, when the state in which the data read out in step S104 is identical to the previous value is repeated a predetermined number of times, the arithmetic unit 111 determines that the data is not the latest value.

In step S106, the arithmetic unit 111 notifies the cores 12 and 13 that the abnormality is detected in steps S102, S103, or S105. Next, in step S107, the arithmetic unit 111 acquires the substitute data (pY 2 shown in fig. 3) from the shared memory 14, and the process proceeds to step S108.

In step S108, the arithmetic unit 111 executes arithmetic processing. At this time, when the substitute data is acquired in step S106, the arithmetic unit 111 uses the substitute data for arithmetic processing. Next, in step S109, the arithmetic unit 111 stores the arithmetic result (pX 1 shown in fig. 3) obtained by the arithmetic processing in the shared memory 14. Finally, in step S110, the communication unit 114 reads out the CAN frame in which the calculation result stored in the shared memory 14 is stored, and transmits the CAN frame in which the calculation result is stored to the other ECU via the CAN 2.

Since the cores 12 and 13 detect the abnormality of their own cores by the abnormality detection function and output an abnormality occurrence signal to the core 11, the processing of steps S102 and S106 is not performed. In the cores 12 and 13, the processing of step S110 is not performed. As described above, the calculation results of the cores 12 and 13 stored in the shared memory 14 by the cores 12 and 13 are stored in the CAN frame by the communication unit 114 of the core 11, and are output to the CAN 2.

The following effects can be achieved by the embodiments of the present invention.

(1) The ECU10A mounted on the vehicle 1 includes a plurality of cores 11 to 13 each performing an operation process, a shared memory 14 accessible to the plurality of cores 11 to 13, and a communication unit 114 (fig. 2) that communicates with the ECU10B, ECU C as an external device via the in-vehicle communication network 2. The communication unit 114 transmits and receives data of a plurality of types to and from the ECU10B, ECU C, and the shared memory 14 stores data corresponding to any of the plurality of types among the data obtained by the arithmetic processing of the plurality of cores 11 to 13.

Thus, the data stored in the shared memory 14 is limited to data transmitted and received between the ECUs. Therefore, data that is not shared between the ECUs, such as intermediate data, is not stored in the shared memory 14. Thereby enabling improved independence of the cores.

The independence of the cores is described herein. Conventionally, there has been proposed a method of sharing intermediate data among cores and the like, and using intermediate data of other cores in the arithmetic processing of each core, thereby accelerating the arithmetic processing of each core. However, in such a configuration, the dependency between cores increases, and the independence of the cores cannot be maintained. That is, when any core is abnormal, the actions of the other cores are easily affected. On the other hand, as in the present embodiment, by not storing intermediate data or the like in the shared memory 14, the independence of the cores can be improved, and even when any one of the cores is abnormal, the influence on the operation of the other cores can be reduced.

(2) The in-vehicle communication network 2 is a CAN, and the plurality of types of data are data stored in CAN frames transmitted and received between the ECU10A and the ECUs 10B and 10C.

Thus, the data stored in the CAN frame is stored in the shared memory 14, among the data obtained by the arithmetic processing of each core. Therefore, the data obtained by the arithmetic processing is transferred between each core and the other cores just like CAN communication. That is, each core can perform transfer of data obtained by arithmetic processing while maintaining independence without requiring special exclusive control. Further, since CAN2 normally receives and transmits data of the same type as Ne and Ne', even when the data stored in the shared memory 14 cannot be used for some reason, the data received from the other ECU CAN be used instead.

(3) The plurality of cores 11 to 13 include a1 st core (core 12 of fig. 3) and a2 nd core (core 11 of fig. 3) that performs arithmetic processing using 1 st data (pY ₁ of fig. 3) stored in the shared memory 14 by the 1 st core, and when it is determined that an abnormality occurs in the 1 st core (S103), the 2 nd core continues the arithmetic processing using 2 nd data (pY 2 of fig. 3) stored in the CAN frame, which is received from the external device (ECU 10B of fig. 3) by the communication unit 114, using the substitute data of the 1 st data (S103).

Thus, even when any core is abnormal and the other cores cannot acquire the data calculated by the core from the shared memory 14, the influence on the other cores can be minimized.

(4) When the 1 st core determines that the 1 st data stored in the shared memory 14 is abnormal (S105), the 2 nd core continues the arithmetic processing using the 2 nd data which is the substitute data for the 1 st data (S107, S108).

Thus, even when an abnormality occurs in the data stored in the shared memory 14, each core can use the data for the arithmetic processing and the influence on other cores can be minimized.

The above-described embodiments can be modified into various modes. The following describes modifications. In the above embodiment, an example in which the vehicle control apparatus 100 has three electronic control apparatuses is shown, but the vehicle control apparatus 100 may have a plurality of electronic control apparatuses.

In the above embodiment, the ECU10A, ECU10B, ECU C has been shown as an example in which a multi-core processor having three cores is mounted, but the multi-core processor mounted in the electronic control device may have several cores. The CAN is described as an example of the communication network, but the communication network is not limited to CAN, and may be FlexRay or CAN FD.

One or more of the above embodiments and modifications may be arbitrarily combined, or the modifications may be combined with each other.

By adopting the invention, the independence of cores in the electronic control device with the multi-core processor can be improved.

While the invention has been described in connection with preferred embodiments, it will be understood by those skilled in the art that various modifications and changes can be made without departing from the scope of the disclosure of the following claims.

Claims

1. An electronic control device (10A) mounted on a vehicle (1), comprising:

a plurality of cores (11, 12, 13) each performing an arithmetic process;

-a shared memory (14) accessible to said plurality of cores (11, 12, 13); and

A communication unit (114) that communicates with external devices (10B, 10C) via a communication network (2),

Between the communication unit (114) and the external devices (10B, 10C), a plurality of types of data are transmitted and received,

The shared memory (14) stores data corresponding to any of the plurality of types among data obtained by the arithmetic processing of the plurality of cores (11, 12, 13),

The communication network (2) is a CAN,

The plurality of types of data are data stored in a CAN frame, which are transmitted and received between the communication unit (114) and the external devices (10B, 10C),

The plurality of cores (11, 12, 13) includes a1 st core (12) and a2 nd core (11) performing arithmetic processing using 1 st data stored in the shared memory (14) by the 1 st core,

When it is determined that the 1 st core (12) is abnormal, the 2 nd core (11) continues the arithmetic processing using the 2 nd data stored in the CAN frame, which is received from the external devices (10B, 10C) by the communication unit (114) and is the substitute data for the 1 st data.

2. The electronic control device according to claim 1, wherein,

When the 1 st core (12) determines that the 1 st data stored in the shared memory (14) is abnormal, the 2 nd core (11) continues the arithmetic processing using the 2 nd data stored in the CAN frame, which is received from the external devices (10B, 10C) by the communication unit (114) and is the substitute data for the 1 st data.

3. The electronic control device according to claim 1 or 2, wherein,

The cores (11, 12, 13) store data representing the operation result obtained by the operation processing in the shared memory (14).

4. The electronic control device according to claim 1 or 2, wherein,

The cores (11, 12, 13) perform an operation of converting an output of a sensor (20) mounted on the vehicle (1) into a digital value, and store parameters obtained by the operation in the shared memory (14).

5. The electronic control device according to claim 1 or 2, wherein,

The cores (11, 12, 13) do not store data during computation generated during the computation process in the shared memory (14).