CN113363163B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN113363163B CN113363163B CN202110592315.XA CN202110592315A CN113363163B CN 113363163 B CN113363163 B CN 113363163B CN 202110592315 A CN202110592315 A CN 202110592315A CN 113363163 B CN113363163 B CN 113363163B
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof, wherein the manufacturing method of the semiconductor device comprises the following steps: providing a top wafer and a bottom wafer, wherein a metal interconnection structure is formed in the bottom wafer; forming a pad structure on the bottom wafer, wherein the pad structure is electrically connected with the metal interconnection structure; forming a sacrificial layer on the top wafer and/or the bottom wafer, bonding the top wafer and the bottom wafer, wherein the sacrificial layer is located between the pad structure and the surface of the top wafer far away from the bottom wafer, and the projection of the sacrificial layer and the pad structure in the direction perpendicular to the bonding surface at least partially coincides; and forming a first opening on the surface of the top wafer, which is far away from the bottom wafer, wherein the sacrificial layer is exposed out of the first opening. The technical scheme of the invention can reduce the parasitic capacitance and simplify the manufacturing process of the bonding pad structure.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a semiconductor device and a method for fabricating the same.
Background
For semiconductor technology, parasitic capacitance has been one of the limiting factors for some device performance enhancements. Particularly, for a semiconductor device which needs to operate at a high frequency, parasitic Capacitance (Pad CIO) of a metal plate structure of an Input/Output (I/O) terminal thereof may seriously affect an I/O transfer rate.
Taking an optical device developed by using a 3D IC (three-dimensional integrated circuit package) technology as an example, the 3D IC technology is a technology platform and architecture with great development potential and rich expansibility. For example, the 3D IC CIS (CMOS Image Sensor) technology and product, and the 3D IC NAND Flash technology and product, which are already mature at present, bond the pixel wafer and the logic wafer by using the 3D IC technology, so that both the performance and the area utilization rate of the chip are greatly improved.
At present, after the pixel wafer and the logic wafer are bonded, the back surface of the pixel wafer on the top layer is thinned, and then the bonding pad is manufactured. Referring to fig. 1, the pixel wafer includes a first substrate 11 and a first device layer 111 formed on the first substrate 11, the logic wafer includes a second substrate 12 and a second device layer 121 formed on the second substrate 12, the first device layer 111 and the second device layer 121 are bonded through a bonding layer (not shown), a first metal interconnection structure 112 is formed in the first device layer 111, a second metal interconnection structure 122 is formed in the second device layer 121, and the first metal interconnection structure 112 is electrically connected to the second metal interconnection structure 122. The pad structure comprises three schemes:
the first scheme is as follows: in the a1 region, a trench (not shown) penetrating through the first substrate 11 is formed in the first substrate 11, a first insulating medium layer 13 is formed on the inner surface of the trench and the back surface of the first substrate 11 at the periphery of the trench, a through hole (not shown) penetrating through the first insulating medium layer 13 and the first device layer 111 with a partial depth is formed at the bottom of the trench, a part of the first metal interconnection structure 112 is exposed by the through hole, a metal material is filled in the through hole and the bottom of the trench to form a first pad 15 at the bottom of the trench, and the second metal interconnection structure 122 is led out through the first pad 15;
scheme two is as follows: in the a2 region, a trench (not shown) penetrating through the first substrate 11 is formed in the first substrate 11, a first insulating dielectric layer 13 is formed on the inner surface of the trench and the back surface of the first substrate 11 at the periphery of the trench, a through hole (not shown) penetrating through the first insulating dielectric layer 13 and a part of the depth of the first device layer 111 is formed at the bottom of the trench, the through hole exposes a part of the first metal interconnection structure 112, the inner surfaces of the through hole and the trench and the first insulating dielectric layer 13 at the periphery of the trench are sequentially covered with a metal material and a second insulating dielectric layer 14, the metal material on the back surface of the first substrate 11 can be formed into a complex metal wire, an opening in the second insulating dielectric layer 14 exposes a part of the surface of the metal wire to serve as a second pad 16, and the second metal interconnection structure 122 is led out through the second pad 16;
the third scheme is as follows: in the region a3, the back surface of the first substrate 11 is covered with a first insulating dielectric layer 13, a complex metal connecting line is formed on the first insulating dielectric layer 13, a second insulating dielectric layer 14 covering the metal connecting line is formed on the first insulating dielectric layer 13, and an opening in the second insulating dielectric layer 14 exposes a part of the surface of the metal connecting line to serve as a third pad 18; the metal wiring is electrically connected to the first metal interconnection structure 112 through the via plug structure 17 penetrating through the first insulating dielectric layer 13 and the first substrate 11 and the conductive plug 113 in the first device layer 111, so that the third pad 18 leads out the second metal interconnection structure 122.
In the above three pad structure solutions, the corresponding advantages and disadvantages are as follows:
the first scheme is as follows: the parasitic capacitance is small; however, the pad (i.e., the first pad 15) can be formed only in the trench, and the metal wiring cannot be formed on the back surface of the first substrate 11;
scheme II: both metal wiring and pads (i.e., second pads 16) can be formed on the back side of the first substrate 11; however, parasitic capacitance is formed among the metal wiring, the first insulating medium layer 13 and the first substrate 11, resulting in large parasitic capacitance;
the third scheme is as follows: both the metal wiring and the bonding pad (i.e., the third bonding pad 18) can be formed on the back surface of the first substrate 11; however, a parasitic capacitance is formed between the metal line, the first insulating dielectric layer 13 and the first substrate 11, and a parasitic capacitance is also formed between the via plug structure 17 and the first substrate 11, resulting in a large parasitic capacitance.
In addition, in the above-mentioned solution of the pad structure, after the pixel wafer and the logic wafer are bonded, the pad structure needs to be additionally fabricated on the pixel wafer located at the top layer, and a complex first metal interconnection structure needs to be fabricated in the pixel wafer, and a second metal interconnection structure in the logic wafer can be led out only by electrically connecting the pad structure and the first metal interconnection structure, so that the process for fabricating the pad structure is complex.
Therefore, there is a need for an improved pad structure and fabrication process to solve the above problems.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, which can reduce parasitic capacitance and simplify the manufacturing process of a bonding pad structure.
To achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising:
providing a top wafer and a bottom wafer, wherein a metal interconnection structure is formed in the bottom wafer;
forming a pad structure on the bottom wafer, wherein the pad structure is electrically connected with the metal interconnection structure;
forming a sacrificial layer on the top wafer and/or the bottom wafer, bonding the top wafer and the bottom wafer, wherein the sacrificial layer is located between the pad structure and the surface of the top wafer far away from the bottom wafer, and the projection of the sacrificial layer and the pad structure in the direction perpendicular to the bonding surface at least partially coincides; and the number of the first and second groups,
and forming a first opening on the surface of the top wafer, which is far away from the bottom wafer, wherein the sacrificial layer is exposed from the first opening.
Optionally, the method for manufacturing a semiconductor device further includes: and removing the sacrificial layer by adopting an ashing process to form a second opening, wherein the second opening exposes the pad structure.
Optionally, the method for manufacturing a semiconductor device further includes:
forming an insulating medium layer to cover the inner surface of the second opening;
and forming a third opening in the insulating medium layer on the bottom surface of the second opening, wherein the third opening exposes part of the surface of the bonding pad structure.
Optionally, the step of forming the pad structure on the bottom wafer includes:
forming a through hole in the bottom layer wafer, wherein the through hole exposes the metal interconnection structure;
forming a metal layer to cover the bottom wafer, wherein the metal layer fills the through hole; and the number of the first and second groups,
and etching and removing part of the metal layer on the bottom layer wafer to form a pad structure electrically connected with the metal interconnection structure.
Optionally, the method for forming the sacrificial layer on the bottom wafer includes:
forming a bonding layer on the bottom wafer, wherein the bonding layer buries the pad structure inside;
forming a first sacrificial layer in the bonding layer, the first sacrificial layer being connected with the pad structure.
Optionally, the step of bonding the top wafer and the bottom wafer comprises:
forming a second sacrificial layer in the top wafer;
and bonding the top wafer and the bottom wafer, wherein the first sacrificial layer is connected with the second sacrificial layer in an aligned mode.
Optionally, the material of the sacrificial layer includes a carbon-containing material.
The present invention also provides a semiconductor device comprising:
a bottom wafer having a metal interconnect structure;
a pad structure formed on the underlying wafer, the pad structure being electrically connected to the metal interconnect structure;
a top wafer bonded to the bottom wafer;
the sacrificial layer is formed on the top wafer and/or the bottom wafer, the sacrificial layer is located between the pad structure and the surface of the top wafer, which is far away from the bottom wafer, and the projection of the sacrificial layer and the pad structure in the direction perpendicular to the bonding surface is at least partially overlapped; and the number of the first and second groups,
the first opening is formed in the surface, far away from the bottom wafer, of the top wafer, and the sacrificial layer is exposed out of the first opening.
Optionally, a through hole exposing the metal interconnection structure is formed in the bottom wafer, and the pad structure fills the through hole and covers a part of the top surface of the bottom wafer.
Optionally, the semiconductor device further comprises:
a bonding layer located between the bottom wafer and the top wafer; and a first sacrificial layer formed in the bonding layer is used as the sacrificial layer formed on the bottom wafer, the first sacrificial layer is connected with the pad structure, and the bonding layer and the first sacrificial layer jointly bury the pad structure.
Optionally, a second sacrificial layer formed in the top wafer is used as the sacrificial layer formed on the top wafer, and the first sacrificial layer is connected to the second sacrificial layer in an aligned manner.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. according to the manufacturing method of the semiconductor device, before the top wafer is bonded on the bottom wafer, the pad structure is formed on the bottom wafer, after the top wafer is bonded on the bottom wafer, all layers of structures on the pad structure are etched, the pad structure is opened, the metal interconnection structure in the bottom wafer can be led out through the pad structure, and therefore the manufacturing process of the pad structure can be simplified while parasitic capacitance is reduced; and a sacrificial layer is formed on the top wafer and/or the bottom wafer, and the projection of the sacrificial layer and the pad structure in the direction perpendicular to the bonding surface at least partially coincide, so that the process difficulty of opening the pad structure is reduced.
2. In the semiconductor device, in the structure formed by bonding the top wafer and the bottom wafer, the pad structure is formed on the bottom wafer, so that the metal interconnection structure in the bottom wafer can be led out through the pad structure after the pad structure is opened, thereby reducing the parasitic capacitance and simplifying the manufacturing process of the pad structure; and because the sacrificial layer is formed on the top wafer and/or the bottom wafer, and the projection of the sacrificial layer and the pad structure in the direction vertical to the bonding surface is at least partially overlapped, the process difficulty of opening the pad structure is reduced.
Drawings
FIG. 1 is a cross-sectional view of a prior art bond pad structure;
fig. 2 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 3a to 3m are device diagrams in the method of manufacturing the semiconductor device shown in fig. 2.
Wherein the reference numerals of figures 1 to 3m are as follows:
11-a first substrate; 111-a first device layer; 112-a first metal interconnect structure; 113-a conductive plug; 12-a second substrate; 121-a second device layer; 122-a second metal interconnect structure; 13-a first insulating dielectric layer; 14-a second insulating dielectric layer; 15-a first pad; 16-a second pad; 17-a via plug structure; 18-a third pad; 20-a bottom wafer; 21-a first substrate; 22-a first device layer; 221-metal interconnect structures; 222-a via hole; 223-a metal layer; 23-a pad structure; 24-a first bonding layer; 25-a first sacrificial layer; 30-a top wafer; 31-a second substrate; 311-a first opening; 32-a second device layer; 33-a second bonding layer; 34-a second sacrificial layer; 35-a second opening; 36-insulating dielectric layer; 37-third opening.
Detailed Description
To make the objects, advantages and features of the present invention more apparent, the semiconductor device and the method for manufacturing the same proposed by the present invention are described in further detail below. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. As used herein, "and/or" means either or both.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, and referring to fig. 2, fig. 2 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, where the method for manufacturing a semiconductor device includes:
step S1, providing a top wafer and a bottom wafer, wherein a metal interconnection structure is formed in the bottom wafer;
step S2, forming a pad structure on the bottom wafer, wherein the pad structure is electrically connected with the metal interconnection structure;
step S3, forming a sacrificial layer on the top wafer and/or the bottom wafer, and bonding the top wafer and the bottom wafer, where the sacrificial layer is located between the pad structure and a surface of the top wafer far from the bottom wafer, and a projection of the sacrificial layer and the pad structure in a direction perpendicular to a bonding surface at least partially coincides;
step S4, forming a first opening on the surface of the top wafer away from the bottom wafer, where the sacrificial layer is exposed by the first opening.
The method for manufacturing the semiconductor device according to the present embodiment is described in more detail with reference to fig. 3a to 3m, which are schematic cross-sectional views of the semiconductor device in fig. 3a to 3 m.
According to step S1, referring to fig. 3a and 3h, a bottom wafer 20 and a top wafer 30 are provided, wherein the bottom wafer 20 has a metal interconnection structure 221 formed therein.
As shown in fig. 3a, the bottom wafer 20 includes a substrate and a device layer formed on the substrate (for distinguishing from the substrate and the device layer in the top wafer 30, the substrate and the device layer in the bottom wafer 20 are defined as a first substrate 21 and a first device layer 22, respectively, and the substrate and the device layer in the top wafer 30 are defined as a second substrate 31 and a second device layer 32, respectively), and the metal interconnection structure 221 is formed in the first device layer 22.
The bottom wafer 20 may be a logic wafer, and a CMOS circuit is formed inside the logic wafer; the first device layer 22 may also include MOS transistors, resistors, capacitors, and the like. The bottom wafer 20 may be a single-layer wafer structure or a multi-layer wafer bonded structure, as shown in fig. 3a, the bottom wafer 20 is a single-layer wafer structure. The structure of the bottom wafer 20 depends on the function of the device to be ultimately fabricated.
As shown in fig. 3h, the top wafer 30 includes a second substrate 31 and a second device layer 32 formed on the second substrate 31. The second device layer 32 may include functional structures, such as pixel arrays, transistors, or MEMS microstructures (e.g., diaphragms, electrodes, etc.).
The top wafer 30 may be a device wafer, such as a pixel wafer containing an array of pixels of an image sensor, the type of the top wafer 30 depending on the function of the device to be ultimately fabricated. The top wafer 30 may be a single-layer wafer structure or a multi-layer wafer bonded structure, as shown in fig. 3h, in the embodiment, the top wafer 30 is a single-layer wafer structure.
According to step S2, referring to fig. 3b to fig. 3d, a pad structure 23 is formed on the bottom wafer 20, and the pad structure 23 is electrically connected to the metal interconnection structure 221.
The step of forming the pad structure 23 on the bottom wafer 20 includes: first, as shown in fig. 3b, etching the first device layer 22 to form a via 222 in the first device layer 22, wherein the via 222 exposes a portion of the top surface of the metal interconnection structure 221; then, as shown in fig. 3c, a metal layer 223 is formed to cover the first device layer 22, and the metal layer 223 fills up the through hole 222; next, as shown in fig. 3d, etching and removing a portion of the metal layer 223 on the first device layer 22 to form a pad structure 23 electrically connected to the metal interconnection structure 221, where the pad structure 23 includes a portion located in the via 222 and a portion located on a top surface of the first device layer 22 (i.e., a surface of the first device layer 22 away from the first substrate 21).
In addition, in the above step, the first substrate 21 and the first device layer 22 with a partial depth may also be etched to form the through hole 222, and the through hole 222 penetrates through the first substrate 21 and the first device layer 22 with a partial depth, so that the pad structure 23 includes a portion located in the through hole 222 and a portion located on the bottom surface of the first substrate 21 (i.e., the surface of the first substrate 21 away from the first device layer 22).
The material of the metal layer 223 may include at least one of metal materials such as tungsten, aluminum, copper, silver, and gold.
According to step S3, a sacrificial layer is formed on the top wafer 30 and/or the bottom wafer 20, and the top wafer 30 is bonded to the bottom wafer 20, the sacrificial layer is located between the pad structure 23 and a surface of the top wafer 30 away from the bottom wafer 20, and a projection of the sacrificial layer and the pad structure 23 in a direction perpendicular to a bonding surface at least partially coincide.
The method of forming the sacrificial layer on the bottom wafer 20 includes: firstly, forming a bonding layer (for distinguishing from the bonding layer on the top wafer 30, the bonding layer on the bottom wafer 20 is defined as a first bonding layer 24, and the bonding layer on the top wafer 30 is defined as a second bonding layer) on the bottom wafer 20, wherein the pad structure 23 is buried in the first bonding layer 24; then, a first sacrificial layer 25 is formed in the first bonding layer 24, and the first sacrificial layer 25 is connected to the pad structure 23.
If the pad structure 23 includes a portion located in the through hole 222 and a portion located on the top surface of the first device layer 22, referring to fig. 3e, the first bonding layer 24 covers the first device layer 22, and the pad structure 23 is buried in the first bonding layer 24; referring to fig. 3f, the top surface of the first bonding layer 24 is planarized by a chemical mechanical polishing process, so that the top surface of the first device layer 22 is bonded to the top wafer 30 through the first bonding layer 24.
Or, if the pad structure 23 includes a portion located in the through hole 222 and a portion located on the bottom surface of the first substrate 21, the first bonding layer 24 covers a surface of the first substrate 21 away from the first device layer 22, and then a surface of the first substrate 21 away from the first device layer 22 is bonded to the top wafer 30 through the first bonding layer 24.
In addition, the step of forming the sacrificial layer on the top wafer 30 and bonding the top wafer 30 and the bottom wafer 20 comprises: first, forming a second bonding layer 33 on the top wafer 30; then, forming a second sacrificial layer 34 in the top wafer 30, wherein the second sacrificial layer 34 penetrates through the second bonding layer 33; then, the top wafer 30 and the bottom wafer 20 are bonded by the first bonding layer 24 and the second bonding layer 33, and the first sacrificial layer 25 and the second sacrificial layer 34 are connected in alignment.
As shown in fig. 3h, the second bonding layer 33 may be covered on a surface of the second device layer 32 away from the second substrate 31, and then a subsequent surface of the second device layer 32 away from the second substrate 31 is bonded to the bottom wafer 20 through the second bonding layer 33; alternatively, the second bonding layer 33 may be overlaid on the side of the second substrate 31 away from the second device layer 32, and then the side of the second substrate 31 away from the second device layer 32 is bonded to the bottom wafer 20.
The following description will proceed by taking an example in which the surface of the first device layer 22 away from the first substrate 21 and the surface of the second device layer 32 away from the second substrate 31 are bonded through the first bonding layer 24 and the second bonding layer 33 (i.e., the front surface of the top wafer 30 is bonded to the front surface of the bottom wafer 20).
If the sacrificial layer is formed only on the bottom wafer 20, after the first bonding layer 24 is formed on the bottom wafer 20 and before the top wafer 30 is bonded on the bottom wafer 20, as shown in fig. 3g, a first opening (not shown) is formed on the surface of the first bonding layer 24, the pad structure 23 is exposed by the first opening, the first sacrificial layer 25 is filled in the first opening, a planarization process may be used to make the surface of the first sacrificial layer 25 and the surface of the first bonding layer 24 on a same plane, and the bottom surface of the first sacrificial layer 25 contacts the top surface of the pad structure 23, so that the projection of the first sacrificial layer 25 and the pad structure 23 in a direction perpendicular to the bonding plane at least partially coincide. The formation of the first sacrificial layer 25 in the first bonding layer 24 is not limited to the above method, and may be performed according to actual needs.
Alternatively, if the sacrificial layer is formed only on the top wafer 30, before the top wafer 30 is bonded to the bottom wafer 20, as shown in fig. 3h, a second opening (not shown) is formed on the surface of the second bonding layer 33, the second opening at least penetrates through the second bonding layer 33, the second opening is filled with the second sacrificial layer 34, and a planarization process may be used to make the surface of the second sacrificial layer 34 and the surface of the second bonding layer 33 on the same plane. It should be noted that the formation of the second sacrificial layer 34 in at least the second bonding layer 33 is not limited to the above method, and may be performed according to actual needs. And after the top wafer 30 is bonded to the bottom wafer 20, the position of the second sacrificial layer 34 is aligned with the position of the pad structure 23, that is, the projection of the second sacrificial layer 34 and the pad structure 23 in the direction perpendicular to the bonding surface at least partially coincide. The second sacrificial layer 34 in the top wafer 30 may include penetrating only the second bonding layer 33, or penetrating both the second bonding layer 33 and the second device layer 32 (as shown in fig. 3 h), or may penetrate the second bonding layer 33, the second device layer 32, and a part of the depth of the second substrate 31, etc.
Alternatively, if the sacrificial layers are formed on the bottom wafer 20 and the top wafer 30, the first sacrificial layer 25 and the second sacrificial layer 34 may be formed by the method of the embodiment shown in fig. 3g and fig. 3h, and as shown in fig. 3i, after the top wafer 30 is bonded on the bottom wafer 20, the projections of the first sacrificial layer 25 and the second sacrificial layer 34 and the pad structure 23 in the direction perpendicular to the bonding surface at least partially coincide, and the first sacrificial layer 25 is connected to the second sacrificial layer 34, preferably, the positions of the first sacrificial layer 25 and the second sacrificial layer 34 are aligned.
The material of the first sacrificial layer 25 and the second sacrificial layer 34 includes a carbon-containing material, such as a carbon-containing anti-reflective material, a carbon-containing photoresist, a carbon-containing organic polymer, and the like.
After the front surface of the top wafer 30 is bonded to the front surface of the bottom wafer 20, the second substrate 31 on the back surface of the top wafer 30 may be thinned.
In step S4, a first opening 311 is opened on the surface of the top wafer 30 away from the bottom wafer 20, and the sacrificial layer is exposed through the first opening 311.
In addition, the method of manufacturing a semiconductor device further includes: and removing the sacrificial layer by adopting an ashing process to form a second opening 35, wherein the second opening 35 exposes the pad structure 23.
Wherein, if only the first sacrificial layer 25 is formed in the first bonding layer 24, the step of forming the first opening 311 and the second opening 35 includes: firstly, etching the top wafer 30 and the second bonding layer 33 to form a first opening 311, wherein the first opening 311 penetrates through the top wafer 30 and the second bonding layer 33 to expose the top surface of the first sacrificial layer 25; then, the first sacrificial layer 25 is removed by an ashing process to form a second opening 35 exposing the pad structure 23.
If the second sacrificial layer 34 is formed in the top wafer 30 and the second bonding layer 33 only partially deeply, the step of forming the first opening 311 and the second opening 35 includes: firstly, etching the top wafer 30 to form a first opening 311 in the top wafer 30, wherein the second sacrificial layer 34 is exposed from the first opening 311; then, removing the second sacrificial layer 34 by using an ashing process to expose the first bonding layer 24; next, the first bonding layer 24 is etched to form a second opening 35 exposing the pad structure 23.
If the first sacrificial layer 25 is formed in the first bonding layer 24 and the second sacrificial layer 34 is formed in the top wafer 30 and the second bonding layer 33 in partial depth, the steps of forming the first opening 311 and the second opening 35 include: first, as shown in fig. 3j, etching the top wafer 30 to form a first opening 311 in the top wafer 30, wherein the first opening 311 exposes the second sacrificial layer 34; then, as shown in fig. 3k, the second sacrificial layer 34 and the first sacrificial layer 25 are removed by an ashing process to form a second opening 35 exposing the pad structure 23.
In addition, it should be noted that, because the second sacrificial layer 34 is located at different depths in the top wafer 30, and may be located in a side of the top wafer 30 where the second device layer 32 is located or in a side of the top wafer 30 where the second substrate 31 is located, the step of forming the second opening 35 is not limited to the above three types, and the sequence of etching and ashing processes may be adaptively adjusted to form the second opening 35 according to different situations where the second sacrificial layer 34 is located in the top wafer 30.
And, since the entire thickness of the first bonding layer 24 on the region of the pad structure 23 exposed by the second opening 35 is replaced by the first sacrificial layer 25 or a partial thickness of the top wafer 30 is replaced by the second sacrificial layer 34 when the second opening 35 is formed, or the entire thickness of the first bonding layer 24 is replaced by the first sacrificial layer 25 and a part of the thickness of the top wafer 30 is replaced by the second sacrificial layer 34, so that etching of the entire thickness of the first bonding layer 24 and the top wafer 30 on the region of the pad structure 23 exposed by the second opening 35 after bonding can be avoided, but instead combines etching a portion of the thickness (to form a low aspect ratio channel) with an ashing process to obtain the second opening 35 with a high aspect ratio, reducing process difficulties.
In addition, the method of manufacturing a semiconductor device further includes:
as shown in fig. 3l, an insulating dielectric layer 36 is formed to cover the inner surface of the second opening 35 and cover the top wafer 30 at the periphery of the second opening 35;
as shown in fig. 3m, a third opening 37 is formed in the insulating dielectric layer 36 on the bottom surface of the second opening 35, and the third opening 37 exposes a portion of the surface of the pad structure 23, so that the pad structure 23 can extract the metal interconnection structure 221, that is, extract a signal in the bottom wafer 20.
In addition, the steps in the method for manufacturing a semiconductor device are not limited to the above formation order, and the order of the steps can be adaptively adjusted.
As can be known from the manufacturing method of the semiconductor device, before the top wafer is bonded to the bottom wafer, a pad structure is firstly fabricated on the bottom wafer, and after the top wafer is bonded to the bottom wafer, each layer of structure on the pad structure is etched to form a second opening which opens the pad structure, that is, the metal interconnection structure in the bottom wafer can be led out through the pad structure, that is, a signal in the bottom wafer is led out. Compared with the traditional method that after the top wafer is bonded on the bottom wafer, the pad structure is manufactured on the top wafer (such as the three schemes in fig. 1), the method of the invention leads out the metal interconnection structure in the bottom wafer directly through the pad structure on the bottom wafer, does not need to additionally manufacture the pad structure on the top wafer through complicated process steps after bonding, and there is no need to make a complicated metal interconnection structure electrically connected with the pad structure in the top wafer to lead out the metal interconnection structure in the bottom wafer, therefore, the manufacturing process of the pad structure is simplified, the length of the metal interconnection structure in the top wafer is shortened, and meanwhile, the parasitic capacitance corresponding to the pad structure is also reduced (i.e., the parasitic capacitance formed between the metal connecting line, the first insulating medium layer 13 and the first substrate 11 in the second and third schemes in fig. 1 is not generated).
An embodiment of the invention provides a semiconductor device, which comprises a bottom wafer, a bonding pad structure, a top wafer, a sacrificial layer and a first opening, wherein a metal interconnection structure is formed in the bottom wafer; the pad structure is formed on the bottom wafer and is electrically connected with the metal interconnection structure; the top wafer is bonded to the bottom wafer; the sacrificial layer is formed on the top wafer and/or the bottom wafer, the sacrificial layer is located between the pad structure and the surface of the top wafer far away from the bottom wafer, and the projection of the sacrificial layer and the pad structure in the direction perpendicular to the bonding surface is at least partially overlapped; the first opening is formed in the surface, away from the bottom wafer, of the top wafer, and the sacrificial layer is exposed out of the first opening.
The semiconductor device provided in this embodiment will be described in detail with reference to fig. 3 j.
A metal interconnect structure 221 is formed in the bottom wafer 20.
The bottom wafer 20 includes a substrate and a device layer formed on the substrate (to distinguish from the substrate and the device layer in the top wafer, the substrate and the device layer in the bottom wafer 20 are defined as a first substrate 21 and a first device layer 22, respectively, and the substrate and the device layer in the top wafer are defined as a second substrate and a second device layer, respectively), and the metal interconnection structure 221 is formed in the first device layer 22.
The bottom wafer 20 may be a logic wafer, and a CMOS circuit is formed inside the logic wafer; the first device layer 22 may also include MOS transistors, resistors, capacitors, and the like. The bottom wafer 20 may be a single-layer wafer structure or a multi-layer wafer bonded structure, as shown in fig. 3j, the bottom wafer 20 is a single-layer wafer structure. The structure of the bottom wafer 20 depends on the function of the device to be ultimately fabricated.
The pad structure 23 is formed on the bottom wafer 20, and the pad structure 23 is electrically connected to the metal interconnection structure 221.
A via (not shown) exposing the metal interconnection structure 221 is formed in the first device layer 22, the pad structure 23 fills the via and covers a portion of the top surface of the first device layer 22, and the pad structure 23 includes a portion located in the via and a portion located on a side of the first device layer 22 away from the first substrate 21.
Alternatively, the first substrate 21 and the first device layer 22 with a partial depth are formed with the through hole, and the pad structure 23 includes a portion located in the through hole and a portion located on a side of the first substrate 21 away from the first device layer 22.
The material of the pad structure 23 may include at least one of metal materials such as tungsten, aluminum, copper, silver, and gold.
The top wafer 30 is bonded to the bottom wafer 20.
The top wafer 30 includes a second substrate 31 and a second device layer 32 formed on the second substrate 31. The second device layer 32 may include functional structures, such as pixel arrays, transistors, or MEMS microstructures (e.g., diaphragms, electrodes, etc.).
The top wafer 30 may be a device wafer, such as a pixel wafer containing an array of pixels of an image sensor, the type of the top wafer 30 depending on the function of the device to be ultimately fabricated. The top wafer 30 may be a single-layer wafer structure or a multi-layer wafer bonded structure, as shown in fig. 3j, the top wafer 30 is a single-layer wafer structure.
The semiconductor device further comprises a first bonding layer 24 and a second bonding layer 33, which are located between the bottom wafer 20 and the top wafer 30, and the first bonding layer 24 is closer to the bottom wafer 20 than the second bonding layer 33.
If the pad structure 23 includes a portion located in the through hole 222 and a portion located on a side of the first device layer 22 away from the first substrate 21, the first device layer 22 is closer to the top wafer 30 than the first substrate 21, and the first bonding layer 24 covers the portion of the pad structure 23 located on the side of the first device layer 22 away from the first substrate 21.
If the pad structure 23 includes a portion located in the through hole 222 and a portion located on a side of the first substrate 21 away from the first device layer 22, the first substrate 21 is closer to the top wafer 30 than the first device layer 22, and the first bonding layer 24 covers the portion of the pad structure 23 located on the side of the first substrate 21 away from the first device layer 22.
The second device layer 32 is closer to the bottom wafer 20 than the second substrate 31, or the second substrate 31 is closer to the bottom wafer 20 than the second device layer 32.
The sacrificial layer is formed on the top wafer 30 and/or the bottom wafer 20, the sacrificial layer is located between the pad structure 23 and the surface of the top wafer 30 away from the bottom wafer 20, and a projection of the sacrificial layer and the pad structure 23 in a direction perpendicular to a bonding surface at least partially coincides.
A first sacrificial layer 25 formed in the first bonding layer 24 as the sacrificial layer formed on the underlying wafer 20; the first sacrificial layer 25 is connected to the pad structure 23, and the first bonding layer 24 and the first sacrificial layer 25 together bury the pad structure 23.
The second sacrificial layer 34 formed in the top wafer 30 is used as the sacrificial layer formed on the top wafer 30, and the second sacrificial layer 34 penetrates through the second bonding layer 33, and the first sacrificial layer 25 and the second sacrificial layer 34 are connected in alignment. The second sacrificial layer 34 in the top wafer 30 may include penetrating through both the second bonding layer 33 and the second device layer 32 (as shown in fig. 3 h), or may penetrate through the second bonding layer 33, the second device layer 32 and a portion of the depth of the second substrate 31, etc.
The material of the first sacrificial layer 25 and the second sacrificial layer 34 includes a carbon-containing material, such as a carbon-containing anti-reflective material, a carbon-containing photoresist, a carbon-containing organic polymer, and the like.
The first opening 311 is opened on the surface of the top wafer 30 away from the bottom wafer 20, and the sacrificial layer is exposed out of the first opening 311.
Wherein, if only the first sacrificial layer 25 is formed in the first bonding layer 24, the first opening 311 penetrates through the top wafer 30 and the second bonding layer 33 to expose the first sacrificial layer 25; if the second sacrificial layer 34 is formed in the top wafer 30 and the second bonding layer 33 only partially deeply, the first opening 311 exposes the second sacrificial layer 34; if the first sacrificial layer 25 is formed in the first bonding layer 24 and the second sacrificial layer 34 is formed in the top wafer 30 and the second bonding layer 33 in partial depth, the first opening 311 exposes the second sacrificial layer 34, as shown in fig. 3 j.
Since the entire thickness of the first bonding layer 24 on the area of the pad structure 23 is replaced by the first sacrificial layer 25 or a part of the thickness of the top wafer 30 is replaced by the second sacrificial layer 34, or the entire thickness of the first bonding layer 24 on the area of the pad structure 23 is replaced by the first sacrificial layer 25 and a part of the thickness of the top wafer 30 is replaced by the second sacrificial layer 34, such that the pad structure 23 can be exposed by a process of etching a portion of the thickness of the structure on the pad structure 23 (to form a low aspect ratio via) in combination with a process of removing the first sacrificial layer 25 and the second sacrificial layer 34 by an ashing process, the structure with the whole thickness on the pad structure 23 does not need to be removed by an etching process (the etching thickness is too thick, the process difficulty is high), and the process difficulty is reduced.
Subsequently, if the structure from the bottom of the first opening 311 to the pad structure 23 is removed, a second opening (i.e., the second opening 35 in fig. 3 m) exposing the pad structure 23 is formed. And, since the first bonding layer 24 and the second bonding layer 33 are formed between the top wafer 30 and the bottom wafer 20, the second opening 35 also penetrates through the first bonding layer 24 and the second bonding layer 33 to expose the pad structure 23.
Moreover, an insulating dielectric layer 36 may be further formed on the inner surface of the second opening 35, and the insulating dielectric layer 36 may further cover the top wafer 30 at the periphery of the second opening 35; and a third opening 37 is formed in the insulating medium layer 36 on the bottom surface of the second opening 35, and the third opening 37 exposes a part of the surface of the pad structure 23, so that the pad structure 23 can lead out the metal interconnection structure 221, that is, can lead out a signal in the bottom wafer 20.
As can be known from the structure of the semiconductor device, in the structure formed by bonding the top wafer and the bottom wafer, the pad structure is formed on the bottom wafer, so that the metal interconnection structure in the bottom wafer can be led out through the pad structure by opening the pad structure after the structure from the bottom of the first opening to the pad structure is removed, that is, signals in the bottom wafer are led out. Compared with the traditional structure that the top wafer is bonded on the bottom wafer and the pad structure is formed on the top wafer (such as three schemes in fig. 1), the invention leads out the metal interconnection structure in the bottom wafer directly through the pad structure on the bottom wafer, does not need to additionally manufacture the pad structure on the top wafer through complicated process steps after bonding, and there is no need to make a complicated metal interconnection structure electrically connected with the pad structure in the top wafer to lead out the metal interconnection structure in the bottom wafer, therefore, the manufacturing process of the pad structure is simplified, the length of the metal interconnection structure in the top wafer is shortened, and meanwhile, the parasitic capacitance corresponding to the pad structure is also reduced (i.e., the parasitic capacitance formed between the metal connecting line, the first insulating medium layer 13 and the first substrate 11 in the second and third schemes in fig. 1 is not generated).
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (11)
1. A method of manufacturing a semiconductor device, comprising:
providing a top wafer and a bottom wafer, wherein a metal interconnection structure is formed in the bottom wafer;
forming a pad structure on the bottom wafer, wherein the pad structure is electrically connected with the metal interconnection structure;
forming a sacrificial layer on the top wafer and/or the bottom wafer, bonding the top wafer and the bottom wafer, wherein the sacrificial layer is located between the pad structure and the surface of the top wafer far away from the bottom wafer, and the projection of the sacrificial layer and the pad structure in the direction perpendicular to the bonding surface at least partially coincides; and the number of the first and second groups,
and forming a first opening on the surface of the top wafer, which is far away from the bottom wafer, wherein the sacrificial layer is exposed out of the first opening.
2. The method for manufacturing a semiconductor device according to claim 1, further comprising: and removing the sacrificial layer by adopting an ashing process to form a second opening, wherein the second opening exposes the pad structure.
3. The method for manufacturing a semiconductor device according to claim 2, further comprising:
forming an insulating medium layer to cover the inner surface of the second opening;
and forming a third opening in the insulating medium layer on the bottom surface of the second opening, wherein the third opening exposes part of the surface of the bonding pad structure.
4. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the pad structure on the underlying wafer comprises:
forming a through hole in the bottom layer wafer, wherein the through hole exposes the metal interconnection structure;
forming a metal layer to cover the bottom wafer, wherein the metal layer fills the through hole; and the number of the first and second groups,
and etching and removing part of the metal layer on the bottom layer wafer to form a pad structure electrically connected with the metal interconnection structure.
5. The method of manufacturing a semiconductor device according to claim 1, wherein the method of forming the sacrificial layer on the underlying wafer comprises:
forming a bonding layer on the bottom wafer, wherein the bonding layer buries the pad structure inside;
forming a first sacrificial layer in the bonding layer, the first sacrificial layer being connected with the pad structure.
6. The method of manufacturing a semiconductor device according to claim 5, wherein the step of bonding the top wafer and the bottom wafer comprises:
forming a second sacrificial layer in the top wafer;
and bonding the top wafer and the bottom wafer, wherein the first sacrificial layer is connected with the second sacrificial layer in an aligned mode.
7. The method for manufacturing a semiconductor device according to claim 1, wherein a material of the sacrificial layer comprises a carbon-containing material.
8. A semiconductor device, comprising:
a bottom wafer having a metal interconnect structure;
a pad structure formed on the underlying wafer, the pad structure being electrically connected to the metal interconnect structure;
a top wafer bonded to the bottom wafer;
the sacrificial layer is formed on the top wafer and/or the bottom wafer, the sacrificial layer is positioned between the pad structure and the surface of the top wafer far away from the bottom wafer, and the projection of the sacrificial layer and the pad structure in the direction perpendicular to a bonding surface is at least partially overlapped; and the number of the first and second groups,
the first opening is formed in the surface, far away from the bottom wafer, of the top wafer, and the sacrificial layer is exposed out of the first opening.
9. The semiconductor device of claim 8, wherein the bottom wafer has a via formed therein exposing the metal interconnect structure, and the pad structure fills the via and covers a portion of the top surface of the bottom wafer.
10. The semiconductor device according to claim 8, further comprising:
a bonding layer located between the bottom wafer and the top wafer; and a first sacrificial layer formed in the bonding layer is used as the sacrificial layer formed on the bottom wafer, the first sacrificial layer is connected with the pad structure, and the bonding layer and the first sacrificial layer jointly bury the pad structure.
11. The semiconductor device according to claim 10,
and a second sacrificial layer formed in the top wafer is used as the sacrificial layer formed on the top wafer, and the first sacrificial layer is in aligned connection with the second sacrificial layer.
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