CN113346875B - Stripe camera high-voltage scanning pulse generating device - Google Patents
Stripe camera high-voltage scanning pulse generating device Download PDFInfo
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- CN113346875B CN113346875B CN202110884459.2A CN202110884459A CN113346875B CN 113346875 B CN113346875 B CN 113346875B CN 202110884459 A CN202110884459 A CN 202110884459A CN 113346875 B CN113346875 B CN 113346875B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/53—Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback
- H03K3/57—Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback the switching device being a semiconductor device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
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Abstract
The invention discloses a high-voltage scanning pulse generating device of a stripe camera, which comprises a time sequence generating circuit, a first pulse current source circuit, a first bias and reset accelerating circuit, a first speed regulating capacitor array, a first high-voltage module, a first scanning pulse coupling circuit, a second pulse current source circuit, a second bias and reset accelerating circuit, a second speed regulating capacitor array, a second high-voltage module and a second scanning pulse coupling circuit, wherein the first bias and reset accelerating circuit is connected with the first speed regulating capacitor array; the device of the invention can realize high linearity, adjustable slope range and repeated frequency operation, and improves the performance of the stripe camera.
Description
Technical Field
The invention belongs to the technical field of high-speed photography, and particularly relates to a high-voltage scanning pulse generating device of a stripe camera.
Background
The streak camera is also called an image converter tube scanning camera and is used for detecting and recording the ultrafast phenomenon. The camera captures a one-dimensional line image on a target image by using a slit and continuously records the process of the one-dimensional line image along with time, becomes an important diagnostic device in a high-speed photography technology due to the ultrahigh time resolution and the capability of continuously recording events, and is widely applied to the research fields of detonation physics, shock wave physics, accelerator physics, Inertial Confinement Fusion (ICF), laser and substance interaction and the like.
The high-voltage scanning circuit in the stripe camera is used for providing a linearly-changed scanning voltage to the 'stripe tube', and the electron beams in the stripe tube are uniformly swept on a fluorescent screen of the stripe tube along with time so as to obtain a scanning image with high time resolution. The slope of the scan voltage determines the recording length and time resolution of the stripe camera, and the linearity of the scan voltage determines the scan linearity of the stripe camera. In general, in the application of a stripe camera, different recording lengths are required for observing different experimental phenomena, and the slope of the scanning voltage is required to be adjustable in a large range. In addition, in research on biological fluorescence, plasma, material characteristics and the like, scanning voltage is required to be repeatedly scanned at a certain frequency with the same slope, and a weak signal is enhanced by an integration method.
Therefore, how to research and design a high-linearity, large-range adjustable slope and frequently-operating high-voltage scanning circuit of a streak tube is a problem which is urgently needed to be solved at present.
Disclosure of Invention
In view of the above problems, the present invention provides a high-voltage scanning pulse generator for a streak camera, which can provide a scanning voltage with high linearity, large-range adjustable slope and frequent triggering for a streak tube, thereby improving the performance of the streak camera.
The invention is realized by the following technical scheme:
a stripe camera high-voltage scanning pulse generating device comprises a time sequence generating circuit, a first pulse current source circuit, a first bias and reset accelerating circuit, a first speed-regulating capacitor array, a first high-voltage module, a first scanning pulse coupling circuit, a second pulse current source circuit, a second bias and reset accelerating circuit, a second speed-regulating capacitor array, a second high-voltage module and a second scanning pulse coupling circuit;
the time sequence generating circuit is used for outputting two paths of control pulses, namely a first path of control pulse and a second path of control pulse output after the first path of control pulse is finished;
the first pulse current source circuit is driven by the first path of control pulse to charge the first speed regulation capacitor array to generate a forward linear scanning pulse, and the first scanning pulse coupling circuit converts and outputs the forward linear scanning pulse; meanwhile, the second pulse current source circuit discharges to the second speed regulation capacitor array under the driving of the first path of control pulse to generate a negative linear scanning pulse, and the second scanning pulse coupling circuit converts and outputs the negative linear scanning pulse;
the first bias and reset accelerating circuit rapidly resets the voltage on the first speed-regulating capacitor array under the drive of the second path of control pulse, and simultaneously the second bias and reset accelerating circuit rapidly resets the voltage on the second speed-regulating capacitor array under the drive of the second path of control pulse to prepare for next scanning, thereby realizing the function of repeated frequency scanning;
the first high-voltage module is used for supplying power to the first bias voltage and reset accelerating circuit and the first scanning pulse coupling circuit;
the second high-voltage module is used for supplying power for the second bias voltage and reset accelerating circuit and the second scanning pulse coupling circuit.
Preferably, the first pulse current source circuit of the present invention includes a first MOSFET driver, a first PMOS transistor, a bias circuit, and a first resistor;
the bias circuit supplies power to the source electrode of the first PMOS tube through a first resistor, the first MOSFET driver is controlled by the first control pulse, negative pulses are output to drive the grid electrode of the first PMOS tube, and the drain electrode of the first PMOS tube is used as a current output end to output current, so that the capacitance voltage on the first speed-regulating capacitor array is linearly increased, and forward linear scanning pulses are generated.
Preferably, the second pulse current source circuit of the present invention includes a second MOSFET driver, a first NMOS transistor, and a second resistor;
the source electrode of the first NMOS tube is grounded through the second resistor;
the second MOSFET driver is controlled by the first path of control pulse, positive pulse is output to drive the grid electrode of the first NMOS tube, and the drain electrode of the first NMOS tube is used as a current input end to input current, so that the capacitance voltage on the second speed-regulating capacitor array is linearly reduced, and negative linear scanning pulse is generated.
Preferably, the first bias and reset accelerating circuit of the present invention comprises a third MOSFET driver, a first coupling capacitor, a first bias resistor, and a second NMOS transistor;
the first high-voltage module provides pre-charging voltage for the first speed-regulating capacitor array through the first bias resistor, so that when the first pulse current source circuit outputs current, a forward linear scanning pulse can be generated on the first speed-regulating capacitor array;
and the third MOSFET driver outputs positive pulses under the drive of the second path of control pulses, and the positive pulses are coupled to the grid electrode of the second NMOS tube through the first coupling capacitor, so that the second NMOS tube is quickly conducted, the voltage on the first speed regulating capacitor array is quickly reset to negative high voltage, and the next scanning is waited.
Preferably, the second bias and reset accelerating circuit of the present invention includes a fourth MOSFET driver, a second coupling capacitor, a second bias resistor, and a second PMOS transistor;
the second high-voltage module provides a pre-charging voltage for the second speed-regulating capacitor array through the second bias resistor, so that when current is input to the second pulse current source circuit, a linearly-changing negative scanning pulse can be generated on the second speed-regulating capacitor array;
and the fourth MOSFET driver outputs negative pulses under the driving of the second path of control pulses, and the negative pulses are coupled to the grid electrode of the second PMOS tube through the second coupling capacitor, so that the second PMOS tube is quickly conducted, the voltage on the second speed-regulating capacitor array is quickly reset to positive high voltage, and the next scanning is waited.
Preferably, the first speed-regulating capacitor array and the second speed-regulating capacitor array of the invention both comprise a plurality of capacitors and selection switches, different capacitors are selected to be connected into the circuit through the selection switches, and the positive and negative symmetrical linear scanning voltages with various selectable slopes are respectively realized by matching with the first pulse current source circuit and the second pulse current source circuit.
Preferably, the first speed-adjusting capacitor array of the present invention includes a plurality of series branches formed by serially connecting first capacitors and first selection switches, and one end of each of the first capacitors in the plurality of series branches is connected together and grounded, and the other end of each of the first capacitors in the plurality of series branches is connected to the first forward scan voltage generation end after passing through the first selection switch.
Preferably, the second speed-adjusting capacitor array of the present invention includes a plurality of series branches formed by connecting second capacitors and second selection switches in series, and one end of each of the second capacitors in the plurality of series branches is connected together and grounded, and the other end of each of the second capacitors in the plurality of series branches is connected to the first negative-direction scanning voltage generation end after passing through the second selection switch.
Preferably, the first scanning pulse coupling circuit of the present invention is configured to shift the positive linear scanning pulse generated by the first speed-adjusting capacitor array from a negative high voltage to 0V upwards to form a positive linear scanning voltage output from the negative high voltage to the positive high voltage.
Preferably, the second scan pulse coupling circuit of the present invention is configured to shift downward a negative linear scan pulse generated by the second speed adjusting capacitor array and changing from a positive high voltage to 0V, so as to form a negative linear scan voltage output changing from a positive high voltage to a negative high voltage.
The invention has the following advantages and beneficial effects:
compared with the prior art, the high-voltage scanning pulse generating device has the characteristics of high linearity, large-range adjustable slope and capability of working at repeated frequency, and the performance of the streak camera is improved. On the premise of ensuring that the scanning nonlinearity is better than 4%, the differential scanning voltage slope can be adjusted in a large range from 35000000V/ms to 350V/ms, and the highest repetition frequency can reach MHz;
the invention has wide application range and can provide high-voltage linear scanning pulse for a plurality of streak tube types at home and abroad.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
fig. 1 is a general schematic block diagram of a method and an apparatus for generating high-voltage scanning pulses of a streak camera according to the present invention.
FIG. 2 is a schematic diagram of timing pulses output by the timing generation circuit.
Fig. 3 is a schematic diagram of a first pulse current source circuit.
Fig. 4 is a schematic diagram of a second pulse current source circuit.
FIG. 5 is a schematic diagram of a first bias and reset accelerating circuit.
FIG. 6 is a schematic diagram of a second bias and reset accelerating circuit.
FIG. 7 is a schematic diagram of a first speed regulating capacitor array.
FIG. 8 is a schematic diagram of a second speed regulating capacitor array.
Fig. 9 is a schematic diagram of a first scan pulse coupling circuit.
Fig. 10 is a schematic diagram of a second scan pulse coupling circuit.
Reference numbers and corresponding part names in the drawings:
101. a timing generation circuit; 111. a first pulse current source circuit; 112. a first bias and reset accelerating circuit; 113. a first speed regulating capacitor array; 114. a first high voltage module; 115. a first scan pulse coupling circuit; 121. a second pulse current source circuit; 122. a second bias and reset accelerating circuit; 123. a second speed regulating capacitor array; 124. a second high voltage module; 125. a second scan pulse coupling circuit;
201. a first path of control pulse; 202. a second path of control pulse;
301. an input terminal of a first pulse current source circuit; 302. a first MOSFET driver; 303. a bias circuit; 304. a first resistor; 305. a first PMOS tube; 306. a current output terminal of the first pulse current source circuit;
401. an input terminal of a second pulse current supply circuit; 402. a second MOSFET driver; 403. a first NMOS transistor; 404. a second resistor; 405. a current input terminal of the second pulse current supply circuit;
501. an input terminal of a first bias and reset accelerating circuit; 502. a third MOSFET driver; 503. a first coupling capacitor; 504. a third resistor; 505. a first diode; 506. a second NMOS transistor; 507. a first bias resistor; 508. a first bias and reset voltage output terminal; 509. a first negative high voltage supply terminal;
601. an input terminal of a second bias and reset accelerating circuit; 602. a fourth MOSFET driver; 603. a second coupling capacitor; 604. a fourth resistor; 605. a second diode; 606. a second PMOS tube; 607. a second bias resistor; 608. a first positive high voltage supply terminal; 609. a second bias and reset voltage output terminal;
701. a first forward direction scan voltage generating terminal; 702. a first selection switch; 703. a first capacitor;
801. a first negative-direction scanning voltage generating terminal; 802. a second selection switch; 803. a second capacitor;
901. a second forward direction scan voltage generation terminal; 902. a third coupling capacitor; 903. a first voltage dividing resistor; 904. a second voltage dividing resistor; 905. a first single pole double throw switch; 906. a fifth resistor; 907. a first matching resistor; 908. a forward scan voltage output; 909. a second negative high voltage supply terminal;
1001. a second negative-direction scanning voltage generating terminal; 1002. a fourth coupling capacitor; 1003. a third voltage dividing resistor; 1004. a fourth voltage dividing resistor; 1005. a second single pole double throw switch; 1006. a sixth resistor; 1007. a second matching resistor; 1008. a negative scan voltage output terminal; 1009. a second positive high voltage supply terminal.
Detailed Description
Hereinafter, the term "comprising" or "may include" used in various embodiments of the present invention indicates the presence of the invented function, operation or element, and does not limit the addition of one or more functions, operations or elements. Furthermore, as used in various embodiments of the present invention, the terms "comprises," "comprising," "includes," "including," "has," "having" and their derivatives are intended to mean that the specified features, numbers, steps, operations, elements, components, or combinations of the foregoing, are only meant to indicate that a particular feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as first excluding the existence of, or adding to the possibility of, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
In various embodiments of the invention, the expression "or" at least one of a or/and B "includes any or all combinations of the words listed simultaneously. For example, the expression "a or B" or "at least one of a or/and B" may include a, may include B, or may include both a and B.
Expressions (such as "first", "second", and the like) used in various embodiments of the present invention may modify various constituent elements in various embodiments, but may not limit the respective constituent elements. For example, the above description does not limit the order and/or importance of the elements described. The foregoing description is for the purpose of distinguishing one element from another. For example, the first user device and the second user device indicate different user devices, although both are user devices. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of various embodiments of the present invention.
It should be noted that: if it is described that one constituent element is "connected" to another constituent element, the first constituent element may be directly connected to the second constituent element, and a third constituent element may be "connected" between the first constituent element and the second constituent element. In contrast, when one constituent element is "directly connected" to another constituent element, it is understood that there is no third constituent element between the first constituent element and the second constituent element.
The terminology used in the various embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the invention. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Examples
As shown in fig. 1, the apparatus of this embodiment includes a timing generation circuit 101, a first pulse current source circuit 111, a first bias and reset acceleration circuit 112, a first speed-adjusting capacitor array 113, a first high-voltage module 114, a first scan pulse coupling circuit 115, a second pulse current source circuit 121, a second bias and reset acceleration circuit 122, a second speed-adjusting capacitor array 123, a second high-voltage module 124, and a second scan pulse coupling circuit 125.
The timing generation circuit 101 uses a programmable logic array (FPGA or CPLD) to generate two control pulses after being triggered by an input pulse, as shown in fig. 2. The first path of control pulse 201 drives the first pulse current source circuit 111 to charge the first speed-regulating capacitor array 113, and generates a forward (voltage changes from-HV to 0V) linear scanning pulse; the first control pulse 201 drives the second pulse current source circuit 121 to discharge to the second speed-adjusting capacitor array 123, and generates a negative-going (voltage changes from + HV to 0V) linear scan pulse. The second path of control pulse 202 is output after the first path of control pulse 201 is finished, and is used for driving the first bias and reset accelerating circuit 112 to quickly reset the voltage on the first speed-regulating capacitor array 113; and driving the second bias and reset accelerating circuit 122 to quickly reset the voltage on the second speed-adjusting capacitor array 123, so as to prepare for next scanning, thereby implementing the function of repeated frequency scanning.
The first pulse current source circuit 111 of this embodiment is a charging type pulse current source circuit, and as shown in fig. 3, includes a first MOSFET driver 302, a first PMOS transistor 305, a bias circuit 303, and a first resistor 304. Wherein the bias circuit 303 supplies power to the source of the first PMOS transistor 305 through the first resistor 304. The first path of control pulse 201 generated by the timing generation circuit 101 is input from the input terminal 301 of the first pulse current source circuit 111, drives the gate of the first PMOS transistor 305 through the first MOSFET driver 302 (the first MOSFET driver outputs a negative pulse), and outputs a current from the current output terminal 306 (i.e., the drain of the first PMOS transistor) of the first pulse current source circuit 111, so that the capacitor voltage on the first speed-adjusting capacitor array 113 is linearly increased, and a linearly changing forward scan pulse is generated.
The second pulse current source circuit 121 of this embodiment is a discharge type pulse current source circuit, as shown in fig. 4, and includes a second MOSFET driver 402, a first NMOS transistor 403, and a second resistor 404, where a source of the first NMOS transistor is grounded through the second resistor 404. The first path of control pulse 201 generated by the timing generation circuit 101 is input from the input end 401 of the second pulse current supply circuit 121, the gate of the first NMOS transistor is driven by the second MOSFET driver 402, and the current is input from the current input end 405 (i.e., the drain of the first NMOS transistor) of the second pulse current supply circuit 121, so that the capacitor voltage on the second speed-adjusting capacitor array 123 is linearly decreased, and a linearly changing negative-direction scan pulse is generated.
The first bias and reset accelerating circuit 112 of this embodiment is used to provide a negative bias to the first speed-adjusting capacitor array 113, and quickly reset the voltage on the first speed-adjusting capacitor array 113 to an initial negative bias state after the first pulse current source circuit 111 charges the first speed-adjusting capacitor array 113 to generate a positive scan voltage. As shown in fig. 5, the MOSFET driver includes a third MOSFET driver 502, a first coupling capacitor 503, a first bias resistor 507, a second NMOS transistor 506, a third resistor 504, and a first diode 505. The first negative high voltage supply terminal 509 (the supply voltage is represented by-HV) provides a pre-charge voltage from the first bias and reset voltage output terminal 508 to the first speed-adjusting capacitor array 113 through the first bias resistor 507, so that when the first pulse current source circuit 111 outputs a current, a linearly changing forward scan pulse can be generated on the first speed-adjusting capacitor array 113. When the forward scan pulse ends, the second path of control pulse 202 generated by the timing generation circuit 101 is input from the input terminal 501 of the first bias and reset accelerating circuit 112, drives the third MOSFET driver 502 to output a positive pulse, and is coupled to the gate of the second NMOS transistor 506 through the first coupling capacitor 503, so that the second NMOS transistor 506 is rapidly turned on, and pulls the voltage on the first speed-adjusting capacitor array 113 to the initial negative bias state, i.e., rapidly resets to the negative high voltage (-HV), and waits for the next scan. The third resistor 504 and the first diode 505 are peripheral components of the second NMOS transistor 506, and cooperate with the second NMOS transistor 506 to complete the switching operation of the repetition frequency.
The first high voltage module 114 of this embodiment outputs a negative high voltage, provides a bias voltage to the first speed adjusting capacitor array 113 through the first bias resistor 507 of the first bias and reset accelerating circuit 112, supplies power to the source of the second NMOS transistor 506 in the first bias and reset accelerating circuit 112, provides a reset accelerating voltage, and also supplies power to the first scan pulse coupling circuit 115.
The second bias and reset accelerating circuit 122 of this embodiment is configured to provide a positive bias to the second speed-adjusting capacitor array 123, and quickly reset the voltage on the second speed-adjusting capacitor array 123 to an initial positive bias state after the second pulse current source circuit 121 finishes discharging the negative scanning voltage generated by the second speed-adjusting capacitor array 123. As shown in fig. 6, the MOSFET driver includes a fourth MOSFET driver 602, a second coupling capacitor 603, a second bias resistor 607, a second PMOS transistor, a fourth resistor 604, and a second diode 605. The first positive high voltage supply terminal 608 (the supply voltage is represented by + HV) provides a precharge voltage from the second bias and reset voltage output terminal 609 to the second speed-adjusting capacitor array 123 through the second bias resistor 607, so that when the second pulse current source circuit 121 inputs a current, a linearly changing negative scan pulse can be generated on the second speed-adjusting capacitor array 123. When the negative scan pulse ends, the second path of control pulse 202 generated by the timing generation circuit 101 is input from the input terminal 601 of the second bias and reset accelerating circuit 122, drives the fourth MOSFET driver 602 to output a negative pulse, and is coupled to the gate of the second PMOS transistor 606 through the second coupling capacitor 603, so that the second PMOS transistor 606 is rapidly turned on, and pulls the voltage on the second speed-adjusting capacitor array 123 to the initial positive bias state, i.e., rapidly resets to the positive high voltage (+ HV), and waits for the next scan. The fourth resistor 604 and the second diode 605 are peripheral components of the second PMOS transistor 606, and cooperate with the second PMOS transistor to complete the switching operation of the repetition frequency.
The second high voltage module 124 of this embodiment outputs a positive high voltage, and provides a bias voltage to the second speed adjusting capacitor array 123 through the second bias resistor 607 of the second bias and reset accelerating circuit 122, and supplies power to the source of the second PMOS transistor in the second bias and reset accelerating circuit to provide a reset accelerating voltage, and also supplies power to the second scan pulse coupling circuit 125.
The first speed-adjusting capacitor array 113 of this embodiment includes a plurality of capacitors and a selection switch, and the selection switch selects different capacitors to access the circuit, and cooperates with the first pulse current source circuit 111 to implement a plurality of slope-selectable linear scan voltages. As shown in fig. 7, a plurality of series branches formed by serially connecting a first capacitor 703 and a first selection switch 702 are included, and one end of the first capacitor 703 in the plurality of series branches is connected together and grounded, and the other end is connected to the first forward scan voltage generation terminal 701 after passing through the first selection switch 702. The first selection switch 702 of this embodiment is a single pole, single throw switch.
The first pulse current source circuit 111 charges the first speed-adjusting capacitor array 113 through the first forward scan voltage generation terminal 701 to generate a linearly rising scan voltage, and the first capacitor 703 is selectively connected by turning on the corresponding single-pole single-throw switch, thereby changing the slope of the increase of the scan voltage.
The second speed-adjusting capacitor array 123 of this embodiment includes a plurality of capacitors and a selection switch, and the selection switch selects different capacitors to access the circuit, and cooperates with the second pulse current source circuit 121 to implement a plurality of slope-selectable linear scan voltages. As shown in fig. 8, the scanning circuit includes a plurality of series branches formed by serially connecting a second capacitor 803 and a second selection switch 802, and one end of the second capacitor 803 in the plurality of series branches is connected together and grounded, and the other end is connected to the first negative-direction scanning voltage generating terminal 801 after passing through the second selection switch 802. The second selection switch 802 of this embodiment is a single pole single throw switch.
The second pulse current source circuit 121 absorbs current from the second speed-adjusting capacitor array 123 through the first negative-going scanning voltage generating terminal 801 to generate a linearly-decreasing scanning voltage, and the slope of the decrease of the scanning voltage is changed by turning on the corresponding single-pole single-throw switch to select the connected second capacitor 803.
The first scanning pulse coupling circuit 115 of the present embodiment functions to shift up the linear scanning voltage varying from the negative high voltage to around 0V, forming a linear scanning voltage varying from the negative high voltage to the positive high voltage. As shown in fig. 9, the circuit includes a third coupling capacitor 902, a first voltage-dividing resistor 903, a second voltage-dividing resistor 904, a first single-pole double-throw switch 905, a fifth resistor 906, and a first matching resistor 907. The scan voltage at the second forward scan voltage generation terminal 901 is a linear scan voltage varying from-HV to 0V, and is coupled to the voltage divider network formed by the first voltage divider resistor 903 and the second voltage divider resistor 904 through the third coupling capacitor 902, so as to be converted into a scan voltage varying from-HV/2 to + HV/2. The first single-pole double-throw switch 905 is used for selectively outputting a scan voltage (outputting the scan voltage through the forward scan voltage output terminal via the first matching resistor 907) or a static voltage (grounding via the fifth resistor 906). The first scan pulse coupling circuit 115 is powered by the first high voltage module 114 through the second negative high voltage power supply 909.
The second scan pulse coupling circuit 125 of the present embodiment functions to shift down the linear scan voltage varying from the positive high voltage to 0V, forming a linear scan voltage varying from the positive high voltage to the negative high voltage. As shown in fig. 10, the circuit includes a fourth coupling capacitor 1002, a third matching resistor 1003, a fourth matching resistor 1004, a second single-pole double-throw switch 1005, a sixth resistor 1006, and a second matching resistor 1007. The scanning voltage at the second negative-going scanning voltage generation terminal 1001 is a linear scanning voltage varying from + HV to 0V, and is coupled to a voltage division network formed by a third matching resistor 1003 and a fourth matching resistor 1004 through a fourth coupling capacitor 1002, so as to be converted into a scanning voltage varying from + HV/2 to-HV/2. The single-pole double-throw switch 1005 is used to select the scan voltage (output through the second matching resistor 1007 via the negative scan voltage output terminal 1008) or the static voltage (grounded through the sixth resistor 1006). The second scan pulse coupling circuit 125 is powered by the second high voltage module 124 through the second positive high voltage power terminal 1009.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
1. A stripe camera high-voltage scanning pulse generation device is characterized by comprising a time sequence generation circuit (101), a first pulse current source circuit (111), a first bias and reset acceleration circuit (112), a first speed regulation capacitor array (113), a first high-voltage module (114), a first scanning pulse coupling circuit (115), a second pulse current source circuit (121), a second bias and reset acceleration circuit (122), a second speed regulation capacitor array (123), a second high-voltage module (124) and a second scanning pulse coupling circuit (125);
the time sequence generating circuit (101) is used for outputting two paths of control pulses, namely a first path of control pulse (201) and a second path of control pulse (202) output after the first path of control pulse (201) is finished;
the first pulse current source circuit (111) is driven by the first path of control pulse (201) to charge the first speed regulation capacitor array (113) to generate a forward linear scanning pulse, and the first scanning pulse coupling circuit (115) converts and outputs the forward linear scanning pulse; meanwhile, the second pulse current source circuit (121) discharges to the second speed-regulating capacitor array (123) under the drive of the first path of control pulse (201) to generate a negative linear scanning pulse, and the second scanning pulse coupling circuit (125) converts and outputs the negative linear scanning pulse;
the first bias and reset accelerating circuit (112) rapidly resets the voltage on the first speed-regulating capacitor array (113) under the drive of the second path of control pulse (202), and the second bias and reset accelerating circuit (122) rapidly resets the voltage on the second speed-regulating capacitor array (123) under the drive of the second path of control pulse (202) to prepare for next scanning, thereby realizing the function of repeated frequency scanning;
the first high voltage module (114) is used for supplying power to the first bias voltage and reset accelerating circuit (112) and the first scanning pulse coupling circuit (115);
the second high voltage module (124) is used for supplying power to the second bias voltage and reset accelerating circuit (122) and the second scanning pulse coupling circuit (125);
the first scanning pulse coupling circuit (115) is used for translating the positive linear scanning pulse which is generated by the first speed regulating capacitor array (113) and changes from negative high voltage to 0V upwards to form positive linear scanning voltage output which changes from negative high voltage to positive high voltage;
the second scanning pulse coupling circuit (125) is used for translating the negative linear scanning pulse which is generated by the second speed regulating capacitor array (123) and changes from the positive high voltage to 0V downwards to form negative linear scanning voltage output which changes from the positive high voltage to the negative high voltage.
2. The streak camera high voltage scanning pulse generating device according to claim 1, wherein the first pulse current source circuit (111) comprises a first MOSFET driver (302), a first PMOS transistor (305), a bias circuit (303) and a first resistor (304);
the bias circuit (303) supplies power to the source of the first PMOS transistor (305) through a first resistor (304), the first MOSFET driver (302) is controlled by the first control pulse (201), negative pulses are output to drive the gate of the first PMOS transistor (305), and the drain of the first PMOS transistor (305) is used as a current output end to output current, so that the voltage of a capacitor on the first speed-adjusting capacitor array (113) is linearly increased, and a forward linear scanning pulse is generated.
3. The streak camera high voltage scanning pulse generating device according to claim 1, wherein said second pulse current source circuit (121) comprises a second MOSFET driver (402), a first NMOS transistor (403), and a second resistor (404);
wherein the source of the first NMOS transistor (403) is grounded through the second resistor (404);
the second MOSFET driver (402) is controlled by the first path of control pulse (201), positive pulses are output to drive the grid electrode of the first NMOS tube (403), the drain electrode of the first NMOS tube (403) is used as a current input end to input current, so that the capacitance voltage on the second speed-regulating capacitor array (123) is linearly reduced, and negative linear scanning pulses are generated.
4. The streak camera high voltage scanning pulse generating device according to claim 1, wherein the first bias and reset accelerating circuit (112) comprises a third MOSFET driver (502), a first coupling capacitor (503), a first bias resistor (507), a second NMOS transistor (506);
the first high-voltage module (114) provides a pre-charging voltage for the first speed-regulating capacitor array (113) through the first bias resistor (507), so that when the first pulse current source circuit (111) outputs current, a forward linear scanning pulse can be generated on the first speed-regulating capacitor array (113);
and the third MOSFET driver (502) outputs a positive pulse under the driving of the second path of control pulse (202), and is coupled to the grid electrode of the second NMOS tube (506) through the first coupling capacitor (503), so that the second NMOS tube (506) is rapidly conducted, the voltage on the first speed-regulating capacitor array (113) is rapidly reset to a negative high voltage, and the next scanning is waited.
5. The streak camera high voltage scanning pulse generating device according to claim 3, wherein the second bias and reset accelerating circuit (122) comprises a fourth MOSFET driver (602), a second coupling capacitor (603), a second bias resistor (607), and a second PMOS transistor (606);
the second high-voltage module (124) provides a pre-charge voltage for the second speed-regulating capacitor array (123) through the second bias resistor (607), so that when the second pulse current source circuit (121) inputs current, a linearly-changing negative-direction scanning pulse can be generated on the second speed-regulating capacitor array (123);
the fourth MOSFET driver (602) outputs negative pulses under the driving of the second path of control pulses (202), and is coupled to the grid electrode of the second PMOS tube (606) through the second coupling capacitor (603), so that the second PMOS tube (606) is rapidly conducted, the voltage on the second speed-regulating capacitor array (123) is rapidly reset to positive high voltage, and the next scanning is waited.
6. The streak camera high-voltage scanning pulse generating device according to claim 1, wherein the first speed-adjusting capacitor array (113) and the second speed-adjusting capacitor array (123) each comprise a plurality of capacitors and a selection switch, different capacitors are selected by the selection switch to be connected to a circuit, and the first pulse current source circuit (111) and the second pulse current source circuit (121) are respectively matched to realize multiple slope-selectable positive and negative symmetrical linear scanning voltages.
7. The streak camera high voltage scanning pulse generation device according to claim 6, wherein the first speed adjusting capacitor array (113) comprises a plurality of series branches formed by serially connecting a first capacitor (703) and a first selection switch (702), and one end of the first capacitor (703) in the plurality of series branches is connected together and grounded, and the other end is connected to the first forward scanning voltage generation terminal (701) through the first selection switch (702).
8. The streak camera high voltage scanning pulse generating apparatus according to claim 6, wherein the second timing capacitor array (123) comprises a plurality of series branches formed by connecting the second capacitors (803) and the second selection switch (802) in series, and one end of the second capacitors (803) in the plurality of series branches is connected together and grounded, and the other end is connected to the first negative scanning voltage generating terminal (801) through the second selection switch (802).
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