CN113346606A

CN113346606A - Hood type FTU backup power supply super capacitor module

Info

Publication number: CN113346606A
Application number: CN202110524362.0A
Authority: CN
Inventors: 黄辉琴; 于丽娇; 陈治国; 齐斌
Original assignee: Cloud Valley Technology Zhuhai Co ltd
Current assignee: Cloud Valley Technology Zhuhai Co ltd
Priority date: 2021-05-13
Filing date: 2021-05-13
Publication date: 2021-09-03
Anticipated expiration: 2041-05-13
Also published as: CN113346606B

Abstract

The invention provides a cover type FTU backup power supply super capacitor module, and relates to the technical field of power supply circuits. The capacitor comprises a capacitor main body module consisting of a plurality of capacitor units; the capacitor main body module is provided with an overvoltage protection circuit, a reverse connection protection circuit, a voltage sampling circuit, a current sampling circuit and a main circuit; the method can monitor the electric parameters of the super capacitor module in real time so as to ensure that the backup power supply can be normally used in a long-term floating state, thereby improving the reliability of the operation of the cover-type FTU; meanwhile, reverse connection protection is arranged, so that damage to the power supply module and safety accidents caused by the power supply module are avoided.

Description

Hood type FTU backup power supply super capacitor module

Technical Field

The invention relates to the technical field of power supply circuits, in particular to a hood-type FTU backup power supply super capacitor module.

Background

The cover type FTU backup power supply is mainly used for supplying power by the backup power supply after the power failure of a cover type FTU main power supply, when a power grid line fails, the cover type FTU on the line is powered down due to the fact that the main power supply fails, the main power supply of the cover type FTU is automatically switched to the cover type FTU backup power supply after the power failure, the cover type FTU can continue to work after the power failure of the main power supply, and fault removal is carried out after the fault on the line is judged and fault information is sent to a master station background.

The existing super capacitor module has the following problems when in use: 1. the system only has a single energy storage function and cannot monitor the running electrical parameters of the super capacitor module in real time; 2. the positive electrode and the negative electrode of the conventional super capacitor module are not protected in a reverse connection mode, and once the super capacitor module is connected with a reverse charging super capacitor, the super capacitor module can explode to cause damage to a power module and safety accidents.

Disclosure of Invention

The invention aims to provide a hood-type FTU backup power supply super capacitor module which can monitor the running electrical parameters of the super capacitor module in real time and is provided with reverse connection protection, so that the damage of the power supply module and the occurrence of safety accidents are avoided.

The embodiment of the invention is realized by the following steps:

the embodiment of the application provides a hood-type FTU backup power supply super capacitor module, which comprises a capacitor main body module consisting of a plurality of capacitor monomers; the capacitor main body module is provided with an overvoltage protection circuit, a reverse connection protection circuit, a voltage sampling circuit, a current sampling circuit and a main circuit. In some embodiments of the present invention, the reverse connection protection circuit includes a rectifier bridge D15, the 2 nd pin and the 3 rd pin of the rectifier bridge D15 are connected to the positive pole and the negative pole of the power input terminal, and the 1 st pin and the 4 th pin of the rectifier bridge D15 are connected to the overvoltage protection circuit.

In some embodiments of the present invention, the overvoltage protection circuit includes a voltage detection chip U2, a voltage detection chip U14, a MOS tube U14, a resistor R36r 14, a resistor R36r 14, a resistor R36r 14, a resistor R36r 14, a resistor R36r 14, a resistor R14, a resistor R36r 14, a resistor R36r 14, a resistor 36r 14, a resistor R36r 14, a resistor R14, a resistor R36r 14, a resistor R36r 14, a resistor R36r 14, a resistor R36r 14, a resistor R14, a resistor, The circuit comprises a resistor R77, a polar capacitor C1, a polar capacitor C37, a polar capacitor C8, a polar capacitor C39, a polar capacitor C40, a polar capacitor C41, a polar capacitor C42, a polar capacitor C43, a polar capacitor C44 and a polar capacitor C45; the 2 nd pin of the voltage detection chip U2 is connected with the cathode of the polar capacitor C1, and the anode of the polar capacitor C1 is connected with the 3 rd pin of the voltage detection chip U2; a 2 nd pin of the voltage detection chip U2 is connected with an S pole of the MOS tube U1, a G pole of the MOS tube U1 is connected with a 1 st pin of the voltage detection chip U2, a D pole of the MOS tube U1 is respectively connected with one ends of a resistor R1, a resistor R2 and a resistor R3, and the other ends of the resistor R1, a resistor R2 and the resistor R3 are connected with a 3 rd pin of the voltage detection chip U2; the 3 rd pin of the voltage detection chip U2 is connected with the 2 nd pin of the voltage detection chip U14, the 2 nd pin of the voltage detection chip U14 is connected with the cathode of the polar capacitor C37, and the anode of the polar capacitor C37 is connected with the 3 rd pin of the voltage detection chip U14; a 2 nd pin of the voltage detection chip U14 is connected with an S pole of the MOS tube U13, a G pole of the MOS tube U13 is connected with a 1 st pin of the voltage detection chip U14, a D pole of the MOS tube U13 is respectively connected with one ends of a resistor R51, a resistor R52 and a resistor R53, and the other ends of the resistor R51, a resistor R52 and the resistor R53 are connected with a 3 rd pin of the voltage detection chip U14; the 3 rd pin of the voltage detection chip U14 is connected with the 2 nd pin of the voltage detection chip U16, the 2 nd pin of the voltage detection chip U16 is connected with the cathode of the polar capacitor C38, and the anode of the polar capacitor C38 is connected with the 3 rd pin of the voltage detection chip U16; a 2 nd pin of the voltage detection chip U16 is connected with an S pole of the MOS tube U15, a G pole of the MOS tube U15 is connected with a 1 st pin of the voltage detection chip U16, a D pole of the MOS tube U15 is respectively connected with one ends of a resistor R54, a resistor R55 and a resistor R56, and the other ends of the resistor R54, a resistor R55 and the resistor R56 are connected with a 3 rd pin of the voltage detection chip U16; the 3 rd pin of the voltage detection chip U16 is connected with the 2 nd pin of the voltage detection chip U18, the 2 nd pin of the voltage detection chip U18 is connected with the cathode of the polar capacitor C39, and the anode of the polar capacitor C39 is connected with the 3 rd pin of the voltage detection chip U18; a 2 nd pin of the voltage detection chip U18 is connected with an S pole of the MOS tube U17, a G pole of the MOS tube U17 is connected with a 1 st pin of the voltage detection chip U18, a D pole of the MOS tube U17 is respectively connected with one ends of a resistor R57, a resistor R58 and a resistor R59, and the other ends of the resistor R57, a resistor R58 and the resistor R59 are connected with a 3 rd pin of the voltage detection chip U18; the 3 rd pin of the voltage detection chip U18 is connected with the 2 nd pin of the voltage detection chip U20, the 2 nd pin of the voltage detection chip U20 is connected with the cathode of the polar capacitor C40, and the anode of the polar capacitor C40 is connected with the 3 rd pin of the voltage detection chip U20; a 2 nd pin of the voltage detection chip U20 is connected with an S pole of the MOS tube U19, a G pole of the MOS tube U19 is connected with a 1 st pin of the voltage detection chip U20, a D pole of the MOS tube U19 is respectively connected with one ends of a resistor R60, a resistor R61 and a resistor R62, and the other ends of the resistor R60, a resistor R61 and the resistor R62 are connected with a 3 rd pin of the voltage detection chip U20; the 3 rd pin of the voltage detection chip U20 is connected with the 2 nd pin of the voltage detection chip U22, the 2 nd pin of the voltage detection chip U22 is connected with the cathode of the polar capacitor C41, and the anode of the polar capacitor C41 is connected with the 3 rd pin of the voltage detection chip U22; a 2 nd pin of the voltage detection chip U22 is connected with an S pole of the MOS tube U21, a G pole of the MOS tube U21 is connected with a 1 st pin of the voltage detection chip U22, a D pole of the MOS tube U21 is respectively connected with one ends of a resistor R63, a resistor R64 and a resistor R65, and the other ends of the resistor R63, a resistor R64 and the resistor R65 are connected with a 3 rd pin of the voltage detection chip U22; the 3 rd pin of the voltage detection chip U22 is connected with the 2 nd pin of the voltage detection chip U24, the 2 nd pin of the voltage detection chip U24 is connected with the cathode of the polar capacitor C42, and the anode of the polar capacitor C42 is connected with the 3 rd pin of the voltage detection chip U24; a 2 nd pin of the voltage detection chip U24 is connected with an S pole of the MOS tube U23, a G pole of the MOS tube U23 is connected with a 1 st pin of the voltage detection chip U24, a D pole of the MOS tube U23 is respectively connected with one ends of a resistor R66, a resistor R67 and a resistor R68, and the other ends of the resistor R66, a resistor R67 and the resistor R68 are connected with a 3 rd pin of the voltage detection chip U24; the 3 rd pin of the voltage detection chip U24 is connected with the 2 nd pin of the voltage detection chip U26, the 2 nd pin of the voltage detection chip U26 is connected with the cathode of the polar capacitor C43, and the anode of the polar capacitor C43 is connected with the 3 rd pin of the voltage detection chip U26; a 2 nd pin of the voltage detection chip U26 is connected with an S pole of the MOS tube U25, a G pole of the MOS tube U25 is connected with a 1 st pin of the voltage detection chip U26, a D pole of the MOS tube U25 is respectively connected with one ends of a resistor R69, a resistor R70 and a resistor R71, and the other ends of the resistor R69, a resistor R70 and the resistor R71 are connected with a 3 rd pin of the voltage detection chip U26; the 3 rd pin of the voltage detection chip U26 is connected with the 2 nd pin of the voltage detection chip U28, the 2 nd pin of the voltage detection chip U28 is connected with the cathode of the polar capacitor C44, and the anode of the polar capacitor C44 is connected with the 3 rd pin of the voltage detection chip U28; a 2 nd pin of the voltage detection chip U28 is connected with an S pole of the MOS tube U27, a G pole of the MOS tube U27 is connected with a 1 st pin of the voltage detection chip U28, a D pole of the MOS tube U27 is respectively connected with one ends of a resistor R72, a resistor R73 and a resistor R74, and the other ends of the resistor R72, a resistor R73 and the resistor R74 are connected with a 3 rd pin of the voltage detection chip U28; the 3 rd pin of the voltage detection chip U28 is connected with the 2 nd pin of the voltage detection chip U30, the 2 nd pin of the voltage detection chip U30 is connected with the cathode of the polar capacitor C45, and the anode of the polar capacitor C45 is connected with the 3 rd pin of the voltage detection chip U30; a 2 nd pin of the voltage detection chip U30 is connected with an S pole of the MOS tube U29, a G pole of the MOS tube U29 is connected with a 1 st pin of the voltage detection chip U30, a D pole of the MOS tube U29 is respectively connected with one ends of a resistor R75, a resistor R76 and a resistor R77, and the other ends of the resistor R75, a resistor R76 and the resistor R77 are connected with a 3 rd pin of the voltage detection chip U30; the 1 st pin and the 4 th pin of the rectifier bridge are respectively connected with the 2 nd pin of the voltage detection chip U2 and the 3 rd pin of the voltage detection chip U30.

In some embodiments of the present invention, the main circuit includes a processor U31, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a crystal oscillator Y12, a resistor R12, a capacitor C157, a capacitor C158, an LED 12, a TVS tube s 12, a TVS 12, a watchdog gate, a communication gate 12, a communication cap 36j 12, a communication chip 36j 12, and a communication chip 12 interface 12; a 94 th pin of the processor U31 is connected with one end of a resistor R78, and the other end of the resistor R78 is connected to the ground; two ends of the resistor R78 and the crystal oscillator Y1 are respectively connected with a 12 th pin and a 13 th pin of the processor U31, one end of the crystal oscillator Y1 is connected with a capacitor C2 and a capacitor C46 in series, one end of the capacitor C46 is connected with the other end of the crystal oscillator Y1, and the connection part of the capacitor C2 and the capacitor C46 is connected to the ground; the 10 th pin, the 27 th pin, the 99 th pin, the 74 th pin and the 49 th pin of the processor U31 are connected with each other, and the 11 th pin, the 28 th pin, the 100 th pin, the 75 th pin and the 50 th pin of the processor U31 are connected with each other; two ends of a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11 and a capacitor C12 are respectively connected with a 11 th pin and a 10 th pin of the processor U31; the 10 th pin of the processor U31 is connected to ground, and the 11 th pin of the processor U31 is connected to the +3.3V terminal; the 19 th pin and the 20 th pin of the processor U31 are connected, and the 21 st pin and the 220 th pin of the processor U31 are connected; two ends of the capacitor C13, the capacitor C14, the capacitor C15 and the capacitor C16 are respectively connected with a 22 th pin and a 20 th pin of the processor U31; pin 20 of processor U31 is connected to ground and pin 22 of processor U31 is connected to the +3.3V terminal; the 8 th pin and the 10 th pin of the burning interface J1 are both connected to the ground, and the 1 st pin of the burning interface J1 is connected with the +3.3V end; the 3 rd pin, the 7 th pin and the 9 th pin of the burning interface J1 are respectively connected with the 14 th pin, the 72 th pin and the 76 th pin of the processor U31; the 2 nd pin of the watchdog chip U32 is respectively connected with the +3.3V end and one end of a capacitor C57, the other end of the capacitor C57 is respectively connected with the 3 rd pin of the watchdog chip U32 and one ends of a resistor R9 and a resistor R4, and the other ends of a resistor R9 and a resistor R4 are respectively connected with the 4 th pin of the watchdog chip U32 and the 14 th pin of the processor U31; the 7 th pin of the watchdog chip U32 is connected with one end of a resistor R80, and the other end of the resistor R80 is connected with the 14 th pin of the processor U31; a resistor R5 is connected between the 8 th pin and the 1 st pin of the watchdog chip U32, the 1 st pin of the watchdog chip U32 is connected with the 1 st pin of the jumper cap JP2, the 2 nd pin of the jumper cap JP2 is respectively connected with a +3.3V end and one ends of a resistor R6, a resistor R7 and a resistor R8, and the other end of the resistor R6 is connected with the 1 st pin of the watchdog chip U32; the other end of the resistor R8 is connected with one end of the LED18, and the other ends of the LED18 and the resistor R7 are both connected with the 6 th pin of the watchdog chip U32; the 1 st pin and the 8 th pin of the communication isolation chip U3 are respectively connected with a +3.3V end and a +5VA end, and the 4 th pin and the 5 th pin of the communication isolation chip U3 are both connected to the ground; the No. 2 pin and the No. 3 pin of the communication isolation chip U3 are respectively connected with the No. 69 pin and the No. 68 pin of the processor U31; the 11 th pin and the 12 th pin of the communication chip U4 are respectively connected with one ends of a resistor R40 and a resistor R41, and the other ends of the resistor R40 and the resistor R41 are respectively connected with the 6 th pin and the 7 th pin of the communication isolation chip U3; a capacitor C23 is connected between the 1 st pin and the 3 rd pin of the communication chip U4; a capacitor C158 is connected between the 6 th pin and the 15 th pin of the communication chip U4, and the 15 th pin of the communication chip U4 is connected to the ground; the 2 nd pin of the communication chip U4 is connected with one end of a capacitor C26, and the other end of the capacitor C26 is connected to the ground; the 16 th pin of the communication chip U4 is respectively connected with one end of a capacitor C27 and the +5VA end, and the other end of the capacitor C27 is connected to the ground; the 4 th pin and the 5 th pin of the communication chip U4 are connected into the capacitor C157; the 13 th pin and the 14 th pin of the communication chip U4 are respectively connected with one ends of a resistor R43 and a resistor R42, the other end of the resistor R43 is connected with one end of a TVS (transient voltage suppressor) TVS2, and the other end of the TVS2 is connected to the ground; the other end of the resistor R42 is connected with one end of a TVS tube TVS1, and the other end of the TVS tube TVS1 is connected to the ground; the 1 st pin of the communication interface J48 is connected with the junction of the resistor R42 and the TVS1, the 2 nd pin of the communication interface J48 is connected with the junction of the resistor R43 and the TVS2, and the 3 rd pin of the communication interface J48 is connected with the ground.

In some embodiments of the present invention, the voltage sampling circuit includes an operational amplifier chip U37A, U37B, U38A, U38B, U39A, U39B, U40A, U40B, U41A, U41B, U42A, U42B, U43A, U43B, U44A, U44B, U45A, U45B, U46A, U46B, a resistor R114, a resistor R115, a resistor R116, a resistor R117, a resistor R118, a resistor R119, a resistor R120, a resistor R121, a resistor R122, a resistor R123, a resistor R124, a resistor R125, a resistor R126, a resistor R127, a resistor R128, a resistor R129, a resistor R130, a resistor R131, a resistor R132, a resistor R133, a resistor R134, a resistor R135, a resistor R136, a resistor R138, a resistor R149, a resistor R160, a resistor R153, a resistor R148, a resistor R161, a resistor R144, a resistor R159, a resistor R144, a resistor R158, a resistor R144, a resistor R158, a resistor R151, a resistor R144, a resistor R159, a resistor R144, a resistor R152, a resistor R, A resistor R162, a resistor R163, a resistor R164, a resistor R165, a resistor R166, a resistor R167, a resistor R168, a resistor R169, a resistor R170, a resistor R171, a resistor R172, a resistor R173, a capacitor C113, a capacitor C114, a capacitor C115, a capacitor C116, a capacitor C117, a capacitor C118, a capacitor C119, a capacitor C120, a capacitor C121, a capacitor C122, a capacitor C123, a capacitor C124, a capacitor C125, a capacitor C126, a capacitor C127, a capacitor C128, a capacitor C129, a capacitor C130, a capacitor C131, a capacitor C132, a capacitor C133, a capacitor C134, a capacitor C135, a capacitor C136, a capacitor C137, a capacitor C138, a capacitor C139, a capacitor C140, a capacitor C141, a capacitor C142, a capacitor C143, a capacitor C144, a capacitor C145, a capacitor C146, a capacitor C147 and a capacitor C148; the 4 th pin of the operational amplifier chip U37A is respectively connected with one end of a capacitor C113 and one end of a capacitor C115, and the other ends of the capacitor C113 and the capacitor C115 are both connected to the ground; the 3 rd pin of the operational amplifier chip U37A is respectively connected with a resistor R119 and a capacitor C116, the other end of the capacitor C116 is connected to the ground, and the other ends of the resistor R119 and the capacitor C116 are respectively connected with the positive electrode and the negative electrode of the polar capacitor C1; a resistor R118 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U37A; a resistor R115 is connected between the 1 st pin of the operational amplifier chip U37A and the 6 th pin of the operational amplifier chip U37B; the 5 th pin of the operational amplifier chip U37B is connected with one end of a resistor R117, and the other end of the resistor R117 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U37B are directly connected to the resistor R116; the 7 th pin of the operational amplifier chip U37B is connected in series with a resistor R114 and a capacitor C114, the other end of the capacitor C114 is connected to the ground, and the connection position of the resistor R114 and the capacitor C114 is connected with the 23 rd pin of the processor U31; the 4 th pin of the operational amplifier chip U38A is respectively connected with one end of a capacitor C117 and one end of a capacitor C119, and the other ends of the capacitor C117 and the capacitor C119 are both connected to the ground; the 3 rd pin of the operational amplifier chip U38A is respectively connected with a resistor R125 and a capacitor C120, the other end of the capacitor C120 is connected to the ground, and the other ends of the resistor R125 and the capacitor C120 are respectively connected with the positive electrode and the negative electrode of a polar capacitor C37; a resistor R124 is connected between the No. 1 pin and the No. 2 pin of the operational amplifier chip U38A; a resistor R121 is connected between the 1 st pin of the operational amplifier chip U38A and the 6 th pin of the operational amplifier chip U38B; the 5 th pin of the operational amplifier chip U38B is connected with one end of a resistor R123, and the other end of the resistor R123 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U38B are directly connected to the resistor R122; the 7 th pin of the operational amplifier chip U38B is connected in series with a resistor R120 and a capacitor C118, the other end of the capacitor C118 is connected to the ground, and the connection position of the resistor R120 and the capacitor C118 is connected with the 24 th pin of the processor U31; the 4 th pin of the operational amplifier chip U39A is respectively connected with one end of a capacitor C121 and one end of a capacitor C123, and the other ends of the capacitor C121 and the capacitor C123 are both connected to the ground; the 3 rd pin of the operational amplifier chip U39A is respectively connected with the resistor R131 and the capacitor C124, the other end of the capacitor C124 is connected to the ground, and the other ends of the resistor R131 and the capacitor C124 are respectively connected with the positive electrode and the negative electrode of the polar capacitor C38; a resistor R130 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U39A; a resistor R127 is connected between the 1 st pin of the operational amplifier chip U39A and the 6 th pin of the operational amplifier chip U39B; the 5 th pin of the operational amplifier chip U39B is connected with one end of a resistor R129, and the other end of the resistor R129 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U39B are directly connected to the resistor R128; the 7 th pin of the operational amplifier chip U39B is connected in series with a resistor R126 and a capacitor C122, the other end of the capacitor C122 is connected to the ground, and the connection part of the resistor R126 and the capacitor C122 is connected with the 25 th pin of the processor U31; the 4 th pin of the operational amplifier chip U40A is respectively connected with one end of a capacitor C125 and one end of a capacitor C127, and the other ends of the capacitor C125 and the capacitor C127 are both connected to the ground; the 3 rd pin of the operational amplifier chip U40A is respectively connected with a resistor R137 and a capacitor C128, the other end of the capacitor C128 is connected to the ground, and the other ends of the resistor R137 and the capacitor C128 are respectively connected with the positive electrode and the negative electrode of the polar capacitor C39; a resistor R136 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U40A; a resistor R133 is connected between the 1 st pin of the operational amplifier chip U40A and the 6 th pin of the operational amplifier chip U40B; the 5 th pin of the operational amplifier chip U40B is connected with one end of a resistor R135, and the other end of the resistor R135 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U40B are directly connected to the resistor R134; the 7 th pin of the operational amplifier chip U40B is connected in series with a resistor R132 and a capacitor C126, the other end of the capacitor C126 is connected to the ground, and the connection position of the resistor R132 and the capacitor C126 is connected with the 26 th pin of the processor U31; the 4 th pin of the operational amplifier chip U41A is respectively connected with one end of a capacitor C129 and one end of a capacitor C131, and the other ends of the capacitor C129 and the capacitor C131 are both connected to the ground; the 3 rd pin of the operational amplifier chip U41A is connected with a resistor R143 and a capacitor C132 respectively, the other end of the capacitor C132 is connected to the ground, and the other ends of the resistor R143 and the capacitor C132 are connected with the positive electrode and the negative electrode of the polar capacitor C40 respectively; a resistor R142 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U41A; a resistor R139 is connected between the 1 st pin of the operational amplifier chip U41A and the 6 th pin of the operational amplifier chip U41B; the 5 th pin of the operational amplifier chip U41B is connected with one end of a resistor R141, and the other end of the resistor R141 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U41B are directly connected to the resistor R140; the 7 th pin of the operational amplifier chip U41B is connected in series with a resistor R138 and a capacitor C130, the other end of the capacitor C130 is connected to the ground, and the connection position of the resistor R138 and the capacitor C130 is connected with the 29 th pin of the processor U31; the 4 th pin of the operational amplifier chip U42A is respectively connected with one end of a capacitor C133 and one end of a capacitor C135, and the other ends of the capacitor C133 and the capacitor C135 are both connected to the ground; the 3 rd pin of the operational amplifier chip U42A is connected with a resistor R149 and a capacitor C136 respectively, the other end of the capacitor C136 is connected to the ground, and the other ends of the resistor R149 and the capacitor C136 are connected with the positive and negative electrodes of a polarity capacitor C41 respectively; a resistor R148 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U42A; a resistor R145 is connected between the 1 st pin of the operational amplifier chip U42A and the 6 th pin of the operational amplifier chip U42B; the 5 th pin of the operational amplifier chip U42B is connected with one end of a resistor R147, and the other end of the resistor R147 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U42B are directly connected to the resistor R146; the 7 th pin of the operational amplifier chip U42B is connected in series with a resistor R144 and a capacitor C134, the other end of the capacitor C134 is connected to the ground, and the connection position of the resistor R144 and the capacitor C134 is connected with the 30 th pin of the processor U31; the 4 th pin of the operational amplifier chip U43A is respectively connected with one end of a capacitor C137 and one end of a capacitor C139, and the other ends of the capacitor C137 and the capacitor C139 are both connected to the ground; the 3 rd pin of the operational amplifier chip U43A is respectively connected with the resistor R155 and the capacitor C140, the other end of the capacitor C140 is connected to the ground, and the other ends of the resistor R155 and the capacitor C140 are respectively connected with the positive electrode and the negative electrode of the polar capacitor C42; a resistor R154 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U43A; a resistor R151 is connected between the 1 st pin of the operational amplifier chip U43A and the 6 th pin of the operational amplifier chip U43B; the 5 th pin of the operational amplifier chip U43B is connected with one end of a resistor R153, and the other end of the resistor R153 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U43B are directly connected to the resistor R152; the 7 th pin of the operational amplifier chip U43B is connected in series with a resistor R150 and a capacitor C138, the other end of the capacitor C138 is connected to the ground, and the connection part of the resistor R150 and the capacitor C138 is connected with the 31 st pin of the processor U31; the 4 th pin of the operational amplifier chip U44A is respectively connected with one end of a capacitor C141 and one end of a capacitor C143, and the other ends of the capacitor C141 and the capacitor C143 are both connected to the ground; the 3 rd pin of the operational amplifier chip U44A is respectively connected with the resistor R161 and the capacitor C144, the other end of the capacitor C144 is connected to the ground, and the other ends of the resistor R161 and the capacitor C144 are respectively connected with the positive electrode and the negative electrode of the polar capacitor C43; a resistor R160 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U44A; a resistor R157 is connected between the 1 st pin of the operational amplifier chip U44A and the 6 th pin of the operational amplifier chip U44B; the 5 th pin of the operational amplifier chip U44B is connected with one end of a resistor R159, and the other end of the resistor R159 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U44B are directly connected to the resistor R158; the 7 th pin of the operational amplifier chip U44B is connected in series with a resistor R156 and a capacitor C142, the other end of the capacitor C142 is connected to the ground, and the connection part of the resistor R156 and the capacitor C142 is connected with the 32 nd pin of the processor U31; the 4 th pin of the operational amplifier chip U45A is respectively connected with one end of a capacitor C145 and one end of a capacitor C147, and the other ends of the capacitor C145 and the capacitor C147 are both connected to the ground; the 3 rd pin of the operational amplifier chip U45A is respectively connected with a resistor R167 and a capacitor C148, the other end of the capacitor C148 is connected to the ground, and the other ends of the resistor R167 and the capacitor C148 are respectively connected with the positive electrode and the negative electrode of the polarity capacitor C44; a resistor R166 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U45A; a resistor R163 is connected between the 1 st pin of the operational amplifier chip U45A and the 6 th pin of the operational amplifier chip U45B; the 5 th pin of the operational amplifier chip U45B is connected with one end of a resistor R165, and the other end of the resistor R165 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U45B are directly connected to the resistor R164; the 7 th pin of the operational amplifier chip U45B is connected in series with a resistor R162 and a capacitor C146, the other end of the capacitor C146 is connected to the ground, and the connection position of the resistor R162 and the capacitor C146 is connected with the 35 th pin of the processor U31; the 4 th pin of the operational amplifier chip U46A is connected to one end of a capacitor C149 and one end of a capacitor C151 respectively, and the other ends of the capacitor C149 and the capacitor C151 are connected to the ground; the 3 rd pin of the operational amplifier chip U46A is respectively connected with a resistor R173 and a capacitor C152, the other end of the capacitor C152 is connected to the ground, and the other ends of the resistor R173 and the capacitor C152 are respectively connected with the positive electrode and the negative electrode of the polarity capacitor C45; a resistor R172 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U46A; a resistor R169 is connected between the 1 st pin of the operational amplifier chip U46A and the 6 th pin of the operational amplifier chip U46B; the 5 th pin of the operational amplifier chip U46B is connected with one end of a resistor R170, and the other end of the resistor R170 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U46B are directly connected to the resistor R171; the 7 th pin of the operational amplifier chip U46B is connected in series with a resistor R168 and a capacitor C150, the other end of the capacitor C150 is connected to ground, and the connection point of the resistor R168 and the capacitor C150 is connected with the 36 th pin of the processor U31.

In some embodiments of the present invention, the current sampling circuit includes an operational amplifier chip U47A, an operational amplifier chip U47B, a current hall sensor U8, an interface J2, a resistor R16, a resistor R16, a resistor R174, a resistor R175, a resistor R176, a resistor R177, a resistor R178, a capacitor C21, a capacitor C24, a capacitor C25, a capacitor C21, a capacitor C153, a capacitor C154, a capacitor C155, and a capacitor C156; the 4 th pin of the operational amplifier chip U47A is respectively connected with one end of a capacitor C153 and one end of a capacitor C155, and the other ends of the capacitor C153 and the capacitor C155 are both connected to the ground; the 3 rd pin of the operational amplifier chip U47A is respectively connected with a resistor R179 and a capacitor C156, and the other end of the capacitor C156 is connected to the ground; a resistor R178 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U47A; a resistor R175 is connected between the 1 st pin of the operational amplifier chip U47A and the 6 th pin of the operational amplifier chip U47B; the 5 th pin of the operational amplifier chip U47B is connected with one end of a resistor R176, and the other end of the resistor R176 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U47B are directly connected to the resistor R177; the 7 th pin of the operational amplifier chip U46B is connected in series with a resistor R174 and a capacitor C154, the other end of the capacitor C154 is connected to the ground, and the connection position of the resistor R174 and the capacitor C154 is connected with the 15 th pin of the processor U31; the 1 st pin and the 2 nd pin of the interface J2 are respectively connected with a +26.5VDC terminal and a-26.5 VDC terminal; the 1 st pin and the 2 nd pin of the current Hall sensor U8 are connected with the 1 st pin of the interface J2, and the 3 rd pin and the 4 th pin of the current Hall sensor U8 are connected with the 22 nd pin of the interface J2; the 5 th pin of the current Hall sensor U8 is connected to the ground; the 6 th pin of the current Hall sensor U8 is connected with one end of a capacitor C24, and the other end of the capacitor C24 is connected to the ground; a 7 th pin of the current Hall sensor U8 is connected in series with a resistor R16 and a capacitor C25, the other end of the capacitor C25 is connected to the ground, and the connection part of the resistor R16 and the capacitor C25 is connected with the other end of the resistor R179; the 8 th pin of the current Hall sensor U8 is respectively connected with the +5V terminal and one end of a capacitor C21, and the other end of the capacitor C21 is connected with the ground.

In some embodiments of the present invention, the above-mentioned further includes a voltage conversion circuit, where the voltage conversion circuit includes a power module U5, a resistor R29, a resistor R24, a polar capacitor C92, a capacitor C93, a capacitor C94, a capacitor C95, a capacitor C96, a capacitor C97, and a chip inductor B13; a 1 st pin and a 2 nd pin of the power module U5 are respectively connected with two ends of a polar capacitor C92, a capacitor C93 and a capacitor C94, and a resistor R29 is connected between the polar capacitor C92 and the capacitor C93; pin 1 of the power module U5 is connected to the +26.5VDC terminal, and pin 2 is connected to ground; a 4 th pin of the power module U5 is respectively connected with a resistor R24 and a chip inductor B13 in series, the other end of the chip inductor B13 is respectively connected with one ends of a capacitor C95, a capacitor C96 and a capacitor C97, and the other ends of the capacitor C95, the capacitor C96 and the capacitor C97 are all connected with a 3 rd pin of the power module U5; the other end of the chip inductor B13 is connected to the +5V terminal, and the 3 rd pin of the power module U5 is connected to the ground.

In some embodiments of the present invention, the above further includes a conversion voltage stabilizing circuit, where the conversion voltage stabilizing circuit includes a linear voltage regulator U33, a capacitor C50, a capacitor C51, a capacitor C52, a capacitor C53, a capacitor C54, a capacitor C55, a capacitor C56, and a diode D9; the 1 st pin and the 2 nd pin of the linear voltage regulator U33 are respectively connected with two ends of a capacitor C50 and a capacitor C51, the 1 st pin of the linear voltage regulator U33 is connected to the ground, and the 2 nd pin is connected with a +5V end; the 2 nd pin and the 3 rd pin of the linear voltage regulator U33 are connected with the 4 th pin, a diode D9 is connected between the 2 nd pin and the 3 rd pin, and the output end of the diode D9 is connected with the 1 st pin of the linear voltage regulator U33; the 2 nd pin of the linear voltage regulator U33 is connected to the +3.3V terminal and one terminal of the capacitor C52, the capacitor C53, the capacitor C54, the capacitor C55 and the capacitor C56, respectively, and the other terminals of the capacitor C52, the capacitor C53, the capacitor C54, the capacitor C55 and the capacitor C56 are connected to ground.

In some embodiments of the present invention, the above further includes an isolation circuit, where the isolation circuit includes an isolation power supply module U12, a resistor R180, and a resistor R181; a 1 st pin of the isolation power supply module U12 is connected with one end of a resistor R180, and the other end of the resistor R180 is connected with a +5V end; a 7 th pin of the isolation power supply module U12 is connected with one end of a resistor R181, and the other end of the resistor R181 is connected with a +5V end; pin 2 and pin 5 of the isolated power module U12 are both connected to ground.

In some embodiments of the present invention, the power indication circuit further includes a resistor R83 and an LED16, the resistor R83 is connected in series with the LED16, the other end of the resistor R83 is connected to the +3.3V terminal, and the other end of the LED16 is connected to ground.

Compared with the prior art, the embodiment of the invention has at least the following advantages or beneficial effects: when the cover type FTU is connected with a main power supply, the super capacitor power supply management module of the FTU charges the super capacitor module, an DC25.5V-26.5V power supply of the power supply management module enters the reverse connection protection circuit through a charging interface of the super capacitor module and then charges the super capacitor module, and meanwhile, the single overvoltage-body overvoltage-preventing charging protection circuit is started to protect the super capacitor of each single body, so that the charging voltage is prevented from exceeding the rated voltage of the single-body super capacitor. When the super capacitor module charging voltage reaches the processor U31 boot voltage, the processor U31 will boot. And treater U31 samples the charge-discharge voltage electric current of super capacitor module through voltage electric current sampling circuit, and treater U31 communicates with the core unit that FTU's core unit is connected to the electric parameter of super capacitor module through RS485 communication circuit gathered, and FTU just can carry out the charge-discharge electric current, voltage and the number of charge-discharge of real time monitoring super capacitor module. The method and the device can ensure that the hood-type FTU can normally work when the main power supply is switched to a backup power supply after power failure, and improve the running reliability of the hood-type FTU. The module power supply charging interface (1 is a module power supply charging interface) is provided with a positive access interface and a negative access interface, the positive electrode of the module power supply charging interface is connected with the positive electrode of the power supply, and the negative electrode of the module power supply charging interface is connected with the negative electrode of the power supply. Due to the fact that the reverse connection preventing circuit is added, the super capacitor power management module cannot charge the super capacitor module after reverse connection, and therefore explosion of the super capacitor module due to reverse connection electricity is avoided.

Drawings

FIG. 1 is a schematic diagram of a reverse connection protection circuit according to an embodiment of the present invention; FIG. 2 is a schematic diagram of an overvoltage protection circuit according to an embodiment of the present invention; FIG. 3 is a schematic diagram of a current sampling circuit according to an embodiment of the present invention; FIG. 4 is a schematic diagram of a main circuit according to an embodiment of the present invention; FIG. 5 is a partial schematic diagram of a voltage sampling circuit according to an embodiment of the invention; FIG. 6 is a schematic diagram of another portion of a voltage sampling circuit according to an embodiment of the present invention; FIG. 7 is a schematic diagram of a voltage conversion circuit according to an embodiment of the present invention; FIG. 8 is a schematic diagram of a switching regulator circuit according to an embodiment of the present invention; FIG. 9 is a schematic diagram of an isolation circuit according to an embodiment of the present invention; FIG. 10 is a diagram of a power indication circuit according to an embodiment of the invention.

Detailed Description

Examples

Please refer to fig. 1-10, which include a capacitor main module composed of 10 capacitor units; the capacitor main body module is provided with an overvoltage protection circuit, a reverse connection protection circuit, a voltage sampling circuit, a current sampling circuit and a main circuit. Referring to fig. 1, in the embodiment, the reverse connection protection circuit includes a rectifier bridge D15, the 2 nd pin and the 3 rd pin of the rectifier bridge D15 are connected to the positive electrode and the negative electrode of the power input terminal, and the 1 st pin and the 4 th pin of the rectifier bridge D15 are connected to the overvoltage protection circuit. Rectifier bridge D15 is one and can effectually ensure in time that the input power joins conversely also can export the free positive pole of power to super capacitor, and the power negative pole is to the free positive and negative of super capacitor, and the explosion damage is caused owing to the transposition to effectual protection super capacitor module. Referring to fig. 2, in the present embodiment, the overvoltage protection circuit includes a voltage detection chip U2, a voltage detection chip U14, a MOS tube U14, a resistor R36r 14, a resistor R36r 14, a resistor R36r 14, a resistor R36r 14, a resistor R36r 14, a resistor R36r 14, a resistor R36r 14, a resistor R36r 14, a resistor R36r 14, a resistor R36r 14, a resistor R14, a resistor, The circuit comprises a resistor R77, a polar capacitor C1, a polar capacitor C37, a polar capacitor C8, a polar capacitor C39, a polar capacitor C40, a polar capacitor C41, a polar capacitor C42, a polar capacitor C43, a polar capacitor C44 and a polar capacitor C45; the input power supply enters the main circuit to charge super capacitor monomers C1, C37, C38, C39, C40, C41, C42, C43, C44 and C45 after passing through the reverse connection prevention circuit, and each super capacitor unit is provided with a capacitor overvoltage-preventing charging circuit to ensure that the charging voltage of each super capacitor does not exceed 2.7VDC of the constant voltage of the capacitor, for example, the over-voltage prevention circuit on the monomer capacitor C1 consists of a MOS tube U1, a voltage detection chip U2, a resistor R1, a resistor R2 and a resistor R3 chip resistor, when the voltage of the super capacitor cell exceeds 2.65VDC, the U2 voltage detection chip detects that the voltage of the capacitor cell reaches 2.65VDC and drives the MOS tube U1 to be conducted, the capacitor monomer is connected into the R1, R2 and R3 chip resistors to form a release loop, the capacitor monomer is ensured to be under the rated voltage of 2.7VDC, therefore, the partial circuit effectively protects the capacitor unit from explosion caused by over-rated voltage charging. The 2 nd pin of the voltage detection chip U2 is connected with the cathode of the polar capacitor C1, and the anode of the polar capacitor C1 is connected with the 3 rd pin of the voltage detection chip U2; a 2 nd pin of the voltage detection chip U2 is connected with an S pole of the MOS tube U1, a G pole of the MOS tube U1 is connected with a 1 st pin of the voltage detection chip U2, a D pole of the MOS tube U1 is respectively connected with one ends of a resistor R1, a resistor R2 and a resistor R3, and the other ends of the resistor R1, a resistor R2 and the resistor R3 are connected with a 3 rd pin of the voltage detection chip U2; the 3 rd pin of the voltage detection chip U2 is connected with the 2 nd pin of the voltage detection chip U14, the 2 nd pin of the voltage detection chip U14 is connected with the cathode of the polar capacitor C37, and the anode of the polar capacitor C37 is connected with the 3 rd pin of the voltage detection chip U14; a 2 nd pin of the voltage detection chip U14 is connected with an S pole of the MOS tube U13, a G pole of the MOS tube U13 is connected with a 1 st pin of the voltage detection chip U14, a D pole of the MOS tube U13 is respectively connected with one ends of a resistor R51, a resistor R52 and a resistor R53, and the other ends of the resistor R51, a resistor R52 and the resistor R53 are connected with a 3 rd pin of the voltage detection chip U14; the 3 rd pin of the voltage detection chip U14 is connected with the 2 nd pin of the voltage detection chip U16, the 2 nd pin of the voltage detection chip U16 is connected with the cathode of the polar capacitor C38, and the anode of the polar capacitor C38 is connected with the 3 rd pin of the voltage detection chip U16; a 2 nd pin of the voltage detection chip U16 is connected with an S pole of the MOS tube U15, a G pole of the MOS tube U15 is connected with a 1 st pin of the voltage detection chip U16, a D pole of the MOS tube U15 is respectively connected with one ends of a resistor R54, a resistor R55 and a resistor R56, and the other ends of the resistor R54, a resistor R55 and the resistor R56 are connected with a 3 rd pin of the voltage detection chip U16; the 3 rd pin of the voltage detection chip U16 is connected with the 2 nd pin of the voltage detection chip U18, the 2 nd pin of the voltage detection chip U18 is connected with the cathode of the polar capacitor C39, and the anode of the polar capacitor C39 is connected with the 3 rd pin of the voltage detection chip U18; a 2 nd pin of the voltage detection chip U18 is connected with an S pole of the MOS tube U17, a G pole of the MOS tube U17 is connected with a 1 st pin of the voltage detection chip U18, a D pole of the MOS tube U17 is respectively connected with one ends of a resistor R57, a resistor R58 and a resistor R59, and the other ends of the resistor R57, a resistor R58 and the resistor R59 are connected with a 3 rd pin of the voltage detection chip U18; the 3 rd pin of the voltage detection chip U18 is connected with the 2 nd pin of the voltage detection chip U20, the 2 nd pin of the voltage detection chip U20 is connected with the cathode of the polar capacitor C40, and the anode of the polar capacitor C40 is connected with the 3 rd pin of the voltage detection chip U20; a 2 nd pin of the voltage detection chip U20 is connected with an S pole of the MOS tube U19, a G pole of the MOS tube U19 is connected with a 1 st pin of the voltage detection chip U20, a D pole of the MOS tube U19 is respectively connected with one ends of a resistor R60, a resistor R61 and a resistor R62, and the other ends of the resistor R60, a resistor R61 and the resistor R62 are connected with a 3 rd pin of the voltage detection chip U20; the 3 rd pin of the voltage detection chip U20 is connected with the 2 nd pin of the voltage detection chip U22, the 2 nd pin of the voltage detection chip U22 is connected with the cathode of the polar capacitor C41, and the anode of the polar capacitor C41 is connected with the 3 rd pin of the voltage detection chip U22; a 2 nd pin of the voltage detection chip U22 is connected with an S pole of the MOS tube U21, a G pole of the MOS tube U21 is connected with a 1 st pin of the voltage detection chip U22, a D pole of the MOS tube U21 is respectively connected with one ends of a resistor R63, a resistor R64 and a resistor R65, and the other ends of the resistor R63, a resistor R64 and the resistor R65 are connected with a 3 rd pin of the voltage detection chip U22; the 3 rd pin of the voltage detection chip U22 is connected with the 2 nd pin of the voltage detection chip U24, the 2 nd pin of the voltage detection chip U24 is connected with the cathode of the polar capacitor C42, and the anode of the polar capacitor C42 is connected with the 3 rd pin of the voltage detection chip U24; a 2 nd pin of the voltage detection chip U24 is connected with an S pole of the MOS tube U23, a G pole of the MOS tube U23 is connected with a 1 st pin of the voltage detection chip U24, a D pole of the MOS tube U23 is respectively connected with one ends of a resistor R66, a resistor R67 and a resistor R68, and the other ends of the resistor R66, a resistor R67 and the resistor R68 are connected with a 3 rd pin of the voltage detection chip U24; the 3 rd pin of the voltage detection chip U24 is connected with the 2 nd pin of the voltage detection chip U26, the 2 nd pin of the voltage detection chip U26 is connected with the cathode of the polar capacitor C43, and the anode of the polar capacitor C43 is connected with the 3 rd pin of the voltage detection chip U26; a 2 nd pin of the voltage detection chip U26 is connected with an S pole of the MOS tube U25, a G pole of the MOS tube U25 is connected with a 1 st pin of the voltage detection chip U26, a D pole of the MOS tube U25 is respectively connected with one ends of a resistor R69, a resistor R70 and a resistor R71, and the other ends of the resistor R69, a resistor R70 and the resistor R71 are connected with a 3 rd pin of the voltage detection chip U26; the 3 rd pin of the voltage detection chip U26 is connected with the 2 nd pin of the voltage detection chip U28, the 2 nd pin of the voltage detection chip U28 is connected with the cathode of the polar capacitor C44, and the anode of the polar capacitor C44 is connected with the 3 rd pin of the voltage detection chip U28; a 2 nd pin of the voltage detection chip U28 is connected with an S pole of the MOS tube U27, a G pole of the MOS tube U27 is connected with a 1 st pin of the voltage detection chip U28, a D pole of the MOS tube U27 is respectively connected with one ends of a resistor R72, a resistor R73 and a resistor R74, and the other ends of the resistor R72, a resistor R73 and the resistor R74 are connected with a 3 rd pin of the voltage detection chip U28; the 3 rd pin of the voltage detection chip U28 is connected with the 2 nd pin of the voltage detection chip U30, the 2 nd pin of the voltage detection chip U30 is connected with the cathode of the polar capacitor C45, and the anode of the polar capacitor C45 is connected with the 3 rd pin of the voltage detection chip U30; a 2 nd pin of the voltage detection chip U30 is connected with an S pole of the MOS tube U29, a G pole of the MOS tube U29 is connected with a 1 st pin of the voltage detection chip U30, a D pole of the MOS tube U29 is respectively connected with one ends of a resistor R75, a resistor R76 and a resistor R77, and the other ends of the resistor R75, a resistor R76 and the resistor R77 are connected with a 3 rd pin of the voltage detection chip U30; the 1 st pin and the 4 th pin of the rectifier bridge are respectively connected with the 2 nd pin of the voltage detection chip U2 and the 3 rd pin of the voltage detection chip U30. Referring to fig. 4, in this embodiment, the main circuit includes a processor U31, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a crystal oscillator Y12, a resistor R12, a capacitor C157, a capacitor C158, an LED 12, a TVS 12, a jumper, a TVS 12, a communication gate for a programmed dog burner 36j, a communication chip 12, a communication chip 36j, and a communication cap 12. A 94 th pin of the processor U31 is connected with one end of a resistor R78, and the other end of the resistor R78 is connected to the ground; two ends of the resistor R78 and the crystal oscillator Y1 are respectively connected with a 12 th pin and a 13 th pin of the processor U31, one end of the crystal oscillator Y1 is connected with a capacitor C2 and a capacitor C46 in series, one end of the capacitor C46 is connected with the other end of the crystal oscillator Y1, and the connection part of the capacitor C2 and the capacitor C46 is connected to the ground; the 10 th pin, the 27 th pin, the 99 th pin, the 74 th pin and the 49 th pin of the processor U31 are connected with each other, and the 11 th pin, the 28 th pin, the 100 th pin, the 75 th pin and the 50 th pin of the processor U31 are connected with each other; two ends of a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11 and a capacitor C12 are respectively connected with a 11 th pin and a 10 th pin of the processor U31; the 10 th pin of the processor U31 is connected to ground, and the 11 th pin of the processor U31 is connected to the +3.3V terminal; the 19 th pin and the 20 th pin of the processor U31 are connected, and the 21 st pin and the 220 th pin of the processor U31 are connected; two ends of the capacitor C13, the capacitor C14, the capacitor C15 and the capacitor C16 are respectively connected with a 22 th pin and a 20 th pin of the processor U31; pin 20 of processor U31 is connected to ground and pin 22 of processor U31 is connected to the +3.3V terminal; the 8 th pin and the 10 th pin of the burning interface J1 are both connected to the ground, and the 1 st pin of the burning interface J1 is connected with the +3.3V end; the 3 rd pin, the 7 th pin and the 9 th pin of the burning interface J1 are respectively connected with the 14 th pin, the 72 th pin and the 76 th pin of the processor U31; the 2 nd pin of the watchdog chip U32 is respectively connected with the +3.3V end and one end of a capacitor C57, the other end of the capacitor C57 is respectively connected with the 3 rd pin of the watchdog chip U32 and one ends of a resistor R9 and a resistor R4, and the other ends of a resistor R9 and a resistor R4 are respectively connected with the 4 th pin of the watchdog chip U32 and the 14 th pin of the processor U31; the 7 th pin of the watchdog chip U32 is connected with one end of a resistor R80, and the other end of the resistor R80 is connected with the 14 th pin of the processor U31; a resistor R5 is connected between the 8 th pin and the 1 st pin of the watchdog chip U32, the 1 st pin of the watchdog chip U32 is connected with the 1 st pin of the jumper cap JP2, the 2 nd pin of the jumper cap JP2 is respectively connected with a +3.3V end and one ends of a resistor R6, a resistor R7 and a resistor R8, and the other end of the resistor R6 is connected with the 1 st pin of the watchdog chip U32; the other end of the resistor R8 is connected with one end of the LED18, and the other ends of the LED18 and the resistor R7 are both connected with the 6 th pin of the watchdog chip U32; the 1 st pin and the 8 th pin of the communication isolation chip U3 are respectively connected with a +3.3V end and a +5VA end, and the 4 th pin and the 5 th pin of the communication isolation chip U3 are both connected to the ground; the No. 2 pin and the No. 3 pin of the communication isolation chip U3 are respectively connected with the No. 69 pin and the No. 68 pin of the processor U31; the 11 th pin and the 12 th pin of the communication chip U4 are respectively connected with one ends of a resistor R40 and a resistor R41, and the other ends of the resistor R40 and the resistor R41 are respectively connected with the 6 th pin and the 7 th pin of the communication isolation chip U3; a capacitor C23 is connected between the 1 st pin and the 3 rd pin of the communication chip U4; a capacitor C158 is connected between the 6 th pin and the 15 th pin of the communication chip U4, and the 15 th pin of the communication chip U4 is connected to the ground; the 2 nd pin of the communication chip U4 is connected with one end of a capacitor C26, and the other end of the capacitor C26 is connected to the ground; the 16 th pin of the communication chip U4 is respectively connected with one end of a capacitor C27 and the +5VA end, and the other end of the capacitor C27 is connected to the ground; the 4 th pin and the 5 th pin of the communication chip U4 are connected into the capacitor C157; the 13 th pin and the 14 th pin of the communication chip U4 are respectively connected with one ends of a resistor R43 and a resistor R42, the other end of the resistor R43 is connected with one end of a TVS (transient voltage suppressor) TVS2, and the other end of the TVS2 is connected to the ground; the other end of the resistor R42 is connected with one end of a TVS tube TVS1, and the other end of the TVS tube TVS1 is connected to the ground; the 1 st pin of the communication interface J48 is connected with the junction of the resistor R42 and the TVS1, the 2 nd pin of the communication interface J48 is connected with the junction of the resistor R43 and the TVS2, and the 3 rd pin of the communication interface J48 is connected with the ground. Referring to fig. 5-6, in the present embodiment, the voltage sampling circuit includes an operational amplifier chip U37A, U37B, U38A, U38B, U39A, U39B, U40A, U40B, U41A, U41B, U42A, U42B, U43A, U43B, U44A, U44B, U45A, U45B, U46A, U46B, a resistor R114, a resistor R115, a resistor R116, a resistor R117, a resistor R118, a resistor R119, a resistor R120, a resistor R121, a resistor R122, a resistor R123, a resistor R124, a resistor R125, a resistor R126, a resistor R127, a resistor R128, a resistor R129, a resistor R130, a resistor R131, a resistor R132, a resistor R137, a resistor R134, a resistor R135, a resistor R136, a resistor R152, a resistor R149, a resistor R160, a resistor R153, a resistor R127, a resistor R128, a resistor R144, a resistor R151, a resistor R144, a resistor R152, a resistor R151, a resistor R144, a resistor R152, a resistor R144, a resistor R152, a resistor R, A resistor R161, a resistor R162, a resistor R163, a resistor R164, a resistor R165, a resistor R166, a resistor R167, a resistor R168, a resistor R169, a resistor R170, a resistor R171, a resistor R172, a resistor R173, a capacitor C113, a capacitor C114, a capacitor C115, a capacitor C116, a capacitor C117, a capacitor C118, a capacitor C119, a capacitor C120, a capacitor C121, a capacitor C122, a capacitor C123, a capacitor C124, a capacitor C125, a capacitor C126, a capacitor C127, a capacitor C128, a capacitor C129, a capacitor C130, a capacitor C131, a capacitor C132, a capacitor C133, a capacitor C134, a capacitor C135, a capacitor C136, a capacitor C137, a capacitor C138, a capacitor C139, a capacitor C140, a capacitor C141, a capacitor C142, a capacitor C143, a capacitor C144, a capacitor C145, a capacitor C146, a capacitor C147, and a capacitor C148; the 4 th pin of the operational amplifier chip U37A is respectively connected with one end of a capacitor C113 and one end of a capacitor C115, and the other ends of the capacitor C113 and the capacitor C115 are both connected to the ground; the 3 rd pin of the operational amplifier chip U37A is respectively connected with a resistor R119 and a capacitor C116, the other end of the capacitor C116 is connected to the ground, and the other ends of the resistor R119 and the capacitor C116 are respectively connected with the positive electrode and the negative electrode of the polar capacitor C1; a resistor R118 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U37A; a resistor R115 is connected between the 1 st pin of the operational amplifier chip U37A and the 6 th pin of the operational amplifier chip U37B; the 5 th pin of the operational amplifier chip U37B is connected with one end of a resistor R117, and the other end of the resistor R117 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U37B are directly connected to the resistor R116; the 7 th pin of the operational amplifier chip U37B is connected in series with a resistor R114 and a capacitor C114, the other end of the capacitor C114 is connected to the ground, and the connection position of the resistor R114 and the capacitor C114 is connected with the 23 rd pin of the processor U31; the 4 th pin of the operational amplifier chip U38A is respectively connected with one end of a capacitor C117 and one end of a capacitor C119, and the other ends of the capacitor C117 and the capacitor C119 are both connected to the ground; the 3 rd pin of the operational amplifier chip U38A is respectively connected with a resistor R125 and a capacitor C120, the other end of the capacitor C120 is connected to the ground, and the other ends of the resistor R125 and the capacitor C120 are respectively connected with the positive electrode and the negative electrode of a polar capacitor C37; a resistor R124 is connected between the No. 1 pin and the No. 2 pin of the operational amplifier chip U38A; a resistor R121 is connected between the 1 st pin of the operational amplifier chip U38A and the 6 th pin of the operational amplifier chip U38B; the 5 th pin of the operational amplifier chip U38B is connected with one end of a resistor R123, and the other end of the resistor R123 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U38B are directly connected to the resistor R122; the 7 th pin of the operational amplifier chip U38B is connected in series with a resistor R120 and a capacitor C118, the other end of the capacitor C118 is connected to the ground, and the connection position of the resistor R120 and the capacitor C118 is connected with the 24 th pin of the processor U31; the 4 th pin of the operational amplifier chip U39A is respectively connected with one end of a capacitor C121 and one end of a capacitor C123, and the other ends of the capacitor C121 and the capacitor C123 are both connected to the ground; the 3 rd pin of the operational amplifier chip U39A is respectively connected with the resistor R131 and the capacitor C124, the other end of the capacitor C124 is connected to the ground, and the other ends of the resistor R131 and the capacitor C124 are respectively connected with the positive electrode and the negative electrode of the polar capacitor C38; a resistor R130 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U39A; a resistor R127 is connected between the 1 st pin of the operational amplifier chip U39A and the 6 th pin of the operational amplifier chip U39B; the 5 th pin of the operational amplifier chip U39B is connected with one end of a resistor R129, and the other end of the resistor R129 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U39B are directly connected to the resistor R128; the 7 th pin of the operational amplifier chip U39B is connected in series with a resistor R126 and a capacitor C122, the other end of the capacitor C122 is connected to the ground, and the connection part of the resistor R126 and the capacitor C122 is connected with the 25 th pin of the processor U31; the 4 th pin of the operational amplifier chip U40A is respectively connected with one end of a capacitor C125 and one end of a capacitor C127, and the other ends of the capacitor C125 and the capacitor C127 are both connected to the ground; the 3 rd pin of the operational amplifier chip U40A is respectively connected with a resistor R137 and a capacitor C128, the other end of the capacitor C128 is connected to the ground, and the other ends of the resistor R137 and the capacitor C128 are respectively connected with the positive electrode and the negative electrode of the polar capacitor C39; a resistor R136 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U40A; a resistor R133 is connected between the 1 st pin of the operational amplifier chip U40A and the 6 th pin of the operational amplifier chip U40B; the 5 th pin of the operational amplifier chip U40B is connected with one end of a resistor R135, and the other end of the resistor R135 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U40B are directly connected to the resistor R134; the 7 th pin of the operational amplifier chip U40B is connected in series with a resistor R132 and a capacitor C126, the other end of the capacitor C126 is connected to the ground, and the connection position of the resistor R132 and the capacitor C126 is connected with the 26 th pin of the processor U31; the 4 th pin of the operational amplifier chip U41A is respectively connected with one end of a capacitor C129 and one end of a capacitor C131, and the other ends of the capacitor C129 and the capacitor C131 are both connected to the ground; the 3 rd pin of the operational amplifier chip U41A is connected with a resistor R143 and a capacitor C132 respectively, the other end of the capacitor C132 is connected to the ground, and the other ends of the resistor R143 and the capacitor C132 are connected with the positive electrode and the negative electrode of the polar capacitor C40 respectively; a resistor R142 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U41A; a resistor R139 is connected between the 1 st pin of the operational amplifier chip U41A and the 6 th pin of the operational amplifier chip U41B; the 5 th pin of the operational amplifier chip U41B is connected with one end of a resistor R141, and the other end of the resistor R141 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U41B are directly connected to the resistor R140; the 7 th pin of the operational amplifier chip U41B is connected in series with a resistor R138 and a capacitor C130, the other end of the capacitor C130 is connected to the ground, and the connection position of the resistor R138 and the capacitor C130 is connected with the 29 th pin of the processor U31; the 4 th pin of the operational amplifier chip U42A is respectively connected with one end of a capacitor C133 and one end of a capacitor C135, and the other ends of the capacitor C133 and the capacitor C135 are both connected to the ground; the 3 rd pin of the operational amplifier chip U42A is connected with a resistor R149 and a capacitor C136 respectively, the other end of the capacitor C136 is connected to the ground, and the other ends of the resistor R149 and the capacitor C136 are connected with the positive and negative electrodes of a polarity capacitor C41 respectively; a resistor R148 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U42A; a resistor R145 is connected between the 1 st pin of the operational amplifier chip U42A and the 6 th pin of the operational amplifier chip U42B; the 5 th pin of the operational amplifier chip U42B is connected with one end of a resistor R147, and the other end of the resistor R147 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U42B are directly connected to the resistor R146; the 7 th pin of the operational amplifier chip U42B is connected in series with a resistor R144 and a capacitor C134, the other end of the capacitor C134 is connected to the ground, and the connection position of the resistor R144 and the capacitor C134 is connected with the 30 th pin of the processor U31; the 4 th pin of the operational amplifier chip U43A is respectively connected with one end of a capacitor C137 and one end of a capacitor C139, and the other ends of the capacitor C137 and the capacitor C139 are both connected to the ground; the 3 rd pin of the operational amplifier chip U43A is respectively connected with the resistor R155 and the capacitor C140, the other end of the capacitor C140 is connected to the ground, and the other ends of the resistor R155 and the capacitor C140 are respectively connected with the positive electrode and the negative electrode of the polar capacitor C42; a resistor R154 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U43A; a resistor R151 is connected between the 1 st pin of the operational amplifier chip U43A and the 6 th pin of the operational amplifier chip U43B; the 5 th pin of the operational amplifier chip U43B is connected with one end of a resistor R153, and the other end of the resistor R153 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U43B are directly connected to the resistor R152; the 7 th pin of the operational amplifier chip U43B is connected in series with a resistor R150 and a capacitor C138, the other end of the capacitor C138 is connected to the ground, and the connection part of the resistor R150 and the capacitor C138 is connected with the 31 st pin of the processor U31; the 4 th pin of the operational amplifier chip U44A is respectively connected with one end of a capacitor C141 and one end of a capacitor C143, and the other ends of the capacitor C141 and the capacitor C143 are both connected to the ground; the 3 rd pin of the operational amplifier chip U44A is respectively connected with the resistor R161 and the capacitor C144, the other end of the capacitor C144 is connected to the ground, and the other ends of the resistor R161 and the capacitor C144 are respectively connected with the positive electrode and the negative electrode of the polar capacitor C43; a resistor R160 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U44A; a resistor R157 is connected between the 1 st pin of the operational amplifier chip U44A and the 6 th pin of the operational amplifier chip U44B; the 5 th pin of the operational amplifier chip U44B is connected with one end of a resistor R159, and the other end of the resistor R159 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U44B are directly connected to the resistor R158; the 7 th pin of the operational amplifier chip U44B is connected in series with a resistor R156 and a capacitor C142, the other end of the capacitor C142 is connected to the ground, and the connection part of the resistor R156 and the capacitor C142 is connected with the 32 nd pin of the processor U31; the 4 th pin of the operational amplifier chip U45A is respectively connected with one end of a capacitor C145 and one end of a capacitor C147, and the other ends of the capacitor C145 and the capacitor C147 are both connected to the ground; the 3 rd pin of the operational amplifier chip U45A is respectively connected with a resistor R167 and a capacitor C148, the other end of the capacitor C148 is connected to the ground, and the other ends of the resistor R167 and the capacitor C148 are respectively connected with the positive electrode and the negative electrode of the polarity capacitor C44; a resistor R166 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U45A; a resistor R163 is connected between the 1 st pin of the operational amplifier chip U45A and the 6 th pin of the operational amplifier chip U45B; the 5 th pin of the operational amplifier chip U45B is connected with one end of a resistor R165, and the other end of the resistor R165 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U45B are directly connected to the resistor R164; the 7 th pin of the operational amplifier chip U45B is connected in series with a resistor R162 and a capacitor C146, the other end of the capacitor C146 is connected to the ground, and the connection position of the resistor R162 and the capacitor C146 is connected with the 35 th pin of the processor U31; the 4 th pin of the operational amplifier chip U46A is connected to one end of a capacitor C149 and one end of a capacitor C151 respectively, and the other ends of the capacitor C149 and the capacitor C151 are connected to the ground; the 3 rd pin of the operational amplifier chip U46A is respectively connected with a resistor R173 and a capacitor C152, the other end of the capacitor C152 is connected to the ground, and the other ends of the resistor R173 and the capacitor C152 are respectively connected with the positive electrode and the negative electrode of the polarity capacitor C45; a resistor R172 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U46A; a resistor R169 is connected between the 1 st pin of the operational amplifier chip U46A and the 6 th pin of the operational amplifier chip U46B; the 5 th pin of the operational amplifier chip U46B is connected with one end of a resistor R170, and the other end of the resistor R170 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U46B are directly connected to the resistor R171; the 7 th pin of the operational amplifier chip U46B is connected in series with a resistor R168 and a capacitor C150, the other end of the capacitor C150 is connected to ground, and the connection point of the resistor R168 and the capacitor C150 is connected with the 36 th pin of the processor U31. Referring to fig. 3, in the present embodiment, the current sampling circuit includes an operational amplifier chip U47A, an operational amplifier chip U47B, a current hall sensor U8, an interface J2, a resistor R16, a resistor R16, a resistor R174, a resistor R175, a resistor R176, a resistor R177, a resistor R178, a capacitor C21, a capacitor C24, a capacitor C25, a capacitor C21, a capacitor C153, a capacitor C154, a capacitor C155, and a capacitor C156; when the cover type FTU is connected with a main power supply, the super capacitor power supply management module of the FTU charges the super capacitor module, an DC25.5V-26.5V power supply of the power supply management module is connected with the super capacitor module through J2, enters a current Hall sensor U8 to sample the current of a main power supply loop, and after the current quantity collected by the U8 is converted into a small voltage signal, the small voltage signal is processed by the U47A and the U47B operational amplifier and then is sent to an AD sampling module of a U31 main MCU to collect the current quantity. The partial circuit can monitor the charging and discharging current and the charging and discharging times of the super capacitor module in real time so as to ensure the stability of the super capacitor module and provide real data for module maintenance. The 4 th pin of the operational amplifier chip U47A is respectively connected with one end of a capacitor C153 and one end of a capacitor C155, and the other ends of the capacitor C153 and the capacitor C155 are both connected to the ground; the 3 rd pin of the operational amplifier chip U47A is respectively connected with a resistor R179 and a capacitor C156, and the other end of the capacitor C156 is connected to the ground; a resistor R178 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U47A; a resistor R175 is connected between the 1 st pin of the operational amplifier chip U47A and the 6 th pin of the operational amplifier chip U47B; the 5 th pin of the operational amplifier chip U47B is connected with one end of a resistor R176, and the other end of the resistor R176 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U47B are directly connected to the resistor R177; the 7 th pin of the operational amplifier chip U46B is connected in series with a resistor R174 and a capacitor C154, the other end of the capacitor C154 is connected to the ground, and the connection position of the resistor R174 and the capacitor C154 is connected with the 15 th pin of the processor U31; the 1 st pin and the 2 nd pin of the interface J2 are respectively connected with a +26.5VDC terminal and a-26.5 VDC terminal; the 1 st pin and the 2 nd pin of the current Hall sensor U8 are connected with the 1 st pin of the interface J2, and the 3 rd pin and the 4 th pin of the current Hall sensor U8 are connected with the 22 nd pin of the interface J2; the 5 th pin of the current Hall sensor U8 is connected to the ground; the 6 th pin of the current Hall sensor U8 is connected with one end of a capacitor C24, and the other end of the capacitor C24 is connected to the ground; a 7 th pin of the current Hall sensor U8 is connected in series with a resistor R16 and a capacitor C25, the other end of the capacitor C25 is connected to the ground, and the connection part of the resistor R16 and the capacitor C25 is connected with the other end of the resistor R179; the 8 th pin of the current Hall sensor U8 is respectively connected with the +5V terminal and one end of a capacitor C21, and the other end of the capacitor C21 is connected with the ground. Referring to fig. 7, in the present embodiment, the voltage conversion circuit further includes a power module U5, a resistor R29, a resistor R24, a polar capacitor C92, a capacitor C93, a capacitor C94, a capacitor C95, a capacitor C96, a capacitor C97, and a chip inductor B13; a 1 st pin and a 2 nd pin of the power module U5 are respectively connected with two ends of a polar capacitor C92, a capacitor C93 and a capacitor C94, and a resistor R29 is connected between the polar capacitor C92 and the capacitor C93; pin 1 of the power module U5 is connected to the +26.5VDC terminal, and pin 2 is connected to ground; a 4 th pin of the power module U5 is respectively connected with a resistor R24 and a chip inductor B13 in series, the other end of the chip inductor B13 is respectively connected with one ends of a capacitor C95, a capacitor C96 and a capacitor C97, and the other ends of the capacitor C95, the capacitor C96 and the capacitor C97 are all connected with a 3 rd pin of the power module U5; the other end of the chip inductor B13 is connected to the +5V terminal, and the 3 rd pin of the power module U5 is connected to the ground. Referring to fig. 8, in the present embodiment, the above-mentioned apparatus further includes a conversion voltage stabilizing circuit, where the conversion voltage stabilizing circuit includes a linear voltage regulator U33, a capacitor C50, a capacitor C51, a capacitor C52, a capacitor C53, a capacitor C54, a capacitor C55, a capacitor C56, and a diode D9; the 1 st pin and the 2 nd pin of the linear voltage regulator U33 are respectively connected with two ends of a capacitor C50 and a capacitor C51, the 1 st pin of the linear voltage regulator U33 is connected to the ground, and the 2 nd pin is connected with a +5V end; the 2 nd pin and the 3 rd pin of the linear voltage regulator U33 are connected with the 4 th pin, a diode D9 is connected between the 2 nd pin and the 3 rd pin, and the output end of the diode D9 is connected with the 1 st pin of the linear voltage regulator U33; the 2 nd pin of the linear voltage regulator U33 is connected to the +3.3V terminal and one terminal of the capacitor C52, the capacitor C53, the capacitor C54, the capacitor C55 and the capacitor C56, respectively, and the other terminals of the capacitor C52, the capacitor C53, the capacitor C54, the capacitor C55 and the capacitor C56 are connected to ground.

Referring to fig. 9, in the present embodiment, the above-mentioned circuit further includes an isolation circuit, where the isolation circuit includes an isolation power module U12, a resistor R180, and a resistor R181; a 1 st pin of the isolation power supply module U12 is connected with one end of a resistor R180, and the other end of the resistor R180 is connected with a +5V end; a 7 th pin of the isolation power supply module U12 is connected with one end of a resistor R181, and the other end of the resistor R181 is connected with a +5V end; pin 2 and pin 5 of the isolated power module U12 are both connected to ground.

Referring to fig. 10, in the present embodiment, the power indication circuit further includes a resistor R83 and an LED16, the resistor R83 is connected in series with the LED16, the other end of the resistor R83 is connected to the +3.3V terminal, and the other end of the LED16 is connected to ground.

Claims

1. The cover type FTU backup power supply super capacitor module is characterized by comprising a capacitor main body module consisting of a plurality of capacitor monomers; the capacitor main body module is provided with an overvoltage protection circuit, a reverse connection protection circuit, a voltage sampling circuit, a current sampling circuit and a main circuit.

2. The covered FTU backup power supply super capacitor module as claimed in claim 1, wherein said reverse connection protection circuit comprises a rectifier bridge D15, the 2 nd pin and the 3 rd pin of said rectifier bridge D15 are connected to the positive pole and the negative pole of the power supply input terminal, and the 1 st pin and the 4 th pin of the rectifier bridge D15 are connected to the overvoltage protection circuit.

3. The covered FTU backup power supply super capacitor module according to claim 2, wherein the overvoltage protection circuit comprises a voltage detection chip U2, a voltage detection chip U14, a voltage detection chip U16, a voltage detection chip U18, a voltage detection chip U20, a voltage detection chip U22, a voltage detection chip U24, a voltage detection chip U26, a voltage detection chip U28, a voltage detection chip U30, a MOS tube U1, a MOS tube U13, a resistor R36R 13, a resistor R36R 13, a resistor R36R 13, a resistor R36R 13, a resistor R36R 13, a resistor R36R 13, a resistor R36R 72, a resistor R36R 13, a resistor R36R 13, a resistor R36R 72, a resistor R36R 72, a resistor R36R 13, a resistor R72, a resistor R36R 13, a resistor R36R 72, a resistor R36R 13, a resistor R72, a resistor R36R 72, a resistor R13, a resistor R72, a resistor R36R 72, a resistor R13, a resistor R36R 13, a resistor R36R 13, a resistor R72, a resistor R36R 72, a resistor R36R 72, a resistor R36R, The circuit comprises a resistor R72, a resistor R73, a resistor R74, a resistor R75, a resistor R76, a resistor R77, a polar capacitor C1, a polar capacitor C37, a polar capacitor C8, a polar capacitor C39, a polar capacitor C40, a polar capacitor C41, a polar capacitor C42, a polar capacitor C43, a polar capacitor C44 and a polar capacitor C45;

the 2 nd pin of the voltage detection chip U2 is connected with the cathode of a polar capacitor C1, and the anode of the polar capacitor C1 is connected with the 3 rd pin of the voltage detection chip U2; a 2 nd pin of the voltage detection chip U2 is connected with an S pole of the MOS tube U1, a G pole of the MOS tube U1 is connected with a 1 st pin of the voltage detection chip U2, a D pole of the MOS tube U1 is respectively connected with one ends of a resistor R1, a resistor R2 and a resistor R3, and the other ends of the resistor R1, a resistor R2 and the resistor R3 are connected with a 3 rd pin of the voltage detection chip U2;

the 3 rd pin of the voltage detection chip U2 is connected with the 2 nd pin of the voltage detection chip U14, the 2 nd pin of the voltage detection chip U14 is connected with the cathode of a polar capacitor C37, and the anode of the polar capacitor C37 is connected with the 3 rd pin of the voltage detection chip U14; a 2 nd pin of the voltage detection chip U14 is connected with an S pole of the MOS tube U13, a G pole of the MOS tube U13 is connected with a 1 st pin of the voltage detection chip U14, a D pole of the MOS tube U13 is respectively connected with one ends of a resistor R51, a resistor R52 and a resistor R53, and the other ends of the resistor R51, a resistor R52 and the resistor R53 are connected with a 3 rd pin of the voltage detection chip U14;

the 3 rd pin of the voltage detection chip U14 is connected with the 2 nd pin of the voltage detection chip U16, the 2 nd pin of the voltage detection chip U16 is connected with the cathode of a polar capacitor C38, and the anode of the polar capacitor C38 is connected with the 3 rd pin of the voltage detection chip U16; a 2 nd pin of the voltage detection chip U16 is connected with an S pole of the MOS tube U15, a G pole of the MOS tube U15 is connected with a 1 st pin of the voltage detection chip U16, a D pole of the MOS tube U15 is respectively connected with one ends of a resistor R54, a resistor R55 and a resistor R56, and the other ends of the resistor R54, a resistor R55 and the resistor R56 are connected with a 3 rd pin of the voltage detection chip U16;

the 3 rd pin of the voltage detection chip U16 is connected with the 2 nd pin of the voltage detection chip U18, the 2 nd pin of the voltage detection chip U18 is connected with the cathode of a polar capacitor C39, and the anode of the polar capacitor C39 is connected with the 3 rd pin of the voltage detection chip U18; a 2 nd pin of the voltage detection chip U18 is connected with an S pole of the MOS tube U17, a G pole of the MOS tube U17 is connected with a 1 st pin of the voltage detection chip U18, a D pole of the MOS tube U17 is respectively connected with one ends of a resistor R57, a resistor R58 and a resistor R59, and the other ends of the resistor R57, a resistor R58 and the resistor R59 are connected with a 3 rd pin of the voltage detection chip U18;

the 3 rd pin of the voltage detection chip U18 is connected with the 2 nd pin of the voltage detection chip U20, the 2 nd pin of the voltage detection chip U20 is connected with the cathode of a polar capacitor C40, and the anode of the polar capacitor C40 is connected with the 3 rd pin of the voltage detection chip U20; a 2 nd pin of the voltage detection chip U20 is connected with an S pole of the MOS tube U19, a G pole of the MOS tube U19 is connected with a 1 st pin of the voltage detection chip U20, a D pole of the MOS tube U19 is respectively connected with one ends of a resistor R60, a resistor R61 and a resistor R62, and the other ends of the resistor R60, a resistor R61 and the resistor R62 are connected with a 3 rd pin of the voltage detection chip U20;

the 3 rd pin of the voltage detection chip U20 is connected with the 2 nd pin of the voltage detection chip U22, the 2 nd pin of the voltage detection chip U22 is connected with the cathode of a polar capacitor C41, and the anode of the polar capacitor C41 is connected with the 3 rd pin of the voltage detection chip U22; a 2 nd pin of the voltage detection chip U22 is connected with an S pole of the MOS tube U21, a G pole of the MOS tube U21 is connected with a 1 st pin of the voltage detection chip U22, a D pole of the MOS tube U21 is respectively connected with one ends of a resistor R63, a resistor R64 and a resistor R65, and the other ends of the resistor R63, a resistor R64 and the resistor R65 are connected with a 3 rd pin of the voltage detection chip U22;

the 3 rd pin of the voltage detection chip U22 is connected with the 2 nd pin of the voltage detection chip U24, the 2 nd pin of the voltage detection chip U24 is connected with the cathode of a polar capacitor C42, and the anode of the polar capacitor C42 is connected with the 3 rd pin of the voltage detection chip U24; a 2 nd pin of the voltage detection chip U24 is connected with an S pole of the MOS tube U23, a G pole of the MOS tube U23 is connected with a 1 st pin of the voltage detection chip U24, a D pole of the MOS tube U23 is respectively connected with one ends of a resistor R66, a resistor R67 and a resistor R68, and the other ends of the resistor R66, a resistor R67 and the resistor R68 are connected with a 3 rd pin of the voltage detection chip U24;

the 3 rd pin of the voltage detection chip U24 is connected with the 2 nd pin of the voltage detection chip U26, the 2 nd pin of the voltage detection chip U26 is connected with the cathode of a polar capacitor C43, and the anode of the polar capacitor C43 is connected with the 3 rd pin of the voltage detection chip U26; a 2 nd pin of the voltage detection chip U26 is connected with an S pole of the MOS tube U25, a G pole of the MOS tube U25 is connected with a 1 st pin of the voltage detection chip U26, a D pole of the MOS tube U25 is respectively connected with one ends of a resistor R69, a resistor R70 and a resistor R71, and the other ends of the resistor R69, a resistor R70 and the resistor R71 are connected with a 3 rd pin of the voltage detection chip U26;

the 3 rd pin of the voltage detection chip U26 is connected with the 2 nd pin of the voltage detection chip U28, the 2 nd pin of the voltage detection chip U28 is connected with the cathode of a polar capacitor C44, and the anode of the polar capacitor C44 is connected with the 3 rd pin of the voltage detection chip U28; a 2 nd pin of the voltage detection chip U28 is connected with an S pole of the MOS tube U27, a G pole of the MOS tube U27 is connected with a 1 st pin of the voltage detection chip U28, a D pole of the MOS tube U27 is respectively connected with one ends of a resistor R72, a resistor R73 and a resistor R74, and the other ends of the resistor R72, a resistor R73 and the resistor R74 are connected with a 3 rd pin of the voltage detection chip U28;

the 3 rd pin of the voltage detection chip U28 is connected with the 2 nd pin of the voltage detection chip U30, the 2 nd pin of the voltage detection chip U30 is connected with the cathode of a polar capacitor C45, and the anode of the polar capacitor C45 is connected with the 3 rd pin of the voltage detection chip U30; a 2 nd pin of the voltage detection chip U30 is connected with an S pole of the MOS tube U29, a G pole of the MOS tube U29 is connected with a 1 st pin of the voltage detection chip U30, a D pole of the MOS tube U29 is respectively connected with one ends of a resistor R75, a resistor R76 and a resistor R77, and the other ends of the resistor R75, a resistor R76 and the resistor R77 are connected with a 3 rd pin of the voltage detection chip U30;

the No. 1 pin and the No. 4 pin of the rectifier bridge are respectively connected with the No. 2 pin of the voltage detection chip U2 and the No. 3 pin of the voltage detection chip U30.

4. The covered FTU backup power supply super capacitor module according to claim 3, wherein the main circuit includes a processor U31, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a crystal oscillator Y12, a resistor R12, a capacitor C36157, a capacitor C158, a capacitor C12, a TVS 12, a tvu communication interface 36j 12, a TVS communication interface 36j communication chip, a tvu 12, a TVS communication interface 12, a tvu 36j communication interface, and a tvj communication interface;

the 94 th pin of the processor U31 is connected with one end of a resistor R78, and the other end of the resistor R78 is connected to the ground; two ends of a resistor R78 and a crystal oscillator Y1 are respectively connected with a 12 th pin and a 13 th pin of the processor U31, one end of the crystal oscillator Y1 is connected with a capacitor C2 and a capacitor C46 in series, one end of a capacitor C46 is connected with the other end of the crystal oscillator Y1, and the connection part of the capacitor C2 and the capacitor C46 is connected to the ground;

the 10 th pin, the 27 th pin, the 99 th pin, the 74 th pin and the 49 th pin of the processor U31 are connected with each other, and the 11 th pin, the 28 th pin, the 100 th pin, the 75 th pin and the 50 th pin of the processor U31 are connected with each other; two ends of the capacitor C3, the capacitor C4, the capacitor C5, the capacitor C6, the capacitor C7, the capacitor C8, the capacitor C9, the capacitor C10, the capacitor C11 and the capacitor C12 are respectively connected with a 11 th pin and a 10 th pin of the processor U31; the 10 th pin of the processor U31 is connected to ground, and the 11 th pin of the processor U31 is connected to the +3.3V terminal;

the 19 th pin of the processor U31 is connected with the 20 th pin, and the 21 st pin of the processor U31 is connected with the 220 th pin; two ends of the capacitor C13, the capacitor C14, the capacitor C15 and the capacitor C16 are respectively connected with a 22 th pin and a 20 th pin of the processor U31; the 20 th pin of the processor U31 is connected to ground, and the 22 nd pin of the processor U31 is connected to the +3.3V terminal;

the 8 th pin and the 10 th pin of the burning interface J1 are both connected to the ground, and the 1 st pin of the burning interface J1 is connected with the +3.3V end; the 3 rd pin, the 7 th pin and the 9 th pin of the burning interface J1 are respectively connected with the 14 th pin, the 72 th pin and the 76 th pin of the processor U31;

the 2 nd pin of the watchdog chip U32 is respectively connected with the +3.3V end and one end of a capacitor C57, the other end of the capacitor C57 is respectively connected with the 3 rd pin of the watchdog chip U32 and one ends of a resistor R9 and a resistor R4, and the other ends of a resistor R9 and a resistor R4 are respectively connected with the 4 th pin of the watchdog chip U32 and the 14 th pin of the processor U31; the 7 th pin of the watchdog chip U32 is connected with one end of a resistor R80, and the other end of the resistor R80 is connected with the 14 th pin of the processor U31; a resistor R5 is connected between the 8 th pin and the 1 st pin of the watchdog chip U32, the 1 st pin of the watchdog chip U32 is connected with the 1 st pin of the jumper cap JP2, the 2 nd pin of the jumper cap JP2 is respectively connected with a +3.3V end and one ends of a resistor R6, a resistor R7 and a resistor R8, and the other end of the resistor R6 is connected with the 1 st pin of the watchdog chip U32; the other end of the resistor R8 is connected with one end of the LED18, and the other ends of the LED18 and the resistor R7 are both connected with the 6 th pin of the watchdog chip U32;

the 1 st pin and the 8 th pin of the communication isolation chip U3 are respectively connected with a +3.3V end and a +5VA end, and the 4 th pin and the 5 th pin of the communication isolation chip U3 are both connected to the ground; the No. 2 pin and the No. 3 pin of the communication isolation chip U3 are respectively connected with the No. 69 pin and the No. 68 pin of the U31;

the 11 th pin and the 12 th pin of the communication chip U4 are respectively connected with one ends of a resistor R40 and a resistor R41, and the other ends of the resistor R40 and the resistor R41 are respectively connected with the 6 th pin and the 7 th pin of the communication isolation chip U3; a capacitor C23 is connected between the 1 st pin and the 3 rd pin of the communication chip U4; a capacitor C158 is connected between the 6 th pin and the 15 th pin of the communication chip U4, and the 15 th pin of the communication chip U4 is connected to the ground; the 2 nd pin of the communication chip U4 is connected with one end of a capacitor C26, and the other end of the capacitor C26 is connected to the ground; the 16 th pin of the communication chip U4 is respectively connected with one end of a capacitor C27 and the +5VA end, and the other end of the capacitor C27 is connected to the ground; the 4 th pin and the 5 th pin of the communication chip U4 are connected into a capacitor C157; the 13 th pin and the 14 th pin of the communication chip U4 are respectively connected with one ends of a resistor R43 and a resistor R42, the other end of the resistor R43 is connected with one end of a TVS2, and the other end of the TVS2 is connected to the ground; the other end of the resistor R42 is connected with one end of a TVS tube TVS1, and the other end of the TVS tube TVS1 is connected to the ground;

the 1 st pin of the communication interface J48 is connected with the junction of the resistor R42 and the TVS1, the 2 nd pin of the communication interface J48 is connected with the junction of the resistor R43 and the TVS2, and the 3 rd pin of the communication interface J48 is connected with the ground.

5. The covered FTU backup power supply super capacitor module as claimed in claim 4, wherein the voltage sampling circuit comprises operational amplifier chips U37A, U37B, U38A, U38B, U39A, U39B, U40A, U40B, U41A, U41B, U42A, U42B, U43A, U43B, U44A, U44B, U45A, U45B, U46A, U46B, resistor R114, resistor R115, resistor R116, resistor R117, resistor R118, resistor R119, resistor R120, resistor R121, resistor R122, resistor R123, resistor R124, resistor R125, resistor R126, resistor R127, resistor R128, resistor R129, resistor R130, resistor R131, resistor R132, resistor R133R 134, resistor R135, resistor R136, resistor R149, resistor R153, resistor R145R 142, resistor R145, resistor R145R 144, resistor R145R 144, resistor R140R 145R 148, resistor R150, resistor R148, resistor R, A resistor R157, a resistor R158, a resistor R159, a resistor R160, a resistor R161, a resistor R162, a resistor R163, a resistor R164, a resistor R165, a resistor R166, a resistor R167, a resistor R168, a resistor R169, a resistor R170, a resistor R171, a resistor R172, a resistor R173, a capacitor C113, a capacitor C114, a capacitor C115, a capacitor C116, a capacitor C117, a capacitor C118, a capacitor C119, a capacitor C120, a capacitor C121, a capacitor C122, a capacitor C123, a capacitor C124, a capacitor C125, a capacitor C126, a capacitor C127, a capacitor C128, a capacitor C129, a capacitor C130, a capacitor C131, a capacitor C132, a capacitor C133, a capacitor C134, a capacitor C135, a capacitor C136, a capacitor C137, a capacitor C138, a capacitor C139, a capacitor C140, a capacitor C141, a capacitor C142, a capacitor C143, a capacitor C144, a capacitor C145, a capacitor C146, a capacitor C147 and a capacitor C148;

the 4 th pin of the operational amplifier chip U37A is respectively connected with one end of a capacitor C113 and one end of a capacitor C115, and the other ends of the capacitor C113 and the capacitor C115 are both connected to the ground; the 3 rd pin of the operational amplifier chip U37A is respectively connected with a resistor R119 and a capacitor C116, the other end of the capacitor C116 is connected to the ground, and the other ends of the resistor R119 and the capacitor C116 are respectively connected with the positive electrode and the negative electrode of the polar capacitor C1; a resistor R118 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U37A; a resistor R115 is connected between the 1 st pin of the operational amplifier chip U37A and the 6 th pin of the operational amplifier chip U37B; the 5 th pin of the operational amplifier chip U37B is connected with one end of a resistor R117, and the other end of the resistor R117 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U37B are directly connected to the resistor R116; the 7 th pin of the operational amplifier chip U37B is connected in series with a resistor R114 and a capacitor C114, the other end of the capacitor C114 is connected to the ground, and the connection position of the resistor R114 and the capacitor C114 is connected with the 23 rd pin of the processor U31;

the 4 th pin of the operational amplifier chip U38A is respectively connected with one ends of a capacitor C117 and a capacitor C119, and the other ends of the capacitor C117 and the capacitor C119 are both connected to the ground; the 3 rd pin of the operational amplifier chip U38A is respectively connected with a resistor R125 and a capacitor C120, the other end of the capacitor C120 is connected to the ground, and the other ends of the resistor R125 and the capacitor C120 are respectively connected with the positive electrode and the negative electrode of a polar capacitor C37; a resistor R124 is connected between the No. 1 pin and the No. 2 pin of the operational amplifier chip U38A; a resistor R121 is connected between the 1 st pin of the operational amplifier chip U38A and the 6 th pin of the operational amplifier chip U38B; the 5 th pin of the operational amplifier chip U38B is connected with one end of a resistor R123, and the other end of the resistor R123 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U38B are directly connected to the resistor R122; the 7 th pin of the operational amplifier chip U38B is connected in series with a resistor R120 and a capacitor C118, the other end of the capacitor C118 is connected to the ground, and the connection position of the resistor R120 and the capacitor C118 is connected with the 24 th pin of the processor U31;

the 4 th pin of the operational amplifier chip U39A is respectively connected with one ends of a capacitor C121 and a capacitor C123, and the other ends of the capacitor C121 and the capacitor C123 are both connected to the ground; the 3 rd pin of the operational amplifier chip U39A is respectively connected with the resistor R131 and the capacitor C124, the other end of the capacitor C124 is connected to the ground, and the other ends of the resistor R131 and the capacitor C124 are respectively connected with the positive electrode and the negative electrode of the polar capacitor C38; a resistor R130 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U39A; a resistor R127 is connected between the 1 st pin of the operational amplifier chip U39A and the 6 th pin of the operational amplifier chip U39B; the 5 th pin of the operational amplifier chip U39B is connected with one end of a resistor R129, and the other end of the resistor R129 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U39B are directly connected to the resistor R128; the 7 th pin of the operational amplifier chip U39B is connected in series with a resistor R126 and a capacitor C122, the other end of the capacitor C122 is connected to the ground, and the connection part of the resistor R126 and the capacitor C122 is connected with the 25 th pin of the processor U31;

the 4 th pin of the operational amplifier chip U40A is respectively connected with one end of a capacitor C125 and one end of a capacitor C127, and the other ends of the capacitor C125 and the capacitor C127 are both connected to the ground; the 3 rd pin of the operational amplifier chip U40A is respectively connected with a resistor R137 and a capacitor C128, the other end of the capacitor C128 is connected to the ground, and the other ends of the resistor R137 and the capacitor C128 are respectively connected with the positive electrode and the negative electrode of the polar capacitor C39; a resistor R136 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U40A; a resistor R133 is connected between the 1 st pin of the operational amplifier chip U40A and the 6 th pin of the operational amplifier chip U40B; the 5 th pin of the operational amplifier chip U40B is connected with one end of a resistor R135, and the other end of the resistor R135 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U40B are directly connected to the resistor R134; the 7 th pin of the operational amplifier chip U40B is connected in series with a resistor R132 and a capacitor C126, the other end of the capacitor C126 is connected to the ground, and the connection position of the resistor R132 and the capacitor C126 is connected with the 26 th pin of the processor U31;

the 4 th pin of the operational amplifier chip U41A is respectively connected with one ends of a capacitor C129 and a capacitor C131, and the other ends of the capacitor C129 and the capacitor C131 are both connected to the ground; the 3 rd pin of the operational amplifier chip U41A is connected with a resistor R143 and a capacitor C132 respectively, the other end of the capacitor C132 is connected to the ground, and the other ends of the resistor R143 and the capacitor C132 are connected with the positive electrode and the negative electrode of the polar capacitor C40 respectively; a resistor R142 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U41A; a resistor R139 is connected between the 1 st pin of the operational amplifier chip U41A and the 6 th pin of the operational amplifier chip U41B; the 5 th pin of the operational amplifier chip U41B is connected with one end of a resistor R141, and the other end of the resistor R141 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U41B are directly connected to the resistor R140; the 7 th pin of the operational amplifier chip U41B is connected in series with a resistor R138 and a capacitor C130, the other end of the capacitor C130 is connected to the ground, and the connection position of the resistor R138 and the capacitor C130 is connected with the 29 th pin of the processor U31;

the 4 th pin of the operational amplifier chip U42A is respectively connected with one end of a capacitor C133 and one end of a capacitor C135, and the other ends of the capacitor C133 and the capacitor C135 are both connected to the ground; the 3 rd pin of the operational amplifier chip U42A is connected with a resistor R149 and a capacitor C136 respectively, the other end of the capacitor C136 is connected to the ground, and the other ends of the resistor R149 and the capacitor C136 are connected with the positive and negative electrodes of a polarity capacitor C41 respectively; a resistor R148 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U42A; a resistor R145 is connected between the 1 st pin of the operational amplifier chip U42A and the 6 th pin of the operational amplifier chip U42B; the 5 th pin of the operational amplifier chip U42B is connected with one end of a resistor R147, and the other end of the resistor R147 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U42B are directly connected to the resistor R146; the 7 th pin of the operational amplifier chip U42B is connected in series with a resistor R144 and a capacitor C134, the other end of the capacitor C134 is connected to the ground, and the connection position of the resistor R144 and the capacitor C134 is connected with the 30 th pin of the processor U31;

the 4 th pin of the operational amplifier chip U43A is respectively connected with one end of a capacitor C137 and one end of a capacitor C139, and the other ends of the capacitor C137 and the capacitor C139 are both connected to the ground; the 3 rd pin of the operational amplifier chip U43A is respectively connected with the resistor R155 and the capacitor C140, the other end of the capacitor C140 is connected to the ground, and the other ends of the resistor R155 and the capacitor C140 are respectively connected with the positive electrode and the negative electrode of the polar capacitor C42; a resistor R154 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U43A; a resistor R151 is connected between the 1 st pin of the operational amplifier chip U43A and the 6 th pin of the operational amplifier chip U43B; the 5 th pin of the operational amplifier chip U43B is connected with one end of a resistor R153, and the other end of the resistor R153 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U43B are directly connected to the resistor R152; the 7 th pin of the operational amplifier chip U43B is connected in series with a resistor R150 and a capacitor C138, the other end of the capacitor C138 is connected to the ground, and the connection part of the resistor R150 and the capacitor C138 is connected with the 31 st pin of the processor U31;

the 4 th pin of the operational amplifier chip U44A is respectively connected with one end of a capacitor C141 and one end of a capacitor C143, and the other ends of the capacitor C141 and the capacitor C143 are both connected to the ground; the 3 rd pin of the operational amplifier chip U44A is respectively connected with the resistor R161 and the capacitor C144, the other end of the capacitor C144 is connected to the ground, and the other ends of the resistor R161 and the capacitor C144 are respectively connected with the positive electrode and the negative electrode of the polar capacitor C43; a resistor R160 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U44A; a resistor R157 is connected between the 1 st pin of the operational amplifier chip U44A and the 6 th pin of the operational amplifier chip U44B; the 5 th pin of the operational amplifier chip U44B is connected with one end of a resistor R159, and the other end of the resistor R159 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U44B are directly connected to the resistor R158; the 7 th pin of the operational amplifier chip U44B is connected in series with a resistor R156 and a capacitor C142, the other end of the capacitor C142 is connected to the ground, and the connection part of the resistor R156 and the capacitor C142 is connected with the 32 nd pin of the processor U31;

a 4 th pin of the operational amplifier chip U45A is respectively connected with one ends of a capacitor C145 and a capacitor C147, and the other ends of the capacitor C145 and the capacitor C147 are both connected to the ground; the 3 rd pin of the operational amplifier chip U45A is respectively connected with a resistor R167 and a capacitor C148, the other end of the capacitor C148 is connected to the ground, and the other ends of the resistor R167 and the capacitor C148 are respectively connected with the positive electrode and the negative electrode of the polarity capacitor C44; a resistor R166 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U45A; a resistor R163 is connected between the 1 st pin of the operational amplifier chip U45A and the 6 th pin of the operational amplifier chip U45B; the 5 th pin of the operational amplifier chip U45B is connected with one end of a resistor R165, and the other end of the resistor R165 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U45B are directly connected to the resistor R164; the 7 th pin of the operational amplifier chip U45B is connected in series with a resistor R162 and a capacitor C146, the other end of the capacitor C146 is connected to the ground, and the connection position of the resistor R162 and the capacitor C146 is connected with the 35 th pin of the processor U31;

the 4 th pin of the operational amplifier chip U46A is respectively connected with one end of a capacitor C149 and one end of a capacitor C151, and the other ends of the capacitor C149 and the capacitor C151 are both connected to the ground; the 3 rd pin of the operational amplifier chip U46A is respectively connected with a resistor R173 and a capacitor C152, the other end of the capacitor C152 is connected to the ground, and the other ends of the resistor R173 and the capacitor C152 are respectively connected with the positive electrode and the negative electrode of the polarity capacitor C45; a resistor R172 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U46A; a resistor R169 is connected between the 1 st pin of the operational amplifier chip U46A and the 6 th pin of the operational amplifier chip U46B; the 5 th pin of the operational amplifier chip U46B is connected with one end of a resistor R170, and the other end of the resistor R170 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U46B are directly connected to the resistor R171; the 7 th pin of the operational amplifier chip U46B is connected in series with a resistor R168 and a capacitor C150, the other end of the capacitor C150 is connected to ground, and the connection point of the resistor R168 and the capacitor C150 is connected with the 36 th pin of the processor U31.

6. The covered FTU backup power supply super capacitor module according to claim 5, wherein the current sampling circuit comprises an operational amplifier chip U47A, an operational amplifier chip U47B, a current Hall sensor U8, an interface J2, a resistor R16, a resistor R16, a resistor R174, a resistor R175, a resistor R176, a resistor R177, a resistor R178, a capacitor C21, a capacitor C24, a capacitor C25, a capacitor C21, a capacitor C153, a capacitor C154, a capacitor C155, and a capacitor C156;

a 4 th pin of the operational amplifier chip U47A is respectively connected with one ends of a capacitor C153 and a capacitor C155, and the other ends of the capacitor C153 and the capacitor C155 are both connected to the ground; the 3 rd pin of the operational amplifier chip U47A is respectively connected with a resistor R179 and a capacitor C156, and the other end of the capacitor C156 is connected to the ground; a resistor R178 is connected between the 1 st pin and the 2 nd pin of the operational amplifier chip U47A; a resistor R175 is connected between the 1 st pin of the operational amplifier chip U47A and the 6 th pin of the operational amplifier chip U47B; the 5 th pin of the operational amplifier chip U47B is connected with one end of a resistor R176, and the other end of the resistor R176 is connected to the ground; the 6 th pin and the 7 th pin of the operational amplifier chip U47B are directly connected to the resistor R177; the 7 th pin of the operational amplifier chip U46B is connected in series with a resistor R174 and a capacitor C154, the other end of the capacitor C154 is connected to the ground, and the connection position of the resistor R174 and the capacitor C154 is connected with the 15 th pin of the processor U31;

the 1 st pin and the 2 nd pin of the interface J2 are respectively connected with a +26.5VDC terminal and a-26.5 VDC terminal;

the 1 st pin and the 2 nd pin of the current Hall sensor U8 are connected with the 1 st pin of the interface J2, and the 3 rd pin and the 4 th pin of the current Hall sensor U8 are connected with the 22 nd pin of the interface J2; the 5 th pin of the current Hall sensor U8 is connected to the ground; the 6 th pin of the current Hall sensor U8 is connected with one end of a capacitor C24, and the other end of the capacitor C24 is connected to the ground; a 7 th pin of the current Hall sensor U8 is connected in series with a resistor R16 and a capacitor C25, the other end of the capacitor C25 is connected to the ground, and the connection part of the resistor R16 and the capacitor C25 is connected with the other end of the resistor R179; the 8 th pin of the current Hall sensor U8 is respectively connected with the +5V terminal and one end of a capacitor C21, and the other end of the capacitor C21 is connected with the ground.

7. The shrouded FTU backup power supercapacitor module of claim 6 further comprising a voltage conversion circuit comprising a power module U5, a resistor R29, a resistor R24, a polar capacitor C92, a capacitor C93, a capacitor C94, a capacitor C95, a capacitor C96, a capacitor C97, a chip inductor B13;

a 1 st pin and a 2 nd pin of the power module U5 are respectively connected with two ends of a polar capacitor C92, a capacitor C93 and a capacitor C94, and a resistor R29 is connected between the polar capacitor C92 and the capacitor C93; pin 1 of the power module U5 is connected to the +26.5VDC terminal, and pin 2 is connected to ground;

a 4 th pin of the power module U5 is respectively connected with a resistor R24 and a chip inductor B13 in series, the other end of the chip inductor B13 is respectively connected with one ends of a capacitor C95, a capacitor C96 and a capacitor C97, and the other ends of the capacitor C95, the capacitor C96 and the capacitor C97 are all connected with a 3 rd pin of the power module U5; the other end of the chip inductor B13 is connected to the +5V terminal, and the 3 rd pin of the power module U5 is connected to the ground.

8. The cap FTU backup power supercapacitor module of claim 7, further comprising a conversion regulation circuit comprising a linear regulator U33, a capacitor C50, a capacitor C51, a capacitor C52, a capacitor C53, a capacitor C54, a capacitor C55, a capacitor C56, and a diode D9;

the 1 st pin and the 2 nd pin of the linear voltage regulator U33 are respectively connected with two ends of a capacitor C50 and a capacitor C51, the 1 st pin of the linear voltage regulator U33 is connected to the ground, and the 2 nd pin is connected with a +5V end; the 2 nd pin and the 3 rd pin of the linear voltage regulator U33 are connected with the 4 th pin, a diode D9 is connected between the 2 nd pin and the 3 rd pin, and the output end of the diode D9 is connected with the 1 st pin of the linear voltage regulator U33;

the 2 nd pin of the linear voltage regulator U33 is respectively connected with the +3.3V terminal and one end of a capacitor C52, a capacitor C53, a capacitor C54, a capacitor C55 and a capacitor C56, and the other end of the capacitor C52, the capacitor C53, the capacitor C54, the capacitor C55 and the capacitor C56 is connected with the ground.

9. The capped FTU backup power supercapacitor module according to claim 8, further comprising an isolation circuit comprising an isolation power module U12, a resistor R180, and a resistor R181; the 1 st pin of the isolation power supply module U12 is connected with one end of a resistor R180, and the other end of the resistor R180 is connected with a +5V end; a 7 th pin of the isolation power supply module U12 is connected with one end of a resistor R181, and the other end of the resistor R181 is connected with a +5V end; the No. 2 pin and the No. 5 pin of the isolation power supply module U12 are both connected to ground.

10. The capped FTU backup power supercapacitor module according to claim 9, further comprising a power indication circuit comprising a resistor R83 and an LED16, wherein the resistor R83 is connected in series with the LED16, wherein the other end of the resistor R83 is connected to the +3.3V terminal, and the other end of the LED16 is connected to ground.