CN113345970A - P-type back contact type crystalline silicon solar cell, preparation method and cell assembly - Google Patents

P-type back contact type crystalline silicon solar cell, preparation method and cell assembly Download PDF

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CN113345970A
CN113345970A CN202110627504.6A CN202110627504A CN113345970A CN 113345970 A CN113345970 A CN 113345970A CN 202110627504 A CN202110627504 A CN 202110627504A CN 113345970 A CN113345970 A CN 113345970A
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silicon wafer
type silicon
solar cell
doped
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邵家俊
陈刚
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Zhejiang Aiko Solar Energy Technology Co Ltd
Guangdong Aiko Technology Co Ltd
Tianjin Aiko Solar Energy Technology Co Ltd
Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
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Zhejiang Aiko Solar Energy Technology Co Ltd
Guangdong Aiko Technology Co Ltd
Tianjin Aiko Solar Energy Technology Co Ltd
Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
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    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
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    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H01L31/022458—Electrode arrangements specially adapted for back-contact solar cells for emitter wrap-through [EWT] type solar cells, e.g. interdigitated emitter-base back-contacts
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Abstract

The invention is suitable for the technical field of solar cell processing, and provides a P-type back contact type crystalline silicon solar cell, a preparation method and a cell assembly, wherein the P-type back contact type crystalline silicon solar cell comprises a P-type silicon wafer, and the front surface of the P-type silicon wafer is provided with a passivation antireflection layer; the back of the silicon chip substrate is provided with a P + doped region, an N + doped region, a back passivation layer, a positive electrode and a negative electrode, wherein the P + doped region and the N + doped region are alternately distributed at intervals; the N + doped region comprises a tunneling oxide layer arranged on the back surface of the P-type silicon wafer and N + doped polycrystalline silicon arranged on the tunneling oxide layer; the back of the P-type silicon wafer is provided with a textured structure at a position corresponding to the negative electrode, and the negative electrode is provided with a rough texture structure which forms ohmic contact with the N + doped polycrystalline silicon at a position corresponding to the textured structure. The P-type back contact type crystalline silicon solar cell provided by the invention can effectively improve the ohmic contact between the negative electrode and the N + doped polycrystalline silicon, improves the cell efficiency, and has the advantages of simple implementation mode and low implementation cost.

Description

P-type back contact type crystalline silicon solar cell, preparation method and cell assembly
Technical Field
The invention relates to the technical field of solar cell processing, in particular to a P-type back contact crystalline silicon solar cell, a preparation method and a cell module.
Background
At present, with the gradual depletion of fossil energy, solar cells are increasingly widely used as a new energy alternative. A solar cell is a device that converts light energy of the sun into electric energy. The solar cell generates current carriers by utilizing a photovoltaic principle, and then the current carriers are led out by using the electrodes, so that the electric energy is effectively utilized. The P-type back-contact crystalline silicon solar cell generally comprises a P-type silicon wafer, wherein a passivation antireflection layer is arranged on the front surface of the P-type silicon wafer, a tunneling oxide layer, N + doped polycrystalline silicon arranged on the tunneling oxide layer, a P + doped region which is arranged on the back surface of the P-type silicon wafer and is distributed alternately with the N + doped polycrystalline silicon, and a back passivation layer covering the N + doped polycrystalline silicon are arranged on the back surface of the P-type silicon wafer, the N + doped polycrystalline silicon is provided with a negative electrode, and the P + doped region is provided with a positive electrode.
In the prior art, since the P-type back-contact crystalline silicon solar cell needs to be polished before the tunneling oxide layer is prepared, and the position of the back surface of the P-type silicon wafer, which corresponds to the negative electrode, is in contact with the tunneling oxide layer through a polished surface, in this way, both the N + doped polycrystalline silicon prepared on the tunneling oxide layer and the back passivation layer prepared on the N + doped polycrystalline silicon are in a planar structure, ohmic contact is realized between the printed and sintered negative electrode and the N + doped polycrystalline silicon through planar contact, and the ohmic contact effect between the negative electrode and the N + doped polycrystalline silicon is poor, so that the cell efficiency is affected.
Disclosure of Invention
The invention provides a P-type back contact type crystalline silicon solar cell, and aims to solve the problem that in the prior art, the ohmic contact effect between the negative electrode of the P-type back contact type crystalline silicon solar cell and N + doped polycrystalline silicon is poor, so that the cell efficiency is influenced.
The invention is realized in such a way, and provides a P-type back contact crystalline silicon solar cell, which comprises a P-type silicon wafer, wherein the front surface of the P-type silicon wafer is provided with a passivation antireflection layer;
the back surface of the P-type silicon wafer is provided with a P + doped region, an N + doped region, a back passivation layer, a positive electrode and a negative electrode, the P + doped region and the N + doped region are alternately distributed at intervals, and the back passivation layer covers the P + doped region and the N + doped region;
the N + doped region comprises a tunneling oxide layer arranged on the back surface of the P-type silicon wafer and N + doped polycrystalline silicon arranged on the tunneling oxide layer, the positive electrode and the P + doped region form ohmic contact, and the negative electrode and the N + doped polycrystalline silicon form ohmic contact; the back surface of the P-type silicon wafer is provided with a textured structure corresponding to the negative electrode, and the negative electrode is provided with a rough texture structure which forms ohmic contact with the N + doped polycrystalline silicon and corresponds to the textured structure.
Preferably, the width of the suede structure is 80-200 um.
Preferably, the sheet resistance of the N + doped polysilicon is 50-200 omega/sqr.
Preferably, the back surface of the P-type silicon wafer is provided with grooves corresponding to the number of the P + doped regions, and each P + doped region is correspondingly arranged at the bottom of one groove.
Preferably, the bottom of the groove is provided with a suede surface, the positive electrode is arranged on the suede surface, and the back passivation layer covers the suede surface.
Preferably, the width of the groove is 300-600um, the depth of the groove is 0.3-10um, and the distance between two adjacent grooves is 20-500 um.
Preferably, the thickness of the tunneling oxide layer is 1-5 nm.
Preferably, the passivated antireflection layer and the back passivation layer are respectively one or more combinations of an aluminum oxide film, a silicon nitride film and a silicon oxynitride film.
The invention also provides a preparation method of the P-type back contact crystalline silicon solar cell, which comprises the following steps:
polishing: selecting a P-type silicon wafer, and polishing the P-type silicon wafer;
first texturing: texturing at a position, corresponding to the position where the negative electrode is prepared, on the back surface of the P-type silicon wafer to form a textured structure;
preparing a tunneling oxide layer: preparing a tunneling oxide layer on the back of the P-type silicon wafer;
preparing N + doped polysilicon: preparing N + doped polysilicon on the back of the P-type silicon wafer;
and (3) second texturing: texturing is carried out on the front side of the P-type silicon wafer to form a textured surface;
preparing a passivated antireflection layer and a back passivation layer: preparing a passivated antireflection layer on the front side of the P-type silicon wafer, and preparing a back passivation layer on the back side of the P-type silicon wafer;
laser grooving: performing laser grooving on the back of the P-type silicon wafer at a position corresponding to the position where the positive electrode is prepared so as to expose the P-type silicon wafer;
printing and sintering positive and negative electrodes: printing a negative electrode at the first texturing position on the back surface of the P-type silicon wafer by using silver slurry, printing a positive electrode at the laser grooving position on the back surface of the P-type silicon wafer by using aluminum slurry, sintering and drying to form a P + doping area between the positive electrode and the P-type silicon wafer, and forming a rough texture structure which forms ohmic contact with the N + doping polycrystalline silicon by using the negative electrode.
Preferably, the polishing treatment of the P-type silicon wafer specifically comprises:
and (3) polishing the P-type silicon wafer by using an alkali solution with the concentration of 1.5-15%, wherein the reflectivity of the polished P-type silicon wafer is controlled to be 38% -45%.
Preferably, the first texturing step includes:
preparing a mask on the back of the P-type silicon wafer;
carrying out laser ablation etching mask at the position of the back of the P-type silicon wafer corresponding to the prepared negative electrode so as to expose the P-type silicon wafer;
and texturing in a laser ablation area on the back of the P-type silicon wafer to form a textured structure, and removing a mask in a non-laser ablation area through acid washing.
Preferably, the thickness of the tunneling oxide layer is controlled to be 1-5 nm.
Preferably, the thickness of the N + doped polysilicon is controlled to be 50-350 nm.
Preferably, the second texturing step further includes:
and texturing at the position, corresponding to the positive electrode, of the back of the P-type silicon wafer to form a textured surface.
Preferably, the second texturing step specifically includes:
preparing a mask on the back of the P-type silicon wafer;
performing laser local ablation etching mask on the position, corresponding to the prepared positive electrode, on the back surface of the P-type silicon wafer to expose the P-type silicon wafer;
texturing is carried out on the laser ablation areas on the front side and the back side of the P-type silicon wafer to form a textured surface, and the mask of the non-laser ablation area is removed through acid washing.
Preferably, the step of preparing the N + doped polysilicon specifically includes:
depositing N + doped amorphous silicon on the back of the P-type silicon wafer, and crystallizing the N + doped amorphous silicon into N + doped polycrystalline silicon at high temperature; or the like, or, alternatively,
depositing intrinsic amorphous silicon on the back of the P-type silicon wafer, carrying out phosphorus diffusion on the intrinsic amorphous silicon to obtain N + doped amorphous silicon, and crystallizing the N + doped amorphous silicon into N + doped polycrystalline silicon at high temperature.
Preferably, the thickness of the back passivation layer is controlled to be 60-150nm, and the refractive index is controlled to be 2-2.5.
The invention also provides a solar cell module which comprises the P-type back contact crystalline silicon solar cell.
According to the P-type back contact type crystalline silicon solar cell, the textured structure is arranged at the position, corresponding to the negative electrode, of the back surface of the P-type silicon wafer, so that a rough texture structure which forms ohmic contact with N + doped polycrystalline silicon is formed at the position, corresponding to the textured structure, of the negative electrode obtained through printing and sintering, ohmic contact is formed between the negative electrode and the N + doped polycrystalline silicon through the rough texture structure, the contact area between the negative electrode and the N + doped polycrystalline silicon is increased, good ohmic contact is formed between the negative electrode and the N + doped polycrystalline silicon, and the cell efficiency is improved; moreover, by only adding one texturing process before preparing the tunneling oxide layer, the textured structure can be prepared on the back surface of the P-type silicon wafer of the P-type back contact type crystalline silicon solar cell, the tunneling oxide layer, the N + doped polycrystalline silicon and the position of the back passivation layer corresponding to the negative electrode, so that the printed and sintered negative electrode can form a rough texture structure to form good ohmic contact with the N + doped polycrystalline silicon, the realization method is simple, and the realization cost is low.
Drawings
Fig. 1 is a schematic structural diagram of a P-type back contact crystalline silicon solar cell according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing a P-type back contact crystalline silicon solar cell according to a second embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
According to the P-type back contact type crystalline silicon solar cell provided by the embodiment of the invention, the textured structure is arranged at the position, corresponding to the negative electrode, on the back surface of the P-type silicon wafer, so that the position, corresponding to the textured structure, of the negative electrode obtained by printing and sintering forms a rough texture structure which forms ohmic contact with N + doped polycrystalline silicon, and thus the negative electrode forms ohmic contact with the N + doped polycrystalline silicon through the rough texture structure, the contact area of the negative electrode and the N + doped polycrystalline silicon is increased, good ohmic contact is formed between the negative electrode and the N + doped polycrystalline silicon, and the cell efficiency is improved; moreover, by only adding one texturing process before preparing the tunneling oxide layer, the textured structure can be prepared on the back surface of the P-type silicon wafer of the P-type back contact type crystalline silicon solar cell, the tunneling oxide layer, the N + doped polycrystalline silicon and the position of the back passivation layer corresponding to the negative electrode, so that the printed and sintered negative electrode can form a rough texture structure to form good ohmic contact with the N + doped polycrystalline silicon, the realization method is simple, and the realization cost is low.
Example one
Referring to fig. 1, the present embodiment provides a P-type back contact crystalline silicon solar cell, which includes a P-type silicon wafer 1, and a passivation antireflection layer 2 is disposed on a front surface of the P-type silicon wafer 1.
The back of the P-type silicon wafer 1 is provided with a P + doped region 3, an N + doped region 4, a back passivation layer 5, a positive electrode 6 and a negative electrode 7, the P + doped region 3 and the N + doped region 4 are alternately distributed at intervals, and the back passivation layer 5 covers the P + doped region 3 and the N + doped region 4.
The N + doped region 4 comprises a tunneling oxide layer 41 arranged on the back surface of the P-type silicon wafer 1 and N + doped polycrystalline silicon 42 arranged on the tunneling oxide layer 41, the positive electrode 6 and the P + doped region 3 form ohmic contact, and the negative electrode 7 and the N + doped polycrystalline silicon 42 form ohmic contact; the back of the P-type silicon wafer 1 is provided with a textured structure 10 at a position corresponding to the negative electrode 7, and the negative electrode 7 is provided with a rough texture structure 71 forming ohmic contact with the N + doped polycrystalline silicon 42 at a position corresponding to the textured structure 10.
As an embodiment of the present invention, the passivated antireflection layer 2 and the back passivation layer 5 are one or more combinations of an aluminum oxide film, a silicon nitride film, and a silicon oxynitride film, respectively.
As an embodiment of the invention, the passivated antireflection layer 2 comprises a passivation film 21 arranged on the front surface of the P-type silicon wafer 1 and an antireflection film 22 arranged on the passivation film 21, so as to reduce the effective reduction of surface recombination of the silicon wafer and reduce the reflection of sunlight on the front surface of the silicon wafer. Preferably, the passivation film 21 is an aluminum oxide film, and the antireflection film 22 is a silicon nitride film.
As an embodiment of the present invention, the thickness of the passivated anti-reflective layer 2 is 80-150nm, so that the passivated anti-reflective layer 2 has good passivation and anti-reflective effects.
As a preferred embodiment of the present invention, the back passivation layer 5 is a silicon nitride film, and the back of the silicon wafer can be passivated well by using the good stability and passivation effect of the silicon nitride film.
As an embodiment of the invention, the thickness of the back passivation layer 5 is 60-150nm, and the refractive index is 2-2.5, so that the back of the silicon wafer can be passivated well, and the absorption and utilization of the silicon wafer to light can be increased.
As an embodiment of the present invention, the back surface of the P-type silicon wafer 1 is provided with grooves 11 corresponding to the number of the P + doped regions 3, and each P + doped region 3 is correspondingly disposed at the bottom of one groove 11. The number of the grooves 11 is equal to the number of the P + doped regions 3, and the number of the P + doped regions 3 and the number of the grooves 11 are 4 in fig. 1. The groove 11 is formed in the back face of the P-type silicon wafer 1, so that the P + doping area 3 is spaced from the N + doping area 4 through the groove 11, the P + doping area 3 is prevented from being in contact with the N + doping area 4, electric leakage is avoided, and accordingly safety performance and efficiency of a battery are improved.
In one embodiment of the invention, the groove 11 is circular, trapezoidal, or square. In one embodiment, as shown in fig. 1, the recess 11 is square. The groove 11 is preferably configured to be circular arc or trapezoid, wherein when the groove 11 is configured to be circular arc or trapezoid, the effect of light reflected by the inner wall of the groove 11 is better, and meanwhile, when the groove 11 is configured to be square, the actual production process is simpler, so that the shape of the groove 11 can be flexibly configured according to actual use requirements, and no specific limitation is made herein.
As an embodiment of the present invention, the bottom of the groove 11 is provided with a textured surface on which the positive electrode 6 is disposed, and the backside passivation layer 5 covers the textured surface. Wherein the pile surface at the bottom of the groove 11 can be made by a pile making process. Because the bottom of the groove 11 is provided with the suede, the positive electrode 6 and the suede form ohmic contact, so that the ohmic contact effect of the positive electrode 6 and the P-type silicon wafer 1 can be improved; and the back passivation layer 5 covering the P + doped region 3 can be more stably attached to the P + doped region 3, thereby achieving a good passivation effect.
As an embodiment of the present invention, the width of the groove 11 is 300-600um, the depth of the groove 11 is 0.3-10um, and the distance between two adjacent grooves 11 is 20-500um, so that the P + doped region 3 and the N + doped region 4 can be well isolated, the P + doped region 3 and the N + doped region 4 can be prevented from contacting with each other, and the groove 11 can be easily processed.
As an embodiment of the present invention, the texture 10 and the coarse texture 71 may be irregular zigzag type texture, hemispherical type texture, or pyramid type texture.
In the embodiment of the invention, the textured structure 10 is arranged at the position, corresponding to the negative electrode 7, of the back surface of the P-type silicon wafer 1, and when the tunneling oxide layer 41 is prepared, the textured structure is also formed at the position, corresponding to the textured structure of the P-type silicon wafer 1, of the tunneling oxide layer 41; when the N + doped polysilicon 42 is prepared on the tunneling oxide layer 41, the N + doped polysilicon 42 forms a textured structure corresponding to the textured structure position on the tunneling oxide layer 41; when the back passivation layer 5 is prepared, the back passivation layer 5 also forms a textured structure corresponding to the textured structure position on the N + doped polysilicon 42, namely, the position corresponding to the negative electrode 7, and the back surface of the P-type silicon wafer 1, the tunneling oxide layer 41, the N + doped polysilicon 42 and the back passivation layer 5 are all provided with textured structures, so that after the negative electrode 7 is silk-screened by adopting silver paste, the silver paste is sintered at high temperature, the silver paste ablates the textured back passivation layer 5 at high temperature, one end of the sintered negative electrode 7 in the N + doped polysilicon 42 forms a rough texture structure 71 with the shape approximately the same as that of the textured structure of the back passivation layer 5, the negative electrode 7 forms ohmic contact with the N + doped polysilicon 42 through the rough texture structure 71, the contact area of the negative electrode 7 and the N + doped polysilicon 42 is increased, and the negative electrode 7 and the N + doped polysilicon 42 form good ohmic contact, the efficiency of the battery is improved.
In addition, the P-type back-contact crystalline silicon solar cell provided by the embodiment of the invention can make the back surface of the P-type silicon wafer 1, the tunneling oxide layer 41, the N + doped polycrystalline silicon 42 and the back passivation layer 5 all have a textured structure by adding the texturing process before preparing the tunneling oxide layer 41 in the process of preparing the traditional P-type back-contact crystalline silicon solar cell, so that the printed and sintered negative electrode 7 can form a rough texture structure to realize good ohmic contact with the N + doped polycrystalline silicon 42, and the implementation process is simple and the implementation cost is low.
As an embodiment of the invention, the width of the textured structure 10 on the back surface of the P-type silicon wafer 1 corresponding to the position of the negative electrode 7 is 80-200um, so that the tunneling oxide layer 41, the N + doped polysilicon 42 and the back passivation layer 5 are all made into a textured surface with a width of 80-200um, and a rough texture structure 71 with a proper width can be formed at one end of the printed and sintered negative electrode 7 inside the N + doped polysilicon 42, so as to further improve the ohmic contact effect between the negative electrode 7 and the N + doped polysilicon 42.
As an embodiment of the present invention, the thickness of the N + doped polysilicon 42 is controlled to be 50-350nm, ensuring good cell efficiency of the cell.
As an embodiment of the present invention, the sheet resistance of the N + doped polysilicon 42 is 50 to 200 Ω/sqr, so that the negative electrode 7 and the N + doped polysilicon 42 can form a good ohmic contact.
As an embodiment of the present invention, the thickness of the tunnel oxide layer 41 is 1-5nm, so that the tunnel oxide layer 41 has a good passivation effect. The tunnel oxide layer 41 is a silicon oxide layer.
According to the P-type back contact type crystalline silicon solar cell provided by the embodiment of the invention, the textured structure 10 is arranged at the position, corresponding to the negative electrode 7, on the back surface of the P-type silicon wafer 1, so that the rough texture structure 71 forming ohmic contact with the N + doped polycrystalline silicon 42 is formed at the position, corresponding to the textured surface, of the negative electrode 7 obtained by printing and sintering the P-type back contact type crystalline silicon solar cell, and the ohmic contact is formed between the negative electrode 7 and the N + doped polycrystalline silicon 42 through the rough texture structure, the contact area between the negative electrode 7 and the N + doped polycrystalline silicon 42 is greatly increased, so that the negative electrode 7 and the N + doped polycrystalline silicon 42 form good ohmic contact, and the cell efficiency is improved. Moreover, as long as a texturing process is added before the tunneling oxide layer 41 is prepared, the back surface of the P-type silicon wafer 1 of the P-type back contact type crystalline silicon solar cell, the tunneling oxide layer 41, the N + doped polycrystalline silicon 42 and the back passivation layer 5 can be made into textured structures, so that the printed and sintered negative electrode 7 can form a rough texture structure to form good ohmic contact with the N + doped polycrystalline silicon 42, the implementation mode is simple, and the implementation cost is low.
Example two
With reference to fig. 2, the present embodiment further provides a method for manufacturing the P-type back-contact crystalline silicon solar cell of the first embodiment, including:
step S1, polishing: selecting a P-type silicon wafer 1, and polishing the P-type silicon wafer 1;
as an embodiment of the present invention, the polishing process of the P-type silicon wafer 1 specifically includes:
and (3) polishing the P-type silicon wafer 1 by using an alkali solution with the concentration of 1.5-15%, wherein the reflectivity of the polished P-type silicon wafer 1 is controlled to be 38-45%. Wherein, the alkali solution can be KOH solution or NaOH solution.
Step S2, first texturing: texturing is carried out on the back of the P-type silicon wafer 1 corresponding to the position where the negative electrode 7 is prepared to form a textured structure 10;
in the embodiment of the invention, the textured structure 10 is formed by texturing the position, corresponding to the preparation of the negative electrode 7, on the back surface of the P-type silicon wafer 1, so that the subsequently prepared tunneling oxide layer 41, the N + doped polycrystalline silicon 42 and the back passivation layer 5 are all provided with textured structures, after the negative electrode 7 is screen-printed by adopting silver paste, the silver paste is sintered at high temperature, one end of the sintered negative electrode 7 in the N + doped polycrystalline silicon 42 can form a rough texture structure 71 which is approximately same as the textured shape of the back passivation layer 5, the negative electrode 7 forms ohmic contact with the N + doped polycrystalline silicon 42 through the rough texture structure 71, the contact area of the negative electrode 7 and the N + doped polycrystalline silicon 42 is greatly increased, and therefore, the negative electrode 7 and the N + doped polycrystalline silicon 42 form good ohmic contact, and the battery efficiency is improved.
In the embodiment of the invention, the weight of the silicon wafer subjected to the first texturing is controlled to be 0.1g-0.3g, and the reflectivity is controlled to be 8% -12%, so that the subsequent preparation of the tunneling oxide layer 41 is facilitated.
As an embodiment of the present invention, step S2 specifically includes:
preparing a mask on the back of the P-type silicon wafer 1;
carrying out laser ablation etching mask at the position, corresponding to the position where the negative electrode 7 is prepared, on the back surface of the P-type silicon wafer 1 to expose the P-type silicon wafer 1;
texturing is carried out in a laser ablation area on the back of the P-type silicon wafer 1 to form a textured structure 10, and a mask of a non-laser ablation area is removed through acid washing.
As an embodiment of the invention, a silicon oxide mask is deposited by PECVD, and the thickness of the mask is controlled to be 80-200 nm.
In the embodiment, a mask is firstly prepared on the back surface of the P-type silicon wafer 1 to protect the non-laser ablation region, so that the non-laser ablation region keeps a polished surface, and the first texturing process is ensured to be carried out only on the position, corresponding to the position for preparing the negative electrode 7, on the back surface of the P-type silicon wafer 1. And simultaneously, after the texturing is finished, removing the mask on the back surface of the silicon wafer by using an acidic solution. Wherein the mask is a silicon oxide mask. The acidic solution may specifically be HF.
Step S3, preparing a tunneling oxide layer 41: preparing a tunneling oxide layer 41 on the back of the P-type silicon wafer 1;
in the step, the tunneling oxide layer 41 is prepared on the back surface of the P-type silicon wafer 1, and the back surface of the silicon wafer is passivated by using the tunneling oxide layer 41, so that the passivation capability of the battery is improved. Specifically, the tunneling oxide layer 41 may be prepared by oxidizing the surface of the P-type silicon wafer 1 by using a wet method or a thermal oxidation technique.
As an embodiment of the present invention, the thickness of the tunnel oxide layer 41 is controlled to be 1-5 nm. The tunnel oxide layer 41 is specifically a silicon oxide layer.
Step S4, preparing N + doped polysilicon 42: preparing N + doped polysilicon 42 on the back of the P-type silicon wafer 1;
as a preferred embodiment of the present invention, the N + doped polysilicon 42 is obtained by a deposition process.
As an embodiment of the present invention, the thickness of the N + doped polysilicon 42 is controlled to be 50-350 nm.
As an embodiment of the invention, the sheet resistance of the N + doped polysilicon 42 is controlled to be 50-200 Ω/sqr, so that the subsequently prepared negative electrode 7 and the N + doped polysilicon 42 can form good ohmic contact.
As an embodiment of the present invention, step S4 specifically includes:
depositing N + doped amorphous silicon on the back of the P-type silicon wafer 1, and crystallizing the N + doped amorphous silicon into N + doped polycrystalline silicon 42 at high temperature; or the like, or, alternatively,
intrinsic amorphous silicon is deposited on the back of the P-type silicon wafer 1, phosphorus diffusion is carried out on the intrinsic amorphous silicon to obtain N + doped amorphous silicon, and meanwhile the N + doped amorphous silicon is crystallized into N + doped polycrystalline silicon 42 at high temperature.
In this embodiment, the N + doped polysilicon 42 may be prepared by depositing N + doped amorphous silicon directly on the back surface of the P-type silicon wafer 1 by LPCVD or PECVD, and then annealing the silicon wafer at a high temperature to crystallize the N + doped amorphous silicon into the N + doped polysilicon 42 at a high temperature. Or, firstly depositing intrinsic amorphous silicon on the back surface of the P-type silicon wafer 1 by LPCVD or PECVD, then performing a phosphorus diffusion process on the intrinsic amorphous silicon to obtain N + doped amorphous silicon, and then performing high-temperature annealing on the silicon wafer to crystallize the N + doped amorphous silicon into N + doped polysilicon 42 at high temperature.
Step S5, second texturing: texturing is carried out on the front side of the P-type silicon wafer 1 to form a textured surface;
in the embodiment of the invention, the front side of the P-type silicon wafer 1 is textured to form a textured surface so as to reduce the reflection of the front side of the silicon wafer to sunlight.
In the embodiment of the invention, the weight of the silicon wafer subjected to the second texturing is controlled to be 0.2-0.5 g, and the reflectivity is controlled to be 8-12%.
As an embodiment of the present invention, the second texturing step further includes:
and texturing at the position of the back of the P-type silicon wafer 1 corresponding to the position for preparing the positive electrode 6 to form a textured surface.
In the embodiment, the positive electrode 6 is printed and sintered to form ohmic contact with the textured surface on the back surface of the P-type silicon wafer 1, so that the ohmic contact effect of the positive electrode 6 and the P-type silicon wafer 1 can be improved; and the back passivation layer 5 covering the P + doped region 3 can be more stably attached to the P + doped region 3, thereby achieving a good passivation effect.
As an embodiment of the invention, before the second texturing step, grooving is further performed on the back surface of the P-type silicon wafer 1 at a position corresponding to the position where the positive electrode 6 is prepared to form the groove 11. Wherein the number of the grooves 11 is equal to the number of the P + doped regions 3. The grooves 11 may be grooved before the polishing step or may be performed before any step prior to the second texturing step.
The bottom of the groove 11 is used for arranging the P + doped region 3, so that the P + doped region 3 is separated from the N + doped region 4 through the groove 11, the P + doped region 3 is prevented from being in contact with the N + doped region 4, and the safety performance and the efficiency of the battery are improved. The position for preparing the positive electrode 6 is the bottom of the groove 11, and the bottom of the groove 11 is subjected to texturing to form a textured surface, so that the positive electrode 6 is printed and sintered to form ohmic contact with the textured surface.
As an embodiment of the present invention, the width of the groove 11 is controlled to be 300-600um, the depth of the groove 11 is controlled to be 0.3-10um, and the distance between adjacent grooves 11 is 20-500um, so that the P + doping region 3 and the N + doping region 4 can be well isolated, and the processing of the groove 11 is facilitated.
As an embodiment of the present invention, the second texturing step specifically includes:
preparing a mask on the back of the P-type silicon wafer 1;
performing laser local ablation etching mask on the correspondingly prepared positive electrode on the back surface of the P-type silicon wafer 1 to expose the P-type silicon wafer 1;
texturing is carried out on the laser ablation areas on the front side of the P-type silicon wafer 1 and the back side of the P-type silicon wafer to form a textured surface, and the mask of the non-laser ablation area is removed through acid washing.
Specifically, in the second texturing process, the laser ablation area on the back of the P-type silicon wafer 1 is located at the bottom of the groove 11, that is, the mask is removed by laser ablation at the bottom of the groove 11, so that texturing is performed in the laser ablation area, and the positive electrode 6 is conveniently printed on the texturing surface at the bottom of the groove 11.
In this embodiment, a mask is prepared on the back surface of the P-type silicon wafer 1 to protect the non-secondary texturing region, so that it is ensured that the secondary texturing process is performed only on the laser ablation regions on the front surface and the back surface of the P-type silicon wafer 1. And after the second texturing process is finished, forming textured surfaces in the laser ablation areas on the front surface and the back surface of the P-type silicon wafer 1. And simultaneously, after the texturing is finished, removing the mask on the back surface of the silicon wafer by using an acidic solution. Wherein the mask is a silicon oxide mask. The acidic solution may specifically be HF.
Step S6, preparing a passivated antireflection layer 2 and a back passivation layer 5: preparing a passivated antireflection layer 2 on the front side of a P-type silicon wafer 1, and preparing a back passivation layer 5 on the back side of the P-type silicon wafer 1;
in the embodiment of the invention, the passivated antireflection layer 2 is prepared on the front surface of the P-type silicon wafer 1, so that the surface recombination of the silicon wafer is reduced, and the reflection of sunlight is reduced.
As an embodiment of the invention, the thickness of the passivated anti-reflective layer 2 is controlled between 80 and 150 nm.
As an embodiment of the invention, the thickness of the back passivation layer 5 is controlled to be 60-150nm, and the refractive index is controlled to be 2-2.5, so that the back of the silicon wafer can be passivated well, and the absorption and utilization of the silicon wafer to light are increased.
Step S7, laser grooving: performing laser grooving on the back of the P-type silicon wafer 1 at a position corresponding to the position where the positive electrode 6 is prepared to expose the P-type silicon wafer 1;
in the step, laser grooving is carried out at the position, corresponding to the position where the positive electrode 6 is prepared, of the back of the P-type silicon wafer 1, and the back passivation layer 5 is etched by using laser to expose the back of the P-type silicon wafer 1, so that the aluminum paste printed at the laser grooving position can form ohmic contact with the P-type silicon wafer 1. Wherein, the grooving width of the laser grooving is 28-45 um.
Step S8, printing and sintering the positive electrode and the negative electrode: printing a negative electrode 7 at the first texturing position on the back surface of the P-type silicon wafer 1 by using silver paste, printing a positive electrode 6 at the laser grooving position on the back surface of the P-type silicon wafer 1 by using aluminum paste, sintering and drying to form a P + doping area 3 between the positive electrode 6 and the P-type silicon wafer 1, and forming a rough texture structure 71 which forms ohmic contact with the N + doping polycrystalline silicon 42 by using the negative electrode 7.
In the step, the negative electrode 7 is screen-printed at the first texturing position of the back passivation layer 5 corresponding to the back of the P-type silicon wafer 1 through the silver paste, as the textured structure 10 is formed by texturing at the position of the back of the P-type silicon wafer 1 corresponding to the position where the negative electrode 7 is prepared, the tunneling oxide layer 41, the N + doped polycrystalline silicon 42 and the back passivation layer 5 corresponding to the back textured position of the P-type silicon wafer 1 are all provided with textured structures, after the negative electrode 7 is screen-printed on the back passivation layer 5 through the silver paste, the silver paste is sintered at high temperature, the sintered negative electrode 7 can form a rough texture structure 71 inside the N + doped polycrystalline silicon 42, and the rough texture structure can be irregular sawtooth-shaped textures, hemispherical textures or pyramid-shaped textures. The negative electrode 7 forms ohmic contact with the N + doped polycrystalline silicon 42 through the rough texture structure 71, so that the contact area of the negative electrode 7 and the N + doped polycrystalline silicon 42 is greatly increased, good ohmic contact is formed between the negative electrode 7 and the N + doped polycrystalline silicon 42, and the efficiency of the battery is improved.
In this step, when the aluminum paste for printing the positive electrode 6 is sintered at a high temperature, aluminum atoms in the aluminum paste can be blended into the P-type silicon wafer 1 according to a certain proportion for doping, so as to form an aluminum-doped P + doping region 3 on the P-type silicon wafer 1, which can reduce the recombination of carriers on the back of the cell, increase the open-circuit voltage, and improve the photoelectric conversion efficiency of the P-type back contact crystalline silicon solar cell.
As an embodiment of the present invention, the sintering temperature is 300-.
According to the preparation method of the P-type back contact type crystalline silicon solar cell, provided by the embodiment of the invention, the one-step texturing process is added before the tunneling oxide layer is prepared, so that the textured structures are formed on the positions, corresponding to the negative electrode, of the back surface, the tunneling oxide layer, the N + doped polycrystalline silicon and the back surface passivation layer of the P-type back contact type crystalline silicon solar cell, of the P-type silicon wafer, and thus the negative electrode after printing and sintering can form a rough texture structure, the negative electrode can form good ohmic contact with the N + doped polycrystalline silicon by utilizing the rough texture structure, the cell efficiency is improved, the realization process is simple, and the realization cost is low.
EXAMPLE III
The embodiment of the invention also provides a solar cell module, which comprises the P-type back contact crystalline silicon solar cell of the first embodiment.
In this embodiment, the solar module is through setting up the P type back contact formula brilliant silicon solar cell of above-mentioned embodiment one, and the negative electrode of P type back contact formula brilliant silicon solar cell forms ohmic contact through coarse texture and N + doping polycrystalline silicon, has increased the area of contact of negative electrode and N + doping polycrystalline silicon to make negative electrode and N + doping polycrystalline silicon form good ohmic contact, promote battery efficiency, thereby can promote solar module's generating efficiency.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (17)

1. A P-type back contact crystalline silicon solar cell is characterized by comprising a P-type silicon wafer, wherein a passivation antireflection layer is arranged on the front surface of the P-type silicon wafer;
the back surface of the P-type silicon wafer is provided with a P + doped region, an N + doped region, a back passivation layer, a positive electrode and a negative electrode, the P + doped region and the N + doped region are alternately distributed at intervals, and the back passivation layer covers the P + doped region and the N + doped region;
the N + doped region comprises a tunneling oxide layer arranged on the back surface of the P-type silicon wafer and N + doped polycrystalline silicon arranged on the tunneling oxide layer, the positive electrode and the P + doped region form ohmic contact, and the negative electrode and the N + doped polycrystalline silicon form ohmic contact; the back surface of the P-type silicon wafer is provided with a textured structure corresponding to the negative electrode, and the negative electrode is provided with a rough texture structure which forms ohmic contact with the N + doped polycrystalline silicon and corresponds to the textured structure.
2. The P-type back-contact crystalline silicon solar cell of claim 1, wherein the width of the textured structure is 80-200 um.
3. The P-type back-contact crystalline silicon solar cell of claim 1, wherein the sheet resistance of the N + doped polysilicon is 50-200 Ω/sqr.
4. The P-type back-contact crystalline silicon solar cell as claimed in claim 1, wherein grooves corresponding to the number of the P + doped regions are formed on the back surface of the P-type silicon wafer, and each P + doped region is correspondingly formed at the bottom of one groove.
5. The P-type back-contact crystalline silicon solar cell of claim 4, wherein a textured surface is arranged at the bottom of the groove, the positive electrode is arranged on the textured surface, and the back passivation layer covers the textured surface.
6. The P-type back-contact crystalline silicon solar cell as claimed in claim 4 or 5, wherein the width of the groove is 300-600um, the depth of the groove is 0.3-10um, and the distance between two adjacent grooves is 20-500 um.
7. The P-type back-contact crystalline silicon solar cell of claim 1, wherein the tunneling oxide layer has a thickness of 1-5 nm.
8. The P-type back-contact crystalline silicon solar cell of claim 1, wherein the passivated antireflection layer and the back passivation layer are respectively one or more combinations of an aluminum oxide film, a silicon nitride film and a silicon oxynitride film.
9. A preparation method of a P-type back contact crystalline silicon solar cell is characterized by comprising the following steps:
polishing: selecting a P-type silicon wafer, and polishing the P-type silicon wafer;
first texturing: texturing at a position, corresponding to the position where the negative electrode is prepared, on the back surface of the P-type silicon wafer to form a textured structure;
preparing a tunneling oxide layer: preparing a tunneling oxide layer on the back of the P-type silicon wafer;
preparing N + doped polysilicon: preparing N + doped polysilicon on the back of the P-type silicon wafer;
and (3) second texturing: texturing is carried out on the front side of the P-type silicon wafer to form a textured surface;
preparing a passivated antireflection layer and a back passivation layer: preparing a passivated antireflection layer on the front side of the P-type silicon wafer, and preparing a back passivation layer on the back side of the P-type silicon wafer;
laser grooving: performing laser grooving on the back of the P-type silicon wafer at a position corresponding to the position where the positive electrode is prepared so as to expose the P-type silicon wafer;
printing and sintering positive and negative electrodes: printing a negative electrode at the first texturing position on the back surface of the P-type silicon wafer by using silver slurry, printing a positive electrode at the laser grooving position on the back surface of the P-type silicon wafer by using aluminum slurry, sintering and drying to form a P + doping area between the positive electrode and the P-type silicon wafer, and forming a rough texture structure which forms ohmic contact with the N + doping polycrystalline silicon by using the negative electrode.
10. The method for preparing a P-type back contact crystalline silicon solar cell according to claim 9, wherein the polishing treatment of the P-type silicon wafer specifically comprises:
and (3) polishing the P-type silicon wafer by using an alkali solution with the concentration of 1.5-15%, wherein the reflectivity of the polished P-type silicon wafer is controlled to be 38% -45%.
11. The method for preparing a P-type back-contact crystalline silicon solar cell according to claim 9, wherein the first texturing step comprises:
preparing a mask on the back of the P-type silicon wafer;
carrying out laser ablation etching mask at the position of the back of the P-type silicon wafer corresponding to the prepared negative electrode so as to expose the P-type silicon wafer;
and texturing in a laser ablation area on the back of the P-type silicon wafer to form a textured structure, and removing a mask in a non-laser ablation area through acid washing.
12. The method for preparing a P-type back contact crystalline silicon solar cell as claimed in claim 9, wherein the thickness of the tunneling oxide layer is controlled to be 1-5 nm.
13. The method for preparing the P-type back contact crystalline silicon solar cell as claimed in claim 9, wherein the thickness of the N + doped polysilicon is controlled to be 50-350 nm.
14. The method for preparing a P-type back-contact crystalline silicon solar cell according to claim 9, wherein the second texturing step further comprises:
and texturing at the position, corresponding to the positive electrode, of the back of the P-type silicon wafer to form a textured surface.
15. The method for preparing a P-type back-contact crystalline silicon solar cell according to claim 14, wherein the second texturing step specifically comprises:
preparing a mask on the back of the P-type silicon wafer;
performing laser local ablation etching mask on the position, corresponding to the prepared positive electrode, on the back surface of the P-type silicon wafer to expose the P-type silicon wafer;
texturing is carried out on the laser ablation areas on the front side and the back side of the P-type silicon wafer to form a textured surface, and the mask of the non-laser ablation area is removed through acid washing.
16. The method for preparing a P-type back-contact crystalline silicon solar cell according to claim 9, wherein the step of preparing N + doped polysilicon specifically comprises:
depositing N + doped amorphous silicon on the back of the P-type silicon wafer, and crystallizing the N + doped amorphous silicon into N + doped polycrystalline silicon at high temperature; or the like, or, alternatively,
depositing intrinsic amorphous silicon on the back of the P-type silicon wafer, carrying out phosphorus diffusion on the intrinsic amorphous silicon to obtain N + doped amorphous silicon, and crystallizing the N + doped amorphous silicon into N + doped polycrystalline silicon at high temperature.
17. A solar cell module comprising the P-type back-contact crystalline silicon solar cell according to any one of claims 1 to 8.
CN202110627504.6A 2021-06-04 2021-06-04 P-type back contact type crystalline silicon solar cell, preparation method and cell assembly Pending CN113345970A (en)

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