CN113345837A - Display panel and manufacturing method thereof - Google Patents
Display panel and manufacturing method thereof Download PDFInfo
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- CN113345837A CN113345837A CN202110578491.8A CN202110578491A CN113345837A CN 113345837 A CN113345837 A CN 113345837A CN 202110578491 A CN202110578491 A CN 202110578491A CN 113345837 A CN113345837 A CN 113345837A
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- 239000001301 oxygen Substances 0.000 claims abstract description 43
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 39
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 28
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 21
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 18
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
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- PQQKPALAQIIWST-UHFFFAOYSA-N oxomolybdenum Chemical compound [Mo]=O PQQKPALAQIIWST-UHFFFAOYSA-N 0.000 claims description 4
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- 229910004205 SiNX Inorganic materials 0.000 description 2
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- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- CWYNVVGOOAEACU-UHFFFAOYSA-N Fe2+ Chemical compound [Fe+2] CWYNVVGOOAEACU-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Abstract
The invention provides a manufacturing method of a display panel and the display panel, which do not increase the manufacturing process of a shading layer additionally, and can save a mask as a metal layer of a source electrode and a drain electrode is used as the shading layer at the same time. The active layer is connected with the source electrode, the drain electrode and the shading layer through the through holes, is a semiconductor layer, and is provided with a first grid insulating layer and a grid layer. And forming a metal film on the non-channel region active layer and the gate layer, wherein the metal film is oxidized into a compact metal oxide serving as a water-oxygen barrier layer by taking oxygen in the non-channel region active layer through a thermal oxidation process, the water-oxygen barrier layer can isolate the influence of the water and the oxygen on the thin film transistor, and meanwhile, the oxygen lost from the non-channel region active layer is converted into a conductor layer by a conductor in the thermal oxidation process, so that the conduction of the non-channel region active layer, the source and drain electrodes and the shading layer can be realized.
Description
Technical Field
The invention relates to the technical field of display, in particular to a manufacturing method of a display panel and the display panel.
Background
The Mini/MicroLED (MLED) display technology enters an accelerated development stage in the last two years and can be used in the application field of small and medium-sized high-added-value displays. Compared to OLED screens, MLED displays can exhibit better performance in terms of cost, contrast, high brightness, and thin profile. At present, the Mini-LED Top gate _ TFT back panel technology is a 9mask technology generally, the cost of the back panel is greatly increased, the mass production of the Micro-LED display technology is not facilitated, on the other hand, the current required by an LED chip is high, the total current of a panel is generally 3-8A, correspondingly, the voltage on a metal wire is also relatively high, and the development of a high-reliability high-mobility novel back panel is imperative for reducing the power consumption of the metal wire.
As liquid crystal display devices and OLED display devices are developed toward large size and high resolution, conventional a-Si has only 1cm2However, the mobility of the material around Vs has not been satisfactory, and a metal oxide material represented by Indium Gallium Zinc Oxide (IGZO) has a mobility of more than 10cm2The mobility of Vs or more and the compatibility of the production of the corresponding thin film transistor with the conventional production line using a-Si as a semiconductor driver are excellent, and the importance of the development of the display field is rapidly becoming important in recent years.
How to reduce the number of mask plates in an etching process in the preparation of a metal oxide thin film transistor is rapidly becoming a key point of research and development in the display field in recent years.
Disclosure of Invention
The invention aims to provide a manufacturing method of a display panel and the display panel, wherein a metal layer serving as a source electrode and a drain electrode simultaneously serves as a light shielding layer, and the number of mask plates can be reduced.
In one aspect, the present invention provides a method for manufacturing a display panel, including:
providing a substrate;
forming a patterned metal layer on the substrate, wherein the metal layer comprises a source electrode, a drain electrode and a light shielding layer;
forming a buffer layer covering the metal layer on the substrate, wherein the buffer layer is provided with a through hole exposing the metal layer;
forming an active layer on the buffer layer and in the via hole, wherein the active layer is connected with the metal layer through the via hole and is a semiconductor layer;
sequentially forming a first gate insulating layer and a gate electrode layer on the active layer, wherein the active layer comprises a channel region active layer and other non-channel region active layers, and the channel region active layer is in contact with the first gate insulating layer;
forming a metal film covering the non-channel region active layer and the gate electrode layer;
and carrying out a thermal oxidation process on the metal film to form a water-oxygen barrier layer, and simultaneously enabling the non-channel region active layer to be conducted into a conductor layer.
Further preferably, the step of sequentially forming a first gate insulating layer and a gate layer on the active layer includes:
sequentially depositing a gate insulating material and a metal material on the active layer;
patterning the metal material to form the gate layer;
and etching the gate insulating material by using the gate layer to perform a self-aligned process to form the first gate insulating layer.
Further preferably, the gate layer includes a barrier layer on the first gate insulating layer, an electrode layer on the barrier layer, and an antireflection layer on the electrode layer.
Further preferably, the material of the barrier layer includes molybdenum, the material of the electrode layer includes copper, and the material of the anti-reflection layer includes molybdenum oxide.
Further preferably, the method further comprises the following steps:
forming a first passivation layer on the water and oxygen barrier layer, wherein the first passivation layer is formed with an opening exposing the non-channel region active layer;
forming an electrode layer and a chip binding pad in sequence on the inner wall of the opening, wherein the electrode layer and the chip binding pad cover part of the upper surface of the first passivation layer;
depositing a passivation material and a color resistance material on the first passivation layer in sequence;
patterning the color resistance material to form a color resistance layer;
and etching the passivation material by utilizing the color resistance layer to perform a self-alignment process to form a second passivation layer, wherein the second passivation layer is positioned between the color resistance layer and the chip binding pad.
In another aspect, the present invention provides a display panel including:
a substrate;
a patterned metal layer on the substrate, the metal layer including a source, a drain, and a light-shielding layer;
a buffer layer on the substrate and covering the metal layer, the buffer layer having a via hole exposing the metal layer;
an active layer on the buffer layer and within the via, the active layer being connected to the metal layer through the via;
the first grid electrode insulating layer is positioned on the active layer, the active layer comprises a channel region active layer and other non-channel region active layers, the channel region active layer is in contact with the first grid electrode insulating layer, the channel region active layer is a semiconductor layer, and the non-channel region active layers are conductor layers;
a gate electrode layer on the first gate insulating layer;
and a water and oxygen barrier layer covering the non-channel region active layer and the gate electrode layer.
Further preferably, the gate layer includes a barrier layer on the first gate insulating layer, an electrode layer on the barrier layer, and an antireflection layer on the electrode layer.
Further preferably, the material of the barrier layer includes molybdenum, the material of the electrode layer includes copper, and the material of the anti-reflection layer includes molybdenum oxide.
Further preferably, the method further comprises the following steps:
a first passivation layer covering the water oxygen blocking layer, the first passivation layer having a first opening exposing the non-channel region active layer;
the electrode layer and the chip binding pad are sequentially positioned on the inner wall of the first opening, and the electrode layer and the chip binding pad cover part of the upper surface of the first passivation layer;
a second passivation layer on the first passivation layer;
and the second passivation layer is positioned between the color resistance layer and the chip binding pad.
Further preferably, the method further comprises the following steps:
a second gate insulating layer on the buffer layer;
the gate layer is positioned on the second gate insulating layer;
the water-oxygen barrier layer covering the gate layer;
a first passivation layer covering the water oxygen barrier layer, the first passivation layer having a second opening over the second gate insulating layer to expose the electrode layer in the gate layer;
and the peripheral bonding pad is positioned on the inner wall of the second opening.
The invention has the beneficial effects that: the manufacturing method of the display panel and the display panel are provided, a patterned metal layer is formed on a substrate to form a source electrode, a drain electrode and a light shielding layer at the same time, so that a mask plate does not need to be used independently to form the light shielding layer, and the mask plate can be saved. And then forming a buffer layer and an active layer, wherein the active layer is connected with the source electrode, the drain electrode and the shading layer through the through holes, and the active layer is a semiconductor layer. Next, a first gate insulating layer and a gate electrode layer are formed on the active layer, which includes a channel region active layer in contact with the first gate insulating layer and other non-channel region active layers. And forming a metal film on the non-channel region active layer and the gate layer, wherein the metal film is oxidized into a compact metal oxide serving as a water-oxygen barrier layer by taking oxygen in the non-channel region active layer through a thermal oxidation process, the water-oxygen barrier layer can isolate the influence of the water and the oxygen on the thin film transistor, and meanwhile, the oxygen lost from the non-channel region active layer is converted into a conductor layer by a conductor in the thermal oxidation process, so that the conduction of the non-channel region active layer, the source and drain electrodes and the shading layer can be realized.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a display panel according to an embodiment of the present invention;
fig. 2a-2h are schematic structural diagrams of a display panel provided in an embodiment of the invention in a manufacturing process;
fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a display panel according to another embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a manufacturing method of a display panel according to an embodiment of the invention. Referring to fig. 2a-2h, fig. 2a-2h are schematic structural diagrams of a display panel according to an embodiment of the invention in a manufacturing process. The manufacturing method of the display panel comprises the following steps S1-S9.
Please first refer to steps S1-S2 in fig. 1 and fig. 2 a.
Step S1: a substrate 10 is provided.
Step S2: a patterned metal layer 11 is formed on the substrate 10, and the metal layer 11 includes a source electrode 111, a drain electrode 112, and a light-shielding layer 113.
In this embodiment, a metal material, which may be Mo, Al/Mo, Mo/Cu, IZO, Cu/IZO, Mo/Cu/ITO, Ni/Cu/Ni, MoTiNi/Cu/MoTiNi, NiCr/Cu/NiCr, or CuNb, is first deposited on the substrate 10 by physical vapor deposition, and then a mask is used to pattern the metal material film, a hydrogen peroxide chemical solution may be used as an etchant to etch the metal material film to obtain the patterned first metal layer 11, where the first metal layer 11 includes the source 111, the drain 112, and the light-shielding layer 113, and therefore the source 111, the drain 112, and the light-shielding layer 113 are etched by using the same mask without adding a light-shielding layer process. The source 111 may be a drain, and the drain 112 may be a source.
Please refer to step S3 in fig. 1 and fig. 2 b.
Step S3: forming a buffer layer 12 on the substrate 10 to cover the metal layer 11, wherein a via hole 121 exposing the metal layer 11 is formed in the buffer layer 12.
In this embodiment, the buffer layer 12 may be formed by chemical vapor deposition, the film may be a laminated structure of SiOx or SiNx/SiOx, and then high temperature annealing is performed for 2-3 hours at a temperature of 300-.
Please refer to step S4 in fig. 1 and fig. 2 c.
Step S4: an active layer 13 is formed on the buffer layer 12 and in the via hole 121, the active layer 13 is connected to the metal layer 11 through the via hole 121, and the active layer 13 is a semiconductor layer.
In this embodiment, semiconductor metal oxides such as IGZO, IGZTO, and IGTO may be deposited first, and the active layer 13 may be formed by patterning, where the active layer 13 is connected to the metal layer 11 through the via hole 121, that is, connected to the source electrode 111, the drain electrode 112, and the light shielding layer 113.
Please refer to step S5 in fig. 1 and fig. 2 d.
Step S5: a first gate insulating layer 14 and a gate electrode layer 15 are sequentially formed on the active layer 13, and the active layer 13 includes a channel region active layer 131 and other non-channel region active layers 132 in contact with the first gate insulating layer 14.
In this embodiment, the step S5 may include: 1) sequentially depositing a gate insulating material and a metal material on the active layer 13; 2) patterning the metal material to form the gate layer 15; 3) the gate insulating material is etched by using the gate electrode layer 15 to perform a self-aligned process, so that the first gate insulating layer 14 is formed, and therefore, the first gate insulating layer 14 and the gate electrode layer 15 only need to be formed by etching through a mask plate. Further, the active layer 13 includes a channel region active layer 131 contacting the first gate insulating layer 14 and a non-channel region active layer 132 at other positions, that is, the active layer 13 under the first gate insulating layer 14 is the channel region active layer 131, and the non-channel region active layer 132 is disposed except the channel region active layer 131.
Preferably, the gate layer 15 may include a barrier layer on the first gate insulating layer 14, an electrode layer on the barrier layer, and an anti-reflection layer on the electrode layer, and the gate layer 15 adopts a low-reflection film structure, which may reduce the influence of scattering light reflected again into the channel through the gate layer 15 on the device stability. For example, a Mo/Cu/MoOx antireflection structure can be used, wherein MoOx is used as an antireflection layer for reducing light reflection, and the thickness can be smaller
Cu as an electrode layer and Mo as a barrier layer for preventing the diffusion of the metal of the electrode layer toward the first gate insulating layer 14 and affecting the first gate insulating layer 14And (4) dielectricity. The MoOx is thin and can be performed along with the etching of the Mo/Cu film, and the extra etching process is not required to be added. The antireflection layer can be made of other ferrous metal materials, and the electrode layer can also be made of other grid metal materials.
In this embodiment, in the process of performing step S5, the second gate insulating layer 14 'is also formed on the buffer layer 12, and the gate electrode layer 15 is also formed on the second gate insulating layer 14'.
Please refer to steps S6-S7 in fig. 1 and fig. 2 e.
Step S6: a metal film is formed covering the non-channel region active layer 132 and the gate layer 15.
Step S7: the metal thin film is subjected to a thermal oxidation process to form a water oxygen barrier layer 16 while the non-channel region active layer 132 is made conductive as a conductor layer.
In this embodiment, a thin Al film with a small thickness can be formed by physical vapor deposition
In some embodiments, other metal films may also be used. Then introducing oxygen, and performing thermal oxidation process at the temperature of 200-300 ℃ to oxidize the metal film into metal oxide (Al)2O3) To form a water oxygen barrier 16. In some embodiments, the thermal oxidation process may be performed without introducing oxygen, which may accelerate the oxidation of the metal film. Since the metal thin film is in contact with the non-channel region active layer 132, the metal thin film will deprive oxygen from the non-channel region active layer 132 during the oxidation reaction, and certainly will also take oxygen from the introduced oxygen, so that the non-channel region active layer 132 loses oxygen and becomes a conductor layer, and can be used as a conductive line to achieve conduction with the source electrode 111, the drain electrode 112 and the light shielding layer 113. Since the channel region active layer 131 is not in contact with the metal thin film, it is not transformed into a conductor during the thermal oxidation process. The water-oxygen barrier layer 16 formed by thermal oxidation can isolate the influence of water and oxygen on the thin film transistor, and the process cost of depositing metal film and thermal oxidation is low, and the thermal oxidation process can form narrow channelA TFT.
Wherein, the reflectivity is Al2O3/MoOx/Cu：MoOx/Cu＝4.5％:5.8％，Al2O3The film layer may further reduce the reflectivity.
Please refer to step S8 in fig. 1 and fig. 2 f.
Step S8: a first passivation layer 17 is formed on the water and oxygen blocking layer 16, and the first passivation layer 17 is formed with a first opening 171 exposing the non-channel region active layer 132.
In this embodiment, a passivation material, which may be SiOx or a SiOx/SiNx stack, may be deposited by using a chemical vapor deposition process, and then patterned to form the first passivation layer 17. The left side of the substrate 10 is a thin film transistor region (TFT region), the middle first opening 171 is a chip bonding region, and the right side of the second gate insulating layer 14' is a peripheral bonding region (Pad region). To ensure good contact, the TFT region etches the water-oxygen barrier layer 16 over the non-channel region active layer 132 along with the passivation material to form a first opening 171 exposing the non-channel region active layer 132.
In step S8, when the gate layer 15 is a barrier/electrode/anti-reflective coating tri-layer anti-reflective structure, a second opening 172 is formed above the second gate insulating layer 14' to expose the electrode layer in the gate layer 15. Specifically, the anti-reflection layer, the water-oxygen barrier layer 16 and the passivation material above the Pad region electrode layer are etched together to form a second opening 172 exposing the electrode layer. When the gate layer 15 is a single-layer metal structure, the Pad region etches the water-oxygen barrier layer 16 and the passivation material together above the gate layer 15 to form a second opening 172 exposing the gate layer 15.
Please refer to step S9 in fig. 1 and fig. 2 g.
Step S9: an electrode layer 18 and a chip bonding pad 19 are sequentially formed on the inner wall of the first opening 171, and the electrode layer 18 and the chip bonding pad 19 cover a portion of the upper surface of the first passivation layer 17.
In the present embodiment, an Indium Tin Oxide (ITO) layer is first physically vapor deposited and patterned to form the electrode layer 18 as an electrode of a subsequent LED chip. During the step S9, ITO is deposited on the inner wall of the second opening 172 to form an oxidation protection layer 18 ', and the oxidation protection layer 18' can prevent the metal of the gate layer 15 in the peripheral bonding region (Pad region) from being oxidized.
The manufacturing method of the display panel further comprises the steps of 1) sequentially depositing a passivation material and a color resistance material on the first passivation layer 17; 2) patterning the color resistance material to form a color resistance layer 21; 3) and etching the passivation material by using the color resistance layer 21 through a self-alignment process to form a second passivation layer 20, wherein the second passivation layer 20 is positioned between the color resistance layer 21 and the chip bonding pad 19. The second passivation layer 20 is used to separate the chip bonding pad 19 and the color resist layer 21, the color resist layer 21 may also be replaced with a black matrix as an LED light shielding layer, in this step, the color resist layer 21 is used as a mask to complete patterning of the second passivation layer 20, only one mask is needed, and the completed structure is shown in fig. 2 h.
The manufacturing method of the display panel further comprises the following processes of solder paste printing, LED chip bulk transfer and the like, the whole process of the Mini-LED or the Micro-LED is completed, and the LED chip is bound on the chip binding bonding pad 19.
In the manufacturing method of the display panel provided by this embodiment, the source electrode 111, the drain electrode 112, and the light-shielding layer 113 are simultaneously formed by using one mask, so that a separate light-shielding layer is not required, and one mask can be saved. Depositing a metal film and forming a water and oxygen barrier layer 16 by using a thermal oxidation process to protect the thin film transistor from external water and oxygen, wherein the thermal oxidation process can simultaneously realize the conductor formation of the non-channel region active layer 132, thereby realizing the conduction of the non-channel region active layer 132 with the source/drain and the light shielding layer 113, and the thermal oxidation process has low cost. The gate layer 15 adopts a three-layer low-reflection film structure, so that the influence on the stability of the device caused by the fact that scattered light is reflected again to enter a channel through the gate layer 15 can be reduced, and the reflectivity can be further reduced by the water-oxygen barrier layer 16 positioned on the gate layer 15. In addition, in the three-layer anti-reflection structure of the barrier layer/the electrode layer/the anti-reflection layer, the thinner anti-reflection layer can be etched along with the barrier layer and the electrode layer, and extra etching processes are not required to be added.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and the display panel 100 may be formed by the above-mentioned manufacturing method, so that the above-mentioned reference numerals are used again in this embodiment. The display panel 100 includes: a substrate 10; a patterned metal layer 11 on the substrate 10, the metal layer 11 including a source electrode 111, a drain electrode 112, and a light-shielding layer 113; a buffer layer 12 on the substrate 10 and covering the metal layer 11, the buffer layer 12 having a via 121 exposing the metal layer 11; an active layer 13 on the buffer layer 12 and within the via 121, the active layer 13 being connected to the metal layer 11 through the via 121; a first gate insulating layer 14 on the active layer 13, wherein the active layer 13 includes a channel region active layer 131 and other non-channel region active layers 132 in contact with the first gate insulating layer 14, the channel region active layer 131 is a semiconductor layer, and the non-channel region active layers 132 are conductor layers; a gate electrode layer 15 on the first gate insulating layer 14; a water-oxygen barrier layer 16 covering the non-channel region active layer 132 and the gate layer 15.
Further, the display panel 100 further includes: a first passivation layer 17 covering the water and oxygen barrier layer 16, the first passivation layer 17 having a first opening 171 exposing the non-channel region active layer 132; an electrode layer 18 and a chip bonding pad 19 sequentially positioned on an inner wall of the first opening 171, wherein the electrode layer 18 and the chip bonding pad 19 cover a portion of an upper surface of the first passivation layer 17; a second passivation layer 20 on the first passivation layer 17; a color resist layer 21 on the second passivation layer 20, the second passivation layer 20 being between the color resist layer 21 and the chip bonding pad 19; and an LED chip 22 bonded on the chip bonding pad 19.
Further, the display panel 100 further includes: a second gate insulating layer 14' on the buffer layer 12; the gate electrode layer 15 on the second gate insulating layer 14'; the water-oxygen barrier layer 16 covering the gate layer 15; a first passivation layer 17 covering the water oxygen barrier layer 16, the first passivation layer 17 having a second opening 172 exposing the gate electrode layer 15 above the second gate insulating layer 14'; and an oxidation protection layer 18' located on the inner wall of the second opening 172.
Please refer to fig. 4, fig. 4 is a schematic structural diagram of a display panel according to another embodiment of the present invention, and for convenience of understanding, the same structures in this embodiment as those in the above embodiments use the same reference numerals and are not repeated herein. The display panel 200 is different from the display panel 100 described above in the gate layer 15. Specifically, the gate layer 15 includes a barrier layer 151 on the first gate insulating layer 14 or the second gate insulating layer 14', an electrode layer 152 on the barrier layer 151, and an anti-reflection layer 153 on the electrode layer 152. The gate layer 15 adopts a low-reflection film structure, so that the influence on the stability of the device caused by the fact that scattered light is reflected again by the gate metal layer and enters the channel can be reduced.
The display panels 100 and 200 provided in this embodiment have the same beneficial effects as those of the above embodiment of the manufacturing method of the display panel, and are not described herein again.
The above description of the embodiments is only for helping understanding the technical solution of the present invention and its core idea; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A method for manufacturing a display panel is characterized by comprising the following steps:
providing a substrate;
forming a patterned metal layer on the substrate, wherein the metal layer comprises a source electrode, a drain electrode and a light shielding layer;
forming a buffer layer covering the metal layer on the substrate, wherein the buffer layer is provided with a through hole exposing the metal layer;
forming an active layer on the buffer layer and in the via hole, wherein the active layer is connected with the metal layer through the via hole and is a semiconductor layer;
sequentially forming a first gate insulating layer and a gate electrode layer on the active layer, wherein the active layer comprises a channel region active layer and other non-channel region active layers, and the channel region active layer is in contact with the first gate insulating layer;
forming a metal film covering the non-channel region active layer and the gate electrode layer;
and carrying out a thermal oxidation process on the metal film to form a water-oxygen barrier layer, and simultaneously enabling the non-channel region active layer to be conducted into a conductor layer.
2. The method according to claim 1, wherein the step of sequentially forming a first gate insulating layer and a gate layer on the active layer comprises:
sequentially depositing a gate insulating material and a metal material on the active layer;
patterning the metal material to form the gate layer;
and etching the gate insulating material by using the gate layer to perform a self-aligned process to form the first gate insulating layer.
3. The method for manufacturing the display panel according to claim 1, wherein the gate layer comprises a barrier layer over the first gate insulating layer, an electrode layer over the barrier layer, and an antireflection layer over the electrode layer.
4. The method according to claim 3, wherein the barrier layer comprises molybdenum, the electrode layer comprises copper, and the anti-reflection layer comprises molybdenum oxide.
5. The method for manufacturing a display panel according to claim 1, further comprising:
forming a first passivation layer on the water and oxygen barrier layer, wherein the first passivation layer is formed with an opening exposing the non-channel region active layer;
forming an electrode layer and a chip binding pad in sequence on the inner wall of the opening, wherein the electrode layer and the chip binding pad cover part of the upper surface of the first passivation layer;
depositing a passivation material and a color resistance material on the first passivation layer in sequence;
patterning the color resistance material to form a color resistance layer;
and etching the passivation material by utilizing the color resistance layer to perform a self-alignment process to form a second passivation layer, wherein the second passivation layer is positioned between the color resistance layer and the chip binding pad.
6. A display panel, comprising:
a substrate;
a patterned metal layer on the substrate, the metal layer including a source, a drain, and a light-shielding layer;
a buffer layer on the substrate and covering the metal layer, the buffer layer having a via hole exposing the metal layer;
an active layer on the buffer layer and within the via, the active layer being connected to the metal layer through the via;
the first grid electrode insulating layer is positioned on the active layer, the active layer comprises a channel region active layer and other non-channel region active layers, the channel region active layer is in contact with the first grid electrode insulating layer, the channel region active layer is a semiconductor layer, and the non-channel region active layers are conductor layers;
a gate electrode layer on the first gate insulating layer;
and a water and oxygen barrier layer covering the non-channel region active layer and the gate electrode layer.
7. The display panel according to claim 6, wherein the gate layer comprises a barrier layer over the first gate insulating layer, an electrode layer over the barrier layer, and an antireflection layer over the electrode layer.
8. The display panel according to claim 7, wherein the material of the barrier layer comprises molybdenum, the material of the electrode layer comprises copper, and the material of the anti-reflection layer comprises molybdenum oxide.
9. The display panel according to claim 6, further comprising:
a first passivation layer covering the water oxygen blocking layer, the first passivation layer having a first opening exposing the non-channel region active layer;
the electrode layer and the chip binding pad are sequentially positioned on the inner wall of the first opening, and the electrode layer and the chip binding pad cover part of the upper surface of the first passivation layer;
a second passivation layer on the first passivation layer;
and the second passivation layer is positioned between the color resistance layer and the chip binding pad.
10. The display panel according to claim 7, further comprising:
a second gate insulating layer on the buffer layer;
the gate layer is positioned on the second gate insulating layer;
the water-oxygen barrier layer covering the gate layer;
a first passivation layer covering the water oxygen barrier layer, the first passivation layer having a second opening over the second gate insulating layer to expose the electrode layer in the gate layer;
and the peripheral bonding pad is positioned on the inner wall of the second opening.
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Application publication date: 20210903 |