CN113342730A

CN113342730A - Communication interface device, board card and data processing method for inter-board communication

Info

Publication number: CN113342730A
Application number: CN202110548365.8A
Authority: CN
Inventors: 吴忠梁
Original assignee: Zhicheauto Technology Beijing Co ltd
Current assignee: Zhicheauto Technology Beijing Co ltd
Priority date: 2021-05-19
Filing date: 2021-05-19
Publication date: 2021-09-03

Abstract

The embodiment of the invention discloses a communication interface device, a board card and a data processing method for inter-board communication, relating to the technical field of embedded systems, wherein the communication interface device comprises: the FPGA module and the connector module are arranged on the PCB; the FPGA module performs protocol conversion processing on first data received through the second communication interface and sent by other modules, generates second data matched with the first communication interface and sends the second data to the connector module through the first communication interface; the FPGA module carries out protocol conversion processing on third data received through the first communication interface and sent by the connector module, generates fourth data matched with the second communication interface and sends the fourth data to other modules through the second communication interface. The communication interface device, the board card and the data processing method can realize the normalized inter-board bus function, reduce the number of communication buses and pins of the connector, and realize the communication compatibility of various platforms.

Description

Communication interface device, board card and data processing method for inter-board communication

Technical Field

The present invention relates to the field of embedded system technologies, and in particular, to a communication interface device, a board card, and a data processing method for inter-board communication.

Background

With the rapid development of integrated circuit technology, various board cards are arranged in automobiles to realize various functions of controlling the running of the automobiles, acquiring external images, processing the images, identifying identities and the like. Connectors are provided in different boards, and compatibility between a multi-pin connector and a connector with fewer pins is poor. Along with the shortening of automobile electronic product modularization and development cycle, the suitability between different mainboards and different bottom plates is required, and connectors with multiple pin numbers are required to be arranged for different board cards. Even if the demand of the card product on the number of pins is low, a connector with multiple pin numbers still needs to be used for the continuity and compatibility of the card product. At present, when a board card product is designed, all pins of a connector need to be subjected to early-stage function planning, after the planning is completed, all the board card products need to be developed according to the regulations, and buses and levels need to be completely matched, so that the flexibility is lower; in addition, the connector with multiple pins increases the cost, is easy to have poor compatibility, and has high failure rate.

Disclosure of Invention

In view of the above, embodiments of the present invention provide a communication interface device, a board card and a data processing method for inter-board communication.

According to a first aspect of the embodiments of the present invention, there is provided a communication interface apparatus for inter-board communication, including: at least one FPGA module and a connector module arranged on the PCB; the FPGA module comprises: at least one first communication interface and at least one second communication interface; the at least one first communication interface is connected with the connector module; the at least one second communication interface is connected with other modules arranged on the PCB; the FPGA module performs protocol conversion processing on first data received through the second communication interface and sent by the other modules to generate second data matched with the first communication interface, and sends the second data to the connector module through the first communication interface; and the FPGA module performs protocol conversion processing on third data received through the first communication interface and sent by the connector module to generate fourth data matched with the second communication interface, and sends the fourth data to other modules through the second communication interface.

Optionally, the number of the first communication interfaces is two; the two first communication interfaces are respectively and correspondingly connected with the two third communication interfaces of the connector module to form two first communication channels; the two first communication channels are respectively used for transmitting the second data or receiving the third data.

Optionally, the first communication interface and the third communication interface include: and a GPIO interface.

Optionally, the number of the second communication interfaces is multiple; each second communication interface is respectively connected with the corresponding fourth communication interface of the other module to form a plurality of second communication channels; wherein the second communication channel is configured to receive the first data and to transmit the fourth data.

Optionally, the second communication interface and the fourth communication interface include: SPI interface, UART interface, GPIO interface, CAN interface, SDIO interface.

Optionally, the number of the FPGA modules is plural; the first communication interfaces of the FPGA modules are respectively connected with the connector module, and the second communication interfaces of the FPGA modules are respectively connected with the other corresponding modules.

Optionally, the other modules include: an MCU module; the at least one FPGA module includes: the FPGA module comprises a main FPGA module and a backup FPGA module; the MCU module is respectively connected with the main FPGA module and the backup FPGA module through signal lines; the MCU module is used for receiving heartbeat signals sent by the main FPGA module and the backup FPGA module, determining whether the main FPGA module and the backup FPGA module break down or not based on the heartbeat signals, and carrying out corresponding switching processing so as to enable the main FPGA module or the backup FPGA module to be in a working state.

Optionally, the FPGA module is provided with a debug JTAG interface, and the FPGA module receives a debug instruction and configuration information through the debug JTAG interface.

Optionally, a memory module is disposed on the PCB; the FPGA module is connected with the storage module; wherein the storage module comprises: DDR module and FLASH module.

According to a second aspect of the embodiments of the present invention, there is provided a board card, including: the communication interface device for the inter-board communication is described above.

According to a third aspect of the embodiments of the present invention, there is provided a data processing method based on the above communication interface device for inter-board communication, including: the FPGA module receives first data sent by the other modules through the second communication interface; the FPGA module carries out protocol conversion processing on the first data, generates second data matched with the first communication interface and sends the second data to the connector module through the first communication interface; the FPGA module receives third data sent by the connector module through the first communication interface; and the FPGA module performs protocol conversion processing on the third data to generate fourth data matched with the second communication interface, and sends the fourth data to the other modules through the second communication interface.

Optionally, the other modules include: an MCU module; the FPGA module comprises: the FPGA module comprises a main FPGA module and a backup FPGA module; the MCU module is respectively connected with the main FPGA module and the backup FPGA module through signal lines, and the method further comprises the following steps: the MCU module receives heartbeat signals sent by the main FPGA module and the backup FPGA module; if the main FPGA module is determined to be in a normal state based on the heartbeat signal, controlling the main FPGA module to be in a working state; and if the main FPGA module is determined to be in fault and the backup FPGA module is in a normal state based on the heartbeat signal, controlling the backup FPGA module to be in a working state.

The communication interface device, the board card and the data processing method for inter-board communication can realize the normalized inter-board bus function; signals of all modules in the board card are accessed through the FPGA module and are output to the connector through the high-speed GPIO port of the FPGA module, so that the number of communication buses and pins of the connector can be reduced; the level conversion device can be saved, so that the signal between the boards has no level mismatching problem; by using the same connector and using the same communication protocol, communication compatibility of a variety of platforms can be achieved.

Additional aspects and advantages of embodiments of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without inventive exercise:

FIG. 1 is a block diagram illustrating an embodiment of a communication interface device for inter-board communication according to the present invention;

FIG. 2 is a block diagram of another embodiment of a communication interface device for inter-board communication according to the present invention;

FIG. 3 is a pin diagram of the connector;

fig. 4 is a schematic block diagram illustrating board data intercommunication in an embodiment of a communication interface device for board-to-board communication according to the present invention;

FIG. 5 is a block diagram illustrating another embodiment of a communication interface device for inter-board communication according to the present invention;

FIG. 6 is a block diagram illustrating a communication interface device for inter-board communication according to yet another embodiment of the present invention;

FIG. 7 is a schematic flow chart diagram illustrating one embodiment of a data processing method in accordance with the present invention;

fig. 8 is a flow chart illustrating handover communication in an embodiment of a data processing method according to the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.

It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It will be appreciated by those skilled in the art that the terms "application," "application program," "application software," and the like, as used herein, are intended to refer to a computer software product electronically-adapted to be electronically-constructed, from a collection of computer instructions and associated data resources, in accordance with the principles of the present invention. Unless otherwise specified, such nomenclature is not itself limited by the programming language class, level, or operating system or platform upon which it depends. Of course, such concepts are not limited to any type of terminal.

In one embodiment, as shown in fig. 1, the present invention provides a communication interface device for inter-board communication, including: an FPGA (Field Programmable Gate Array) module 12 and a connector module 11 are disposed on a PCB (Printed Circuit Board) Circuit Board 10. The number of the FPGA modules 12 may be one or more, and the FPGA modules 12 include one or more first communication interfaces connected to the connector module 11 and one or more second communication interfaces connected to other modules 13 disposed on the PCB circuit board 10. The other modules may be various modules, such as an MCU module, an image processing module, an identity authentication module, and the like.

The FPGA module 12 is capable of performing a data protocol conversion process. The FPGA module 12 performs protocol conversion processing on the first data received through the second communication interface and sent by the other modules 13, generates second data matched with the first communication interface, and sends the second data to the connector module 11 through the first communication interface. The FPGA module 12 performs protocol conversion processing on the third data received through the first communication interface and sent by the connector module 11, generates fourth data matched with the second communication interface, and sends the fourth data to the other modules 13 through the second communication interface. The first data and the third data may be control signal data, image data, radar signal data, or the like.

For example, the FPGA module 12 performs protocol conversion processing on first data received through the SPI interface and sent by the other modules 13, generates second data matched with the GPIO interface, and sends the second data to the connector module 11 through the GPIO interface. The FPGA module 12 performs protocol conversion processing on the third data received through the GPIO interface and sent by the connector module 11, generates fourth data matched with the UART interface, and sends the fourth data to the other modules 13 through the UART interface.

As shown in fig. 2, the number of the first communication interfaces of the FPGA module 12 is two, the two first communication interfaces are correspondingly connected to the two third communication interfaces of the connector module 11, respectively, to form two first communication channels, and the two first communication channels are a TX (Transmitter) communication channel and an RX (Receiver) communication channel, respectively. The two first communication channels are respectively used for sending second data or receiving third data, and the first communication interface and the third communication interface comprise a General Purpose Input/Output (GPIO) interface and the like.

The number of the second communication interfaces of the FPGA module 12 is plural, and each second communication interface is connected to the fourth communication interface of the corresponding other module, so as to form a plurality of second communication channels. The other modules may be the first module 131 and the second module 132, the second communication channel is configured to receive the first data and send fourth data, and the second communication Interface and the fourth communication Interface include an SPI (Serial Peripheral Interface), a UART (Universal Asynchronous Receiver/Transmitter) Interface, a GPIO Interface, a CAN (Controller Area Network) Interface, an SDIO (Secure Digital Input and Output) Interface, and the like.

In one embodiment, the number of the FPGA modules on one PCB may be multiple, the first communication interface of each FPGA module may be connected to different interfaces of one connector module 11, and the second communication interface of each FPGA module may be connected to different other modules. Each FPGA module respectively performs protocol conversion processing on first data received through the second communication interface and sent by other modules, generates second data matched with the first communication interface and sends the second data to the connector module through the first communication interface; each FPGA module performs protocol conversion processing on third data received through the first communication interface and sent by the connector module 11, generates fourth data matched with the second communication interface, and sends the fourth data to the corresponding other modules through the second communication interface.

In one embodiment, the same connector module may be provided for different boards, and the connector modules may be of various types. For example, as shown in fig. 3, the connector has a fixed pin count, and different cards may use the same connector. The interface definition of the connector is shown in table 1 below:

interface	CAN	UART	I2C	I2S	GPIO	SPI	Analog	USB	GND
										Number of	2	4	4	12	11	4	6	2	14

TABLE 1 interface definition of connectors

Based on the above table 1, the requirements for the model selection and the low-speed GPIO number of the FPGA can be obtained, the route diagram of the FPGA model and the subsequent product can be confirmed, and the high-speed GPIO number of the TX/RX of the FPGA can be determined.

In one embodiment, as shown in fig. 4, interfaces required for the first module 131 and the second module 132 in the board where the FPGA module 12 is located to communicate and interact with other board cards are connected to GPIO interfaces of the FPGA module 12, and two pairs of high-speed GPIO interfaces of the FPGA module 12 are connected to the connector module 11 with a fixed pin count. The third module 231 and the fourth module 232 in the board where the FPGA module 22 is located need to interface with other board cards for communication and interaction, and are connected to the GPIO interface of the FPGA module 22. Two pairs of high-speed GPIO ports of the FPGA module 22 are connected with a connector module 21 with a fixed pin count.

The FPGA module 12 and the FPGA module 22 are respectively connected with the connector module 11 and the connector module 21 with fixed pin numbers to form two pairs of high-speed GPIOs, one pair of high-speed GPIOs are responsible for receiving external signals, the other pair of high-speed GPIOs are responsible for sending out signals in the board, and enough bandwidth of the high-speed GPIOs can be reserved according to the requirement on bandwidth in product definition to meet the requirement of products.

In one embodiment, as shown in fig. 5, the other module may be an MCU (micro controller Unit) module 133 or the like. Two FPGA modules, a main FPGA module 121 and a backup FPGA module 122, may be disposed on the PCB circuit board 10. The MCU module 133 is connected to the main FPGA module 121 and the backup FPGA module 122 through signal lines, which may be various signal lines.

The MCU module 133 receives the heartbeat signals sent by the main FPGA module 121 and the backup FPGA module 122, and determines whether the main FPGA module 121 and the backup FPGA module 122 have a fault and performs corresponding switching processing based on the heartbeat signals, so that the main FPGA module 121 or the backup FPGA module 122 is in a working state.

For example, the main FPGA module 121 and the backup FPGA module 122 are connected to the MCU module 133, the connector module 11, and other modules, respectively, in the same manner. The MCU module 133 receives the heartbeat signals sent by the main FPGA module 121 and the backup FPGA module 122, and determines whether the main FPGA module 121 and the backup FPGA module 122 have a fault based on the heartbeat signals.

If the MCU module 133 receives the heartbeat signals sent by the main FPGA module 121 and the backup FPGA module 122, the MCU module 133 controls the main FPGA module 121 to be in a working state and controls the backup FPGA module 122 to be in a sleep state by sending instructions, and the main FPGA module 121 forwards data and converts protocol data.

If the MCU module 133 receives the heartbeat signal sent by the backup FPGA module 122 and does not receive the heartbeat signal sent by the main FPGA module 121, the MCU module 133 determines that the main FPGA module 121 is abnormal, and controls the backup FPGA module 122 to be in a working state and the main FPGA module 121 to be in a sleep state by sending an instruction, and the backup FPGA module 122 forwards data and converts protocol data.

In one embodiment, as shown in fig. 6, the FPGA module 12 is provided with a debug JTAG interface 14, wherein the FPGA module 12 receives debug instructions and configuration information through the debug JTAG interface 14. The PCB 10 is provided with a storage module 15, the FPGA module 12 is connected with the storage module 15, wherein the storage module 15 comprises a DDR (double data rate synchronous dynamic random access memory) module, a FLASH module and the like.

In one embodiment, the present invention provides a board card including the communication interface device for inter-board communication as in any of the above embodiments. The board card comprises various main boards, function cards and the like.

The communication interface device and the board card for inter-board communication in the above embodiments can realize a normalized inter-board bus function, and can reduce the pin count of the connector; signals of all modules in the board card are accessed through the FPGA module and are output to the connector through the high-speed GPIO port of the FPGA module, so that the number of communication buses can be reduced, and the number of pins of the corresponding connector is correspondingly reduced; the matching problem of GPIO level can be reduced; because the power supplies used by different chips are different, signals of all modules in the board card are respectively connected to the FPGA module according to voltage classification, so that a level conversion device can be saved, and the problem of level mismatching of signals among boards does not exist; the compatibility among multiple platforms can be realized: because the number of pins occupied by the high-speed GPIO of the FPGA module on the connector is fixed, the communication compatibility of various platforms can be realized as long as the same connector is used and the same communication protocol is used.

Fig. 7 is a schematic flowchart of an embodiment of a data processing method according to the present invention, where the data processing method is based on the communication interface device for inter-board communication in any of the above embodiments, as shown in fig. 7:

and 701, the FPGA module receives first data sent by other modules through a second communication interface.

Step 702, the FPGA module performs protocol conversion processing on the first data to generate second data matched with the first communication interface and sends the second data to the connector module through the first communication interface.

And 703, the FPGA module receives the third data sent by the connector module through the first communication interface.

Step 704, the FPGA module performs protocol conversion processing on the third data, generates fourth data matched with the second communication interface, and sends the fourth data to other modules through the second communication interface.

Fig. 8 is a schematic flow chart of performing handover communication in an embodiment of a data processing method according to the present invention, and other modules include: an MCU module; the FPGA module comprises a main FPGA module and a backup FPGA module, and the MCU module is respectively connected with the main FPGA module and the backup FPGA module through signal lines; as shown in fig. 8:

step 801, the MCU module receives heartbeat signals sent by the main FPGA module and the backup FPGA module.

And step 802, if the main FPGA module is determined to be in a normal state based on the heartbeat signal, controlling the main FPGA module to be in a working state.

And 803, if the main FPGA module is determined to be in fault and the backup FPGA module is in a normal state based on the heartbeat signal, controlling the backup FPGA module to be in a working state.

The foregoing describes the general principles of the present disclosure in conjunction with specific embodiments, however, it is noted that the advantages, effects, etc. mentioned in the present disclosure are merely examples and are not limiting, and they should not be considered essential to the various embodiments of the present disclosure. Furthermore, the foregoing disclosure of specific details is for the purpose of illustration and description and is not intended to be limiting, since the disclosure is not intended to be limited to the specific details so described.

The communication interface device, the board card and the data processing method for inter-board communication in the above embodiments can realize a normalized inter-board bus function; signals of all modules in the board card are accessed through the FPGA module and are output to the connector through the high-speed GPIO interface of the FPGA module, so that the number of communication buses and pins of the connector can be reduced, a level conversion device can be saved, and the problem of level mismatching of signals between boards does not exist; by using the same connector and using the same communication protocol, communication compatibility of a variety of platforms can be achieved.

In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts in the embodiments are referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

The block diagrams of devices, apparatuses, systems referred to in this disclosure are only given as illustrative examples and are not intended to require or imply that the connections, arrangements, configurations, etc. must be made in the manner shown in the block diagrams. These devices, apparatuses, devices, and systems may be connected, arranged, configured in any manner, as will be appreciated by those skilled in the art. Words such as "including," comprising, "having," and the like are open-ended words that mean "including, but not limited to," and are used interchangeably therewith. The words "or" and "as used herein mean, and are used interchangeably with, the word" and/or, "unless the context clearly dictates otherwise. The word "such as" is used herein to mean, and is used interchangeably with, the phrase "such as but not limited to".

The methods and apparatus of the present disclosure may be implemented in a number of ways. For example, the methods and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order for the steps of the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above unless specifically stated otherwise. Further, in some embodiments, the present disclosure may also be embodied as programs recorded in a recording medium, the programs including machine-readable instructions for implementing the methods according to the present disclosure. Thus, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

It is also noted that in the devices, apparatuses, and methods of the present disclosure, each component or step can be decomposed and/or recombined. These decompositions and/or recombinations are to be considered equivalents of the present disclosure.

The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects, and the like, will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for purposes of illustration and description. Furthermore, the description is not intended to limit embodiments of the disclosure to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof.

Claims

1. A communication interface device for inter-board communication, comprising:

at least one FPGA module and a connector module arranged on the PCB; the FPGA module comprises: at least one first communication interface and at least one second communication interface; the at least one first communication interface is connected with the connector module; the at least one second communication interface is connected with other modules arranged on the PCB;

the FPGA module performs protocol conversion processing on first data received through the second communication interface and sent by the other modules to generate second data matched with the first communication interface, and sends the second data to the connector module through the first communication interface; and the FPGA module performs protocol conversion processing on third data received through the first communication interface and sent by the connector module to generate fourth data matched with the second communication interface, and sends the fourth data to other modules through the second communication interface.

2. The communication interface apparatus of claim 1,

the number of the first communication interfaces is two; the two first communication interfaces are respectively and correspondingly connected with the two third communication interfaces of the connector module to form two first communication channels; the two first communication channels are respectively used for transmitting the second data or receiving the third data.

3. The communication interface apparatus of claim 1,

the first communication interface and the third communication interface include: and a GPIO interface.

4. The communication interface apparatus of claim 1,

the number of the second communication interfaces is multiple; each second communication interface is respectively connected with the corresponding fourth communication interface of the other module to form a plurality of second communication channels; wherein the second communication channel is configured to receive the first data and to transmit the fourth data.

5. The communication interface apparatus of claim 1,

the number of the FPGA modules is multiple; the first communication interfaces of the FPGA modules are respectively connected with the connector module, and the second communication interfaces of the FPGA modules are respectively connected with the other corresponding modules.

6. The communication interface apparatus of claim 1,

the other modules include: an MCU module; the at least one FPGA module includes: the FPGA module comprises a main FPGA module and a backup FPGA module; the MCU module is respectively connected with the main FPGA module and the backup FPGA module through signal lines;

the MCU module is used for receiving heartbeat signals sent by the main FPGA module and the backup FPGA module, determining whether the main FPGA module and the backup FPGA module break down or not based on the heartbeat signals, and carrying out corresponding switching processing so as to enable the main FPGA module or the backup FPGA module to be in a working state.

7. The communication interface apparatus of claim 1,

the FPGA module is provided with a debugging JTAG interface, wherein the FPGA module receives debugging instructions and configuration information through the debugging JTAG interface.

8. A board card, comprising:

a communication interface device for interplate communication according to any one of claims 1 to 7.

9. A data processing method based on the communication interface device for interplate communication according to any one of claims 1 to 7, comprising:

the FPGA module receives first data sent by the other modules through the second communication interface;

the FPGA module carries out protocol conversion processing on the first data, generates second data matched with the first communication interface and sends the second data to the connector module through the first communication interface;

the FPGA module receives third data sent by the connector module through the first communication interface;

and the FPGA module performs protocol conversion processing on the third data to generate fourth data matched with the second communication interface, and sends the fourth data to the other modules through the second communication interface.

10. The method of claim 9, the other modules comprising: an MCU module; the FPGA module comprises: the FPGA module comprises a main FPGA module and a backup FPGA module; the MCU module is respectively connected with the main FPGA module and the backup FPGA module through signal lines, and the method further comprises the following steps:

the MCU module receives heartbeat signals sent by the main FPGA module and the backup FPGA module;

if the main FPGA module is determined to be in a normal state based on the heartbeat signal, controlling the main FPGA module to be in a working state;

and if the main FPGA module is determined to be in fault and the backup FPGA module is in a normal state based on the heartbeat signal, controlling the backup FPGA module to be in a working state.