CN113326212B - Data processing method and device and related equipment - Google Patents

Data processing method and device and related equipment Download PDF

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CN113326212B
CN113326212B CN202110210210.3A CN202110210210A CN113326212B CN 113326212 B CN113326212 B CN 113326212B CN 202110210210 A CN202110210210 A CN 202110210210A CN 113326212 B CN113326212 B CN 113326212B
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data
window
type
target
detection
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CN113326212A (en
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徐达人
石亚飞
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Calterah Semiconductor Technology Shanghai Co Ltd
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Calterah Semiconductor Technology Shanghai Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G06F12/0623—Address space extension for memory modules
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/781—On-chip cache; Off-chip memory

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  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
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  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

The application discloses a data processing method, a device and related equipment, comprising the following steps: determining a target detection window type; when the type of the target detection window is characterized as a detection window of a first type, reading first target data from a target storage device on the chip according to an addressing mode corresponding to the detection window of the first type; when the type of the target detection window is characterized as a detection window of a second type, reading second target data from the target storage device according to an addressing mode corresponding to the detection window of the second type; the number and the size of a plurality of target storage units included in the target storage device are not lower than the window width sizes of a first type of detection window and a second type of detection window, and the first type of detection window is different from the second type of detection window. Therefore, the same target storage device is applicable to different application scenes corresponding to different detection window types, and the flexibility of constant false alarm detection can be effectively improved.

Description

Data processing method and device and related equipment
The present application claims priority from chinese patent office, application number 202010131628.0, chinese patent application entitled "a data processing method, apparatus and device", filed 28 months 2020, the entire contents of which are incorporated herein by reference.
Technical Field
The present application relates to the field of target detection technologies, and in particular, to a method and apparatus for data processing, and related devices.
Background
When the interference intensity of the external signal changes in the process of detecting the target, the sensor can automatically adjust the sensitivity of the sensor, so that the false alarm probability (namely, the probability that the target is actually not present and is judged to be present) is kept unchanged, and the characteristic is called constant false alarm rate characteristic. Under the condition of keeping the constant false alarm probability, the probability of correctly detecting the target can reach the maximum value.
At present, for a digital signal processing module in a sensor, due to the limitation that only a single type of constant false alarm rate detection window and other factors can be adopted, only a specific application scene can be formulated and developed in a standardization manner, so that the sensor can be generally applicable to the scene only, but not applicable to other scenes, and the flexibility is poor.
Disclosure of Invention
The embodiment of the application provides a data processing method, a device and equipment, which are used for enabling a hardware acceleration chip to be suitable for more scenes and improving the flexibility of the hardware acceleration chip.
In a first aspect, an embodiment of the present application provides a data processing method, where the method includes: determining a target detection window type; when the type of the target detection window is characterized as a detection window of a first type, reading first target data from a target storage device on a chip according to an addressing mode corresponding to the detection window of the first type; when the target detection window type is characterized as a detection window of a second type, second target data are read from the target storage device according to an addressing mode corresponding to the detection window of the second type; the target storage device comprises a plurality of target storage units, the number and the size of the plurality of target storage units are not lower than the window width sizes of the first type detection window and the second type detection window, and the first type detection window is different from the second type detection window.
In this embodiment, on the one hand, according to the configuration operation of the user, the hardware acceleration chip may adopt different types of detection windows to perform data addressing, so that the hardware acceleration chip may be applicable to different application scenarios corresponding to different types of detection windows, and flexibility of the hardware acceleration chip is improved; in addition, when the hardware acceleration chip adopts different types of detection windows to address, the data can be read from the same target storage device, namely, the different types of detection windows can multiplex the same data path, so that the hardware complexity is not increased.
In some possible implementations, the first type of detection window is a square window, and the first target data includes at least first square window data of a first node and second square window data of a second node, the first node being adjacent to the second node; the reading the first target data from the plurality of target storage units on the chip according to the addressing mode corresponding to the first type of detection window includes: reading the first square window data from the target storage units on the chip according to an addressing mode corresponding to the square window; and reading first data corresponding to the second node from the plurality of target storage units, wherein the first data is data which is not overlapped with the first square window data in the second square window data, and the second square window data also comprises data which is overlapped with the first square window data. In this embodiment, the data overlapped between the first square window data and the second square window data does not need to be repeatedly read, so that the amount of the read data can be reduced, the consumption of hardware resources can be reduced, and the efficiency of data processing can be improved.
In some possible embodiments, the method further comprises: and adding third original data of a third node in an external storage device to the target storage device, wherein the third node is not adjacent to the second node. In this embodiment, while the square window data is read, the original data of the next node in the external storage device can be added to the target storage device at the same time, and it is not necessary to wait for the square window to read the original data of the next node from the external storage device after the square window is read, so that the data processing efficiency can be improved.
In some possible embodiments, the second type of detection window is a cross window, and the second target data includes at least first cross window data of a first node and second cross window data of a second node, the first node being adjacent to the second node; the reading second target data from the plurality of target storage units on the chip according to the addressing mode corresponding to the second type of detection window includes: reading the first cross window data from a plurality of target storage units on the chip according to the addressing mode corresponding to the cross window; and reading second data corresponding to the second node from the plurality of target storage units, wherein the second data is different from the first cross window data in the second cross window data, and the second cross window data also comprises the same data as the first cross window data. In this embodiment, the data overlapped between the first cross window data and the second cross window data does not need to be repeatedly read, so that the amount of the read data can be reduced, the consumption of hardware resources can be reduced, and the efficiency of data processing can be improved.
In some possible embodiments, the method further comprises: and adding the original data of a third node in the external storage device to the target storage device, wherein the third node is not adjacent to the second node. In this embodiment, the original data of the next node in the external storage device may be added to the target storage device at the same time when the cross window data is read, and it is not necessary to wait for the cross window to read the original data of the next node from the external storage device after the cross window is read, so that the data processing efficiency may be improved.
In some possible embodiments, the method further comprises: when the target detection window type is characterized as other types of detection windows (i.e. the number of the target detection window types is at least three), reading third target data from the target storage device according to the addressing mode corresponding to each of the other types of detection windows; the number of the target storage units in the target storage device is not lower than the window width of the detection windows of other types, and the detection windows of other types are different from the detection windows of the first type and the detection windows of the second type. In this embodiment, the same hardware resource may also support the third type of detection window to implement target detection at the same time, so that universality of implementation of the scheme may be further improved.
In some possible embodiments, the method further comprises: and denoising the first target data and/or the second target data to obtain fourth target data, wherein the data size of the fourth target data is smaller than that of the first target data or the second target data. In this embodiment, the influence of noise data on the target detection result can be reduced by performing the data drying process in advance, and the accuracy of detection can be improved.
In a second aspect, an embodiment of the present application further provides a data processing apparatus, where the apparatus includes a determining module, configured to determine a target detection window type; the first reading module is used for reading first target data from the target storage device on the chip according to an addressing mode corresponding to the first type of detection window when the type of the target detection window is characterized as the first type of detection window; the second reading module is used for reading second target data from the target storage device according to an addressing mode corresponding to the second type of detection window when the target detection window type is characterized as the second type of detection window; the target storage device comprises a plurality of target storage units, the number and the size of the plurality of target storage units are not lower than the window width sizes of the first type detection window and the second type detection window, and the first type detection window is different from the second type detection window.
In some possible embodiments, the apparatus further comprises: the third reading module is used for reading third target data from the target storage device according to the addressing modes corresponding to the other types of detection windows when the type of the target detection window is characterized as the other types of detection windows; the number of the target storage units in the target storage device is not lower than the window width of the detection windows of other types, and the detection windows of other types are different from the detection windows of the first type and the detection windows of the second type.
In some possible implementations, the first type of detection window is a square window, and the first target data includes at least first square window data of a first node and second square window data of a second node, the first node being adjacent to the second node; the first reading module includes: a first reading unit, configured to read the first square window data from a plurality of target storage units on the chip according to an addressing mode corresponding to the square window; and the second reading unit is used for reading first data corresponding to the second node from the plurality of target storage units, wherein the first data is data which is not overlapped with the first square window data in the second square window data, and the second square window data also comprises data which is overlapped with the first square window data.
In some possible embodiments, the apparatus further comprises: and the first adding module is used for adding the original data of a third node in the external storage device to the target storage device, wherein the third node is not adjacent to the second node.
In some possible embodiments, the second type of detection window is a cross window, and the second target data includes at least first cross window data of a first node and second cross window data of a second node, the first node being adjacent to the second node; the second reading module includes: a third reading unit, configured to read the first cross window data from the multiple target storage units on the chip according to an addressing mode corresponding to the cross window; and the fourth reading unit is used for reading second data corresponding to the second node from the plurality of target storage units, wherein the second data is different from the first cross window data in the second cross window data, and the second cross window data also comprises the same data as the first cross window data.
In some possible embodiments, the apparatus further comprises: and the second adding module is used for adding third original data of a third node in the external storage device to the target storage device, wherein the original data is different from the second cross window data in third cross window data of the third node, and the third node is not adjacent to the second node.
In some possible embodiments, the apparatus further comprises: and the denoising module is used for denoising the first target data and/or the second target data to obtain fourth target data, wherein the data volume of the fourth target data is smaller than the data volume of the first target data or the data volume of the second target data.
The data processing apparatus described in the second aspect corresponds to the data processing method described in the first aspect, so the technical effects of any implementation manner in the second aspect may be referred to the technical effect description of the related implementation manner in the first aspect, which is not described herein.
In a third aspect, embodiments of the present application further provide a computer device, the device including a processor and a memory: the memory is used for storing program codes and transmitting the program codes to the processor; the processor is configured to perform the data processing method according to any one of the above first aspects according to instructions in the program code.
In a fourth aspect, an embodiment of the present application further provides a constant false alarm detection device, including: the first storage module is used for storing data to be detected; the determining module is used for determining a detection window of a current required use type; a buffer for buffering a part of the data to be detected based on the detection window of the current required usage type; and the detection module is used for carrying out constant false alarm detection on the data to be detected cached by the cache based on the detection window of the current required use type.
In the embodiment, the constant false alarm detection device can buffer data and perform constant false alarm detection by utilizing the detection window with the determined type, so that the constant false alarm detection device can be applicable to different application scenes corresponding to different detection window types, and the flexibility of the constant false alarm detection device is improved; moreover, different types of detection windows may multiplex the same data path, thus hardware complexity may not be increased.
In one possible embodiment, the constant false alarm device further includes: the second storage module is used for storing at least two types of detection windows; the determining module is used for selecting one detection window from the at least two types of detection windows as the current required use type based on the received instruction or the scene parameter. In this embodiment, the second storage module may store multiple types of detection windows, so that the constant false alarm device may support application scenarios corresponding to multiple different types of detection windows.
In one possible embodiment, the at least two types of detection windows include at least two of a cross-shaped detection window, a square detection window, a rectangular detection window, a triangular detection window, and a trapezoidal detection window. Therefore, the constant false alarm device can be suitable for more application scenes.
In one possible implementation manner, the data to be detected is a two-dimensional matrix data structure; when constant false alarm detection is performed on any test node in the two-dimensional matrix data structure, the buffer is used for buffering all data covered by the detection window of the current required use type. Therefore, the constant false alarm device can buffer and detect the data corresponding to the detection window meeting the specific type each time.
In one possible implementation manner, the buffer includes a plurality of storage units, and a first dimension direction is defined as a row direction and a second dimension direction is defined as a column direction in the two-dimensional matrix data structure; when the buffer caches all data covered by the detection window of the current required use type, the same column of data in the two-dimensional matrix data structure is stored in the same storage unit, and each storage unit can only store one column of data in the two-dimensional matrix data structure. In this embodiment, the buffering of the detection window corresponding data is realized by a plurality of memory cells.
In one possible implementation, the first dimension is a distance dimension and the second dimension is a doppler dimension; or the first dimension is a Doppler dimension and the second dimension is a distance dimension.
In one possible implementation manner, a mode of sharing partial data is adopted to perform constant false alarm detection on two adjacent test nodes in the two-dimensional matrix data structure. Therefore, for the overlapped part between the window data corresponding to the two adjacent test nodes, repeated reading is not needed, the read data quantity can be reduced, the consumption of hardware resources can be reduced, and the data processing efficiency is improved.
In one possible implementation, the buffer and the first storage module are located in different physical storage components independent of each other; and/or the first storage module and the second storage module are located in the same physical storage component.
In one possible implementation, the constant false alarm detection device is an integrated circuit, and the detection module is a CPU or DSP in the integrated circuit.
In one possible implementation, the integrated circuit is a chip structure; wherein the buffer is a static random access memory.
In one possible implementation, the integrated circuit is a millimeter wave radar chip.
In a fifth aspect, an embodiment of the present application further provides a radio device, including: a carrier; the device of any one of the fourth aspects, provided on a carrier; an antenna disposed on the carrier, or integrated with the device as a unitary device AiP structure disposed on the carrier; the device is connected with the antenna and is used for transmitting and receiving radio signals by the antenna.
In a sixth aspect, an embodiment of the present application further provides an apparatus, including: an equipment body; and a radio device according to the fifth aspect provided on the apparatus body; wherein the radio device is used for target detection and/or communication.
In the above implementation manner of the embodiment of the present application, after a user completes a configuration operation on a user interface for a detection window type, the configuration operation may be responded to determine a target detection window type corresponding to the configuration operation; when the target detection window type is determined to be characterized as a first type of detection window, first target data can be read from a plurality of target storage units on the chip according to an addressing mode corresponding to the first type of detection window, and when the target detection window type is determined to be characterized as a second type of detection window, second target data can be read from a plurality of target storage units on the chip according to an addressing mode corresponding to the second type of detection window; the number and the size of the target storage devices are not lower than the window width sizes of a first type of detection window and a second type of detection window, and the first type of detection window is different from the second type of detection window. Therefore, on one hand, according to configuration operation of a user, the hardware acceleration chip can adopt different types of detection windows to carry out data addressing, so that the hardware acceleration chip can be applicable to different application scenes corresponding to different detection window types, and the flexibility of the hardware acceleration chip is improved; in addition, when the hardware acceleration chip adopts different types of detection windows to address, the data can be read from the same target storage device, namely, the different types of detection windows can multiplex the same data path, so that the hardware complexity is not increased.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to these drawings for those of ordinary skill in the art.
FIG. 1 is a flow chart of a data processing method according to an embodiment of the application;
FIG. 2 is a diagram of square window data and addressing modes of a first node and a second node;
FIG. 3 is a schematic diagram of cross window data and addressing modes of a first node and a second node;
FIG. 4 is a schematic diagram of a data processing apparatus according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a constant false alarm device according to an embodiment of the present application;
fig. 6 is a schematic diagram of a hardware structure of an apparatus according to an embodiment of the present application.
Detailed Description
Taking radar as an example, the method is described in detail for how the sensor performs constant false alarm detection in the process of performing target detection; it should be noted that the technical content described in the embodiments of the present application may also be applied to other types of sensors.
At present, a radar digital signal processing module on a hardware acceleration chip is usually formulated and developed based on a specific application scene, and a specific type of target detection window is adopted for the application scene, so that the developed hardware acceleration chip is only applicable to the scene, but cannot be flexibly applicable to various scenes.
Based on the above, the embodiment of the application provides a data processing method, so that the hardware acceleration chip can be suitable for various application scenes, and the flexibility of the hardware acceleration chip is improved. Specifically, after the user (such as a technician) completes the configuration operation of the user interface for the detection window type, the configuration operation can be responded to, and the target detection window type corresponding to the configuration operation can be determined; meanwhile, the radar can automatically determine a target detection window of the adaptation type with the current application scene according to the current environment information. When the target detection window type is determined to be characterized as a first type of detection window, first target data can be read from a plurality of target storage units on the chip according to an addressing mode corresponding to the first type of detection window, and when the target detection window type is determined to be characterized as a second type of detection window, second target data can be read from a plurality of target storage units on the chip according to an addressing mode corresponding to the second type of detection window; the number and the size of the target storage devices are not lower than the window width sizes of a first type of detection window and a second type of detection window, and the first type of detection window is different from the second type of detection window. Therefore, on one hand, according to configuration operation of a user, the hardware acceleration chip can adopt different types of detection windows to carry out data addressing, so that the hardware acceleration chip can be applicable to different application scenes corresponding to different detection window types, and the flexibility of the hardware acceleration chip is improved; in addition, when the hardware acceleration chip adopts different types of detection windows to address, the data can be read from the same target storage device on the chip, namely, the different types of detection windows can multiplex the same data path, so that the hardware complexity is not increased.
In order that the above objects, features and advantages of the present application will be more readily understood, a more particular description of various non-limiting embodiments of the application will be rendered by reference to the appended drawings. It will be apparent that the described embodiments are some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Referring to fig. 1, fig. 1 shows a flow chart of a data processing method in an embodiment of the present application, where the method specifically may include:
s101: the target detection window type is determined.
In some embodiments of practical application, a configuration interface for window type selection may be presented to a user (such as a technician, etc.), so that the user may select a detection window type to be used on the configuration interface, and may specifically perform a corresponding configuration operation. For example, the user may configure the time of use (which may be a period of time in the future, etc.), the width size of the detection window, etc. of a particular type of detection window on the configuration interface. Of course, the user can also complete the configuration of the detection window type by developing a corresponding configuration file.
Meanwhile, the sensor (such as a radar) can also automatically judge and/or select the type of the detection window matched with the current application scene based on the collected or received information parameters.
As some examples, the detection Window types in the present embodiment may include Square Window (SW), cross Window (CW), rectangular Window (RW), triangular Window (triangularly Window), trapezoidal Window (Trapezoid Window), and the like. The user or the sensor can select one of the detection window types to perform a corresponding configuration operation according to an application scenario in which the actual application is located, so as to determine the detection window type (hereinafter referred to as a target detection window type for convenience of description) used by the radar system for target detection. In practical applications, the detection window may specifically be a detection window in which a pointer is configured for a Constant False Alarm Rate (CRAR) module in the digital signal processing module.
S102: when the target detection window type is characterized as a detection window of a first type, first target data is read from a plurality of target storage units on the chip according to an addressing mode corresponding to the detection window of the first type.
S103: when the target detection window type is characterized as a detection window of a second type, second target data is read from a plurality of target storage units on the chip according to an addressing mode corresponding to the detection window of the second type, wherein the number and the size of the storage units of the target storage device are not lower than the window width sizes of the detection windows of the first type and the detection windows of the second type, and the detection windows of the first type are different from the detection windows of the second type. For example, the number of storage units in the target storage device is greater than or equal to the target number of the detection window, and the target storage device can support the same target number of the detection window under different target value ranges.
In this embodiment, when the radar system detects the target, a transmitting end (transmitting antenna) in the radar system may be used to transmit a signal, where the signal is reflected by an object located in a detectable area of the radar system, and then a receiving end (receiving antenna) in the radar system receives a reflected signal (such as an echo signal) and performs corresponding processing on the reflected signal, for example, performing fast fourier transform processing in a distance dimension or fast fourier transform processing in a speed dimension, so as to obtain original data that needs to be processed with constant false alarm rate.
The original data can be stored in the external memory in advance, and when the original data needs to be processed correspondingly, the original data can be written into a plurality of target storage units on the hardware acceleration chip by the external memory, and the original data on the target data storage device is processed by adopting a corresponding detection window. It should be noted that the external memory is located outside the data signal processing module with respect to the target storage device in the data signal processing module, but still configured in the hardware accelerator chip or module. As an example, the external Memory may specifically be a Static Random-Access Memory (SRAM) located in a hardware accelerator chip or module.
In an exemplary embodiment, the hardware acceleration chip may be configured by software, so that the hardware acceleration chip may read data from the multiple on-chip memories according to addressing modes corresponding to at least two different detection window types, so that the hardware acceleration chip may support at least two detection window types to perform data reading and target detection. Taking a hardware acceleration chip to support different types of first type detection windows and second type detection windows as examples (such as square windows and cross windows respectively), when the target detection window type determined based on user configuration operation is specifically the first type detection window, first target data can be read from a plurality of target storage units on a chip according to an addressing mode corresponding to the first type detection window, and when the target detection window type is specifically the second type detection window, second target data can be read from a plurality of target storage units on the chip according to an addressing mode corresponding to the second type detection window. When the types of the two detection windows are different, the addressing modes corresponding to the two detection windows can be different.
As an example, the first type of detection window may be a square window in particular, and the second type of detection window may be a cross window in particular. In this way, when the type of the target detection window is determined to be a square window, square window data corresponding to two adjacent nodes (such as a target node, hereinafter referred to as a first node and a second node respectively) can be sequentially read according to the addressing mode of the square window, that is, after the first square window data corresponding to the first node is read according to the addressing mode of the square window, the second square window data corresponding to the second node is read according to the same addressing mode. When the target detection window is determined to be the cross window, the first cross window data corresponding to the first node and the second cross window data corresponding to the second node can be sequentially read according to the addressing mode of the cross window. The first node and the second node are adjacent, either left and right, or up and down. It should be noted that, here, only two neighboring nodes are used for illustration, the number of nodes processed by the hardware acceleration chip in practical application may be more than 2, for example, 256, 512, etc., and for square window data or cross window data corresponding to other nodes, the analogy can be described with reference to the above process.
For ease of understanding, the following exemplifies the reading of square window data corresponding to the first node and the second node respectively according to the addressing mode of the square window. As shown in fig. 2, the left side of fig. 2 shows first square window data corresponding to a first node and second square window data corresponding to a second node (the second node is located on the right side of the first node), and each square window data corresponding to the node includes (n+1) × (n+1) pieces of data. It is assumed that the hardware acceleration chip includes n+1 on-chip memories (i.e., the above-mentioned target storage devices, namely, on-chip memories 0 to N, respectively; in practical applications, the value of N may be an even number different from 0 based on the object of the window design), raw data of 1 to n+1 for the Range Gate (Range Gate) is cached, and raw data of the Doppler Gate dimension is continuously cached in the interior of each on-chip memory, and the raw data may be written into the on-chip memory from the external memory in advance. When the first window data of the first node is read, the data of the distance gate dimension can be simultaneously and continuously read from the n+1 on-chip memories (which can also be regarded as the continuous sending data of the n+1 on-chip memories to the lower processing module at the same time), and when the original data of the n+1 Doppler gate dimension of the first node is read, the reading of the first window data of the first node is completed. At this time, the second square window data of the second node stored in the external memory may be continuously written into the n+1 on-chip memories, and simultaneously, the data in the distance gate dimension may be continuously read from the n+1 on-chip memories until the original data in the n+1 doppler gate dimension of the second node is completed.
When cross window data corresponding to the first node and the second node are read according to the addressing mode of the cross window, referring to fig. 3, the left side of fig. 3 shows the first cross window data corresponding to the first node and the second cross window data corresponding to the second node (the second node is located at the right side of the first node), and the width and the length (including the original data) of the cross window data corresponding to each node are both n+1. Assuming that the hardware acceleration chip includes n+1 on-chip memories (on-chip memory 0 to on-chip memory N, respectively), the upper window portion (High Wing) data, the test point (Design Under Test, DUT) data, and the lower window portion (Low Wing) data of the range gate dimension are cached in three portions, and original data of the doppler gate dimension is continuously cached inside each on-chip memory, and can be written into the on-chip memory from an external memory in advance. When the first cross window data of the first node is read, the cache data of the on-chip memory can be addressed in three parts from the Doppler gate dimension according to the window characteristics of the cross window, namely a Left window part (Left window), a DUT and a Right window part (Right window). Specifically, N/2 pieces of original data (i.e., left window) can be read continuously in the dimension of the doppler gate, k is skipped (k is a natural number, i.e., when k is equal to 0, the next piece of original data can be read directly without skipping the action of k, the value of k can be preset according to actual requirements, and also can be adaptively adjusted according to the current application scenario) the data of one DUT can be read by using on-chip memory addresses, and then N/2 pieces of original data (i.e., right window) can be read continuously skipped by skipping k on-chip memory addresses, so that the reading of the first cross window data of the first node is completed. At this time, the second cross window data of the second node stored in the external memory may be continuously written into the n+1 on-chip memories, and the data of the distance gate dimension may be continuously read from the n+1 on-chip memories simultaneously with reference to the above process until the original data of the n+1 doppler gate dimension of the second node is completed.
It can be understood that in practical application, since the first node and the second node are two adjacent nodes, the square window data (or cross window data) corresponding to the first node and the square window data (or cross window data) corresponding to the second node are partially overlapped. Thus, in some possible embodiments, after the square window data (or cross window data) corresponding to the first node is read, the overlapping data may be simply written into the target storage units on the chip without repeatedly writing into and reading from the target storage units on the chip, and the non-overlapping portion data may be read out from the target storage units on the chip. As an example, when the first type of detection window is specifically a square window, first square window data corresponding to a first node may be read from a plurality of target storage units on the chip according to an addressing manner corresponding to the square window, then, when second square window data corresponding to a second node is read, only first data corresponding to the second node may be read from the plurality of target storage units, where the first data refers to data, which does not overlap with the first square window data, in the second square window data corresponding to the second node, and for data, which overlaps with the first square window data, since the partial data has been read when the first square window data is read, the reading may not be repeated, and square window data corresponding to the second node refers to the first data and the overlapping data.
Similarly, when the detection window of the first type is specifically a cross window, the first cross window data corresponding to the first node may be read from the multiple target storage units on the chip according to the addressing mode corresponding to the cross window, then, when the second cross window data corresponding to the second node is read, only the second data corresponding to the second node may be read from the multiple target storage units, where the second data refers to the data, which is not overlapped with the first cross window data, in the second cross window data corresponding to the second node, and for the data, which is overlapped with the first cross window data, the part of the data is already read when the first cross window data is read, so that the repeated reading is not needed, and the cross window data corresponding to the second node refers to the second data and the overlapped data.
For example, the first window data of the first node and the second window data of the second node shown in fig. 2 may be read continuously from n+1 on-chip memories according to the addressing mode of the square window until the original data of the n+1th doppler dimension is read; then, since the original data of the 2 nd to n+1 th doppler dimensions in the first square window data corresponding to the first node and the original data of the 1 st to N th doppler dimensions in the second square window data corresponding to the second node overlap, as shown by a hatched portion in fig. 2, the original data of the n+1 th doppler dimensions of the second node can be read from the corresponding target storage device, and the original data of the 1 st to N th doppler dimensions in the second square window data has been read without re-reading, thereby completing the reading of the second square window data.
Taking the above-described reading of the first cross window data of the first node and the second cross window data of the second node shown in fig. 3 as an example, the reading of the first cross window data of the first node may be completed by sequentially and continuously reading N/2 original data (i.e., left window) according to the addressing mode of the cross window, skipping k (k is a natural number) on-chip memory addresses to read the data of one DUT, and then continuously skipping k on-chip memory addresses to read N/2 original data (i.e., right Wing). Then, since the original data of the 2 nd to N/2, (N/2+2k+2) to (n+2k+1) doppler dimensions in the first cross window data of the first node overlap with the original data of the second cross window data of the second node, only the original data of the second cross window data, which do not overlap with the first cross window data, can be read, that is, the original data of the N/2, (N/2+k+1) and (n+2k+1) doppler dimensions in the data of the second cross window can be read, and the original data of the 1 st to (N/2-1) and (N/2+2k+1) to (n+2k) doppler dimensions in the data of the second cross window overlap with the original data of the 2 nd to N/2, (N/2+2k+2) to (n+2k+1) doppler dimensions in the first cross window data, as shown in a hatched portion in fig. 2, so that the consumption of hardware resources can be reduced and the efficiency of data processing can be improved.
In practical applications, the number of the nodes processed is usually far more than 2, so after the square window data or the cross window data corresponding to the second node is read, the square window data or the cross window data corresponding to the next node (adjacent to the second node) can be read continuously. The buffer space of the on-chip target storage device is usually smaller, and all the original data of all the nodes in the external storage device cannot be buffered at one time, so that the original data corresponding to the third node in the external storage device can be written into the corresponding target storage device on-chip while the square window data or the cross window data corresponding to the first node/the second node are read, the address space of the used target storage device is the address space corresponding to the read data, and the read data cannot be read and used when the square window data or the cross window data of other nodes are read later.
For example, assuming that the square window data of the first node and the second node are sequentially read from left to right, and the square window data corresponding to the first node includes the original data of 9 nodes (i.e., 3 rows and 3 columns), the nodes 1, 2, … … and 9 are respectively numbered, where the first node is numbered as node 5, and the second node is numbered as node 6, after the square window data corresponding to the first node is read, when the square window data of the node 6, the node 7 and the other nodes are subsequently read, the original data of the node 1 does not need to be read, and at this time, the original data of the node (i.e., the third node) that needs to be subsequently read may be written from the external storage device into the storage area (address space) corresponding to the original data of the node 1 in the target storage device. Similarly, after the square window data corresponding to the second node is read, when the square window data of other nodes such as the node 7, the node 8 and the like are read later, the original data of the node 2 is not required to be read any more, and at this time, the original data of other nodes which need to be read later can be written into the storage area corresponding to the original data of the node 2 in the target storage device from the external storage device.
In this way, the original data of the new node can be written into the target storage device while the data corresponding to the first node/the second node is read, so that when the data corresponding to other nodes (corresponding to windows such as square windows or cross windows) are read later, the time waste is avoided to wait for the original data corresponding to the third node to be written into the target storage device on the chip from the external storage device.
Based on this, in another possible embodiment, when the target detection window type is a square window or a cross window, the raw data of the third node in the external storage device may be added to the target storage device. Wherein the third node and the second node are not adjacent nodes.
It should be noted that, in this embodiment, the hardware acceleration chip is configured by using software, so that the hardware acceleration chip may support two different types of detection windows to perform data reading for example for illustration, and in practical application, three or more types of detection windows may also be simultaneously supported to perform data reading. For example, when the type of the target detection window is determined to be other types of detection windows (i.e., the types of the target detection windows are at least three) based on the configuration operation of the user, the third target data may be read from the multiple target storage units on the chip according to the addressing modes corresponding to the other types of detection windows, and of course, the number of the target storage devices is not lower than the window width size of the other types of detection windows, and the other types of detection windows are different from the first type of detection window and the second type of detection window, for example, may be triangular windows different from square windows and cross windows.
In another possible implementation manner, after the first node and/or the data corresponding to the node (such as square window data, cross window data, etc.) are read, the read data may be subjected to noise removal processing, and the fourth target data may be obtained after the noise data is filtered, so that a subsequent processing procedure is performed based on the fourth target data corresponding to each node, for example, target detection is performed according to the fourth target data corresponding to each node. In general, the data amount of the fourth target data obtained after the filtering is smaller than the data amount of the first target data or the data amount of the second target data before the filtering. The specific implementation process of the denoising process may be that the denoising process is performed by a preset algorithm through a software mode or the like.
In this embodiment, in response to a configuration operation of a user with respect to a detection window type, a target detection window type corresponding to the configuration operation is determined, or the type of the detection window is automatically determined based on received or acquired scene information; when the target detection window type is determined to be characterized as a first type of detection window, first target data can be read from a plurality of target storage units on the chip according to an addressing mode corresponding to the first type of detection window, and when the target detection window type is determined to be characterized as a second type of detection window, second target data can be read from a plurality of target storage units on the chip according to an addressing mode corresponding to the second type of detection window; the number of the target storage devices is not lower than the window width of a first type of detection window and a second type of detection window, and the first type of detection window is different from the second type of detection window. Therefore, on one hand, according to configuration operation of a user, the hardware acceleration chip can adopt different types of detection windows for addressing, so that the hardware acceleration chip can be applicable to different application scenes corresponding to different detection window types, and the flexibility of the hardware acceleration chip is improved; in addition, when the hardware acceleration chip adopts different types of detection windows to address, the data can be read from the same target storage device, namely, the different types of detection windows can multiplex the same data path, so that the hardware complexity is not increased.
In addition, the embodiment of the application also provides a data processing device. Referring to fig. 4, fig. 4 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present application, the apparatus 400 may include:
a determining module 401, configured to determine a target detection window type;
a first reading module 402, configured to read first target data from a target storage device on a chip according to an addressing mode corresponding to a detection window of a first type when the type of the target detection window is characterized as the detection window of the first type;
a second reading module 403, configured to read second target data from the target storage device according to an addressing mode corresponding to the second type of detection window when the target detection window type is characterized as the second type of detection window;
the target storage device comprises a plurality of target storage units, the number and the size of the plurality of target storage units are not lower than the window width sizes of the first type detection window and the second type detection window, and the first type detection window is different from the second type detection window.
In some possible embodiments, the apparatus 400 further comprises:
The third reading module is used for reading third target data from the target storage device according to the addressing modes corresponding to the other types of detection windows when the type of the target detection window is characterized as the other types of detection windows;
the number of the target storage units in the target storage device is not lower than the window width of the detection windows of other types, and the detection windows of other types are different from the detection windows of the first type and the detection windows of the second type.
In some possible implementations, the first type of detection window is a square window, and the first target data includes at least first square window data of a first node and second square window data of a second node, the first node being adjacent to the second node;
the first reading module 402 includes:
a first reading unit, configured to read the first square window data from a plurality of target storage units on the chip according to an addressing mode corresponding to the square window;
and the second reading unit is used for reading first data corresponding to the second node from the plurality of target storage units, wherein the first data is data which is not overlapped with the first square window data in the second square window data, and the second square window data also comprises data which is overlapped with the first square window data.
In some possible embodiments, the apparatus 400 further comprises:
and the first adding module is used for adding the original data of a third node in the external storage device to the target storage device, wherein the third node is not adjacent to the second node.
In some possible embodiments, the second type of detection window is a cross window, and the second target data includes at least first cross window data of a first node and second cross window data of a second node, the first node being adjacent to the second node;
the second reading module 403 includes:
a third reading unit, configured to read the first cross window data from the multiple target storage units on the chip according to an addressing mode corresponding to the cross window;
and the fourth reading unit is used for reading second data corresponding to the second node from the plurality of target storage units, wherein the second data is different from the first cross window data in the second cross window data, and the second cross window data also comprises the same data as the first cross window data.
In some possible embodiments, the apparatus 400 further comprises:
And the second adding module is used for adding third original data of a third node in the external storage device to the target storage device, wherein the original data is different from the second cross window data in third cross window data of the third node, and the third node is not adjacent to the second node.
In some possible embodiments, the apparatus 400 further comprises:
and the denoising module is used for denoising the first target data and/or the second target data to obtain fourth target data, wherein the data volume of the fourth target data is smaller than the data volume of the first target data or the data volume of the second target data.
It should be noted that, the data processing apparatus in this embodiment corresponds to the data processing method in the foregoing method embodiment, and specific implementations of each module and unit in this embodiment may be referred to the relevant places in the foregoing method embodiment and will not be described herein.
In addition, the embodiment of the application also provides a constant false alarm detection device. Referring to fig. 5, fig. 5 shows a schematic structural diagram of a constant false alarm detection device, and the device 500 may include a first storage module 501, a determination module 502, a buffer 503, and a detection module 504.
The first storage module 501 may be configured to store data to be detected. In practical application, the radar system may transmit a signal by using a transmitting end (transmitting antenna) in the radar system in the target detection process, after the signal is reflected by an object located in a detectable area of the radar system, a receiving end (receiving antenna) in the radar system receives a reflected signal (such as an echo signal), and performs corresponding processing on the reflected signal, such as performing fast fourier transform processing in a distance dimension or fast fourier transform processing in a speed dimension, so as to obtain data to be detected that needs to be processed with constant false alarm rate. As an example, the first memory module 501 may be, for example, a memory, such as an SRAM located in a hardware accelerator chip or module, or the like; the data to be detected stored in the first storage module 501 may be a two-dimensional matrix data structure.
A determining module 502 is configured to determine a detection window of a currently required usage type. As an example, the types of detection windows may include square windows, cross windows, rectangular windows, triangular windows, trapezoidal windows, and the like. In the actual application, the user may select one of the detection window types to execute a corresponding configuration operation according to an application scenario in which the actual application is located, and correspondingly, the determining module 502 may determine the type of the detection window based on the selection operation executed by the user; in other embodiments, the determining module 502 may also automatically determine the type of the detection window by using the application scene sensed by the sensor, which is not limited in this embodiment.
As a specific implementation example for determining the type of the detection window, the constant false alarm detection device may further include a second storage module, where at least two types of detection windows may be stored, so that the determining module 502 may select, based on the received instruction or the scene parameter, one of the at least two types of detection windows as the detection window of the currently required type of use. Wherein the second memory module may be located in the same physical memory component as the first memory module 501.
The buffer 503 is configured to read a portion of data to be detected from the first storage module 501 through the detection window of the determined type, and buffer the read portion of data to be detected. It should be understood that the constant false alarm detection device processes only a part of the data to be detected each time when performing constant false alarm detection by using the detection window, and accordingly, the buffer 503 may only buffer a part of the data to be detected each time. The buffer 503 may be located in a different physical storage component than the first storage module.
For example, when the read data to be detected is a two-dimensional matrix data structure, and constant false alarm detection is performed on any test node in the two-dimensional matrix data structure (i.e. a node when the two-dimensional matrix data structure is detected), the data buffered by the buffer 503 is all the data covered by the detection window of the type currently required to be used. Wherein the two-dimensional matrix data structure may comprise two dimensions. For convenience of description, the first dimension direction is defined as a row direction and the second dimension direction is defined as a column direction in the two-dimensional matrix data structure. In practice, the first dimension may be, for example, a distance dimension, and the second dimension may be, for example, a doppler dimension; of course, the first dimension may be a doppler dimension, and the second dimension may be a distance dimension, which is not limited in this embodiment.
The buffer 503 may include a plurality of memory cells, and when all data covered by the detection window of the currently required usage type is buffered in the buffer 503, the same column of data in the two-dimensional matrix data structure is stored in the same memory cell, and each memory cell can only store one column of data in the two-dimensional matrix data structure.
The detection module 504 is configured to perform constant false alarm detection on a portion of the data to be detected buffered in the buffer 503 based on the determined detection window of the currently required usage type, and a specific implementation process of performing constant false alarm detection by using the detection window may be described in the foregoing embodiments, which is not described herein.
In practical application, since partial data overlap exists between window data corresponding to two adjacent test nodes, when the constant false alarm device 500 respectively performs constant false alarm detection on two connected test nodes in the two-dimensional matrix data structure, the constant false alarm device can perform constant false alarm detection on the two connected test nodes in a manner of sharing partial data, so that after the window data corresponding to one test node is read, data overlapped with the test node in the window data corresponding to the other test node does not need to be repeatedly read, only data which are not overlapped in the window data corresponding to the other test node can be read, the read data quantity can be reduced, the consumption of hardware resources can be reduced, and the data processing efficiency is improved.
In practical application, the specific implementation form of the constant false alarm device 500 may be an integrated circuit, and correspondingly, the detection module 504 in the constant false alarm device 500 may be a CPU (central processing unit) or DSP (Digital Signal Processing ) element in the integrated circuit.
Further, when the constant false alarm device 500 is implemented by an integrated circuit, the integrated circuit may specifically be a chip structure, such as a millimeter wave radar chip. Of course, the integrated circuit may be implemented in other hardware. The buffer may be a static random access memory, although other types of memory are also possible.
In addition, the embodiment of the application also provides equipment. Referring to fig. 6, fig. 6 is a schematic diagram showing a hardware structure of an apparatus according to an embodiment of the present application, where the apparatus 600 includes a processor 601 and a memory 602:
the memory 602 is used for storing program codes and transmitting the program codes to the processor 601;
the processor 601 is configured to execute the following steps according to instructions in the program code:
determining a target detection window type;
when the type of the target detection window is characterized as a detection window of a first type, reading first target data from a target storage device on a chip according to an addressing mode corresponding to the detection window of the first type;
When the target detection window type is characterized as a detection window of a second type, second target data are read from the target storage device according to an addressing mode corresponding to the detection window of the second type;
the target storage device comprises a plurality of target storage units, the number and the size of the plurality of target storage units are not lower than the window width sizes of the first type detection window and the second type detection window, and the first type detection window is different from the second type detection window.
Furthermore, the processor 601 is configured to perform specific steps or other steps described in the method embodiments above or implement functions described in the apparatus embodiments above according to instructions in the program code.
In one embodiment, the present application also provides a radio device comprising: a carrier; the integrated circuit of the above embodiment is disposed on the carrier; the antenna is arranged on the carrier; the integrated circuit is connected with the antenna through a first transmission line and is used for receiving and transmitting radio signals. The carrier may be a printed circuit board PCB, and the first transmission line may be a PCB trace. In addition, the integrated circuit may also be integrated with the antenna into a unitary device structure such as AiP structure.
In one embodiment, the present application also provides an apparatus comprising: an equipment body; and the radio device of the above embodiment provided on the apparatus body; wherein the radio is used for object detection and/or communication.
Specifically, on the basis of the above-described embodiments, in one embodiment of the present application, the radio device may be disposed outside the apparatus body, in another embodiment of the present application, the radio device may also be disposed inside the apparatus body, and in other embodiments of the present application, the radio device may also be disposed partially inside the apparatus body, and partially outside the apparatus body. The present application is not limited thereto, and is particularly applicable.
It should be noted that the radio device may perform functions such as object detection and communication by transmitting and receiving signals.
In an alternative embodiment, the device body may be a component or product for applications such as smart home, transportation, smart home, consumer electronics, monitoring, industrial automation, in-cabin detection, and health care; for example, the device body may be an intelligent transportation device (such as an automobile, a bicycle, a motorcycle, a ship, a subway, a train, etc.), a security device (such as a camera), an intelligent wearable device (such as a bracelet, glasses, etc.), an intelligent home device (such as a television, an air conditioner, an intelligent lamp, etc.), various communication devices (such as a mobile phone, a tablet computer, etc.), etc., and may also be various instruments for detecting vital sign parameters and various devices carrying the instruments, such as a barrier gate, an intelligent traffic light, an intelligent sign, a traffic camera, various industrial manipulators (or robots), etc., and the radio device may be a radio device described in any embodiment of the present application, and the structure and the working principle of the radio device are already described in the above embodiments and are not described in detail herein.
The embodiment of the application also provides a computer readable storage medium. The methods described in the above embodiments may be implemented in whole or in part by software, hardware, firmware, or any concatenation thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer readable media can include computer storage media and communication media and can include any medium that can transfer a computer program from one place to another. The storage media may be any target media that is accessible by a computer.
As an alternative design, the computer readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium targeted for carrying or storing the desired program code in the form of instructions or data structures and accessible by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. The splice described above should also be included within the scope of computer readable media.
In the present application, "english: of", corresponding to "and" corresponding to "are sometimes used in combination, and it should be noted that the meaning of the expression is consistent when the distinction is not emphasized.
It should be noted that, in the embodiments of the present application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment of the present application is not to be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
In the present application, "at least one" means one or more. "plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of the following" or its similar expressions, refers to any concatenation of these items, including any concatenation of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural. In addition, in order to facilitate the clear description of the technical solution of the embodiments of the present application, in the embodiments of the present application, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.
From the above description of embodiments, it will be apparent to those skilled in the art that all or part of the steps of the above described example methods may be implemented in software plus general hardware platforms. Based on such understanding, the technical solution of the present application may be embodied in the form of a software product, which may be stored in a storage medium, such as a read-only memory (ROM)/RAM, a magnetic disk, an optical disk, etc., and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network communication device such as a router) to perform the method according to the embodiments or some parts of the embodiments of the present application.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points. The apparatus embodiments described above are merely illustrative, in which the modules illustrated as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present application without undue burden.
The foregoing description of the exemplary embodiments of the application is merely illustrative of the application and is not intended to limit the scope of the application.

Claims (12)

1. A method of data processing, the method comprising:
determining a target detection window type;
when the type of the target detection window is characterized as a detection window of a first type, reading first target data from a target storage device on a chip according to an addressing mode corresponding to the detection window of the first type;
when the target detection window type is characterized as a detection window of a second type, second target data are read from the target storage device according to an addressing mode corresponding to the detection window of the second type;
the target storage device comprises a plurality of target storage units, the number and the size of the plurality of target storage units are not lower than the window width sizes of the first type detection window and the second type detection window, and the first type detection window is different from the second type detection window.
2. The method of claim 1, wherein the first type of detection window is a square window, the first target data comprising at least first square window data of a first node and second square window data of a second node, the first node being adjacent to the second node;
The reading the first target data from the target storage device on the chip according to the addressing mode corresponding to the first type of detection window includes:
reading the first square window data from the target storage units on the chip according to an addressing mode corresponding to the square window;
and reading first data corresponding to the second node from the plurality of target storage units, wherein the first data is data which is not overlapped with the first square window data in the second square window data, and the second square window data also comprises data which is overlapped with the first square window data.
3. The method according to claim 2, wherein the method further comprises:
and adding the original data of a third node in the external storage device to the target storage device, wherein the third node is not adjacent to the second node.
4. The method of claim 1, wherein the second type of detection window is a cross window, the second target data comprising at least first cross window data of a first node and second cross window data of a second node, the first node being adjacent to the second node;
the reading second target data from the plurality of target storage units on the chip according to the addressing mode corresponding to the second type of detection window includes:
Reading the first cross window data from a plurality of target storage units on the chip according to the addressing mode corresponding to the cross window;
and reading second data corresponding to the second node from the plurality of target storage units, wherein the second data is different from the first cross window data in the second cross window data, and the second cross window data also comprises the same data as the first cross window data.
5. The method according to claim 4, wherein the method further comprises:
and adding the original data of a third node in the external storage device to the target storage device, wherein the third node is not adjacent to the second node.
6. The method according to claim 1, wherein the method further comprises:
when the type of the target detection window is characterized as other types of detection windows, reading third target data from the target storage device according to the addressing modes corresponding to the other types of detection windows respectively;
the number of the target storage units in the target storage device is not lower than the window width of the detection windows of other types, and the detection windows of other types are different from the detection windows of the first type and the detection windows of the second type.
7. The method according to any one of claims 1 to 6, further comprising:
and denoising the first target data and/or the second target data to obtain fourth target data, wherein the data size of the fourth target data is smaller than that of the first target data or the second target data.
8. A data processing apparatus, the apparatus comprising:
a determining module, configured to determine a target detection window type in response to a configuration operation of a user for the detection window type;
the first reading module is used for reading first target data from the target storage device on the chip according to an addressing mode corresponding to the first type of detection window when the target detection window type is characterized as the first type of detection window;
the second reading module is used for reading second target data from the target storage device according to an addressing mode corresponding to the second type of detection window when the target detection window type is characterized as the second type of detection window;
the target storage device comprises a plurality of target storage units, the number and the size of the plurality of target storage units are not lower than the window width sizes of the first type detection window and the second type detection window, and the first type detection window is different from the second type detection window.
9. The apparatus of claim 8, wherein the apparatus further comprises:
the third reading module is used for reading third target data from the plurality of target storage units on the chip according to the addressing mode corresponding to each other type of detection window when the type of the target detection window is characterized as other types of detection windows;
the number and the size of the target storage units are not lower than the window width of the detection windows of other types, and the detection windows of other types are different from the detection windows of the first type and the detection windows of the second type.
10. A computer device, the device comprising a processor and a memory:
the memory is used for storing program codes and transmitting the program codes to the processor;
the processor is configured to perform the data processing method of any one of claims 1 to 7 according to instructions in the program code.
11. A radio device, comprising:
a carrier;
a data processing apparatus as claimed in claim 8 or 9, disposed on the carrier;
an antenna disposed on the carrier, or integrated with the data processing device into an integrated device AiP structure disposed on the carrier;
The data processing device is connected with the antenna and is used for transmitting and receiving radio signals by the antenna.
12. An apparatus, comprising:
an equipment body; and
the radio device of claim 11 disposed on the device body;
wherein the radio device is used for target detection and/or communication.
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