CN113315369A - Charge pump circuit - Google Patents

Charge pump circuit Download PDF

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Publication number
CN113315369A
CN113315369A CN202110779715.1A CN202110779715A CN113315369A CN 113315369 A CN113315369 A CN 113315369A CN 202110779715 A CN202110779715 A CN 202110779715A CN 113315369 A CN113315369 A CN 113315369A
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CN
China
Prior art keywords
circuit
charge pump
output end
clock
driving circuit
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CN202110779715.1A
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Chinese (zh)
Inventor
于海霞
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Beijing Unigroup Tsingteng Microsystems Co Ltd
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Beijing Unigroup Tsingteng Microsystems Co Ltd
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Priority to CN202110779715.1A priority Critical patent/CN113315369A/en
Publication of CN113315369A publication Critical patent/CN113315369A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The application provides a charge pump circuit specifically includes: clock drive circuit, charge pump and feedback branch. In the charge pump circuit, the amplitude of the driving signal provided by the clock driving circuit is adjusted by the feedback branch circuit according to the magnitude relation between the high-voltage signal output by the charge pump and the preset threshold value through regulating the clock driving circuit, and finally the high-voltage signal tends to the preset threshold value, so that even if the process, the power supply voltage, the temperature and the load of the charge pump circuit change, the high-voltage signal output by the charge pump finally tends to be stable through the regulation.

Description

Charge pump circuit
Technical Field
The invention relates to the technical field of power electronics, in particular to a charge pump circuit.
Background
In memory technology, to implement writing and deleting of data, a programming voltage and an erasing voltage much higher than a power supply voltage, i.e., a high voltage signal, are generally required, and thus a charge pump circuit is widely used in a memory.
As shown in fig. 1, a conventional charge pump circuit provides clock drive for a charge pump when a high-voltage signal output by the charge pump is smaller than a preset threshold, so as to increase the output of the charge pump, and removes the clock drive when the high-voltage signal output by the charge pump is greater than the preset threshold, so as to decrease the output of the charge pump; however, each time the above process is performed, a spike voltage is formed, and thus, the ripple is formed in the high voltage signal output by the charge pump without stopping the process.
When the process, the power supply voltage, the temperature and the load of the charge pump circuit change, the ripple also changes, for example, when the power supply voltage is high or the load is low, the ripple is large, and therefore, when the process, the power supply voltage, the temperature and the load of the charge pump circuit change, how to reduce the ripple formed in the high-voltage signal is one of the problems to be solved at present.
Disclosure of Invention
In view of the above, the present invention provides a charge pump circuit, by which the size of a ripple formed in a high voltage signal output by the charge pump circuit itself can be reduced when the process, the power supply voltage, the temperature, and the load of the charge pump circuit vary.
In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:
the application provides a charge pump circuit, including: the device comprises a clock driving circuit, a charge pump and a feedback branch circuit; wherein:
the clock driving circuit outputs driving signals to the charge pump, and the output end of the charge pump is connected with the load circuit and outputs high-voltage signals;
the sampling end of the feedback branch circuit is connected with the output end of the charge pump, the output end of the feedback branch circuit is connected with the regulation end of the clock driving circuit, and the feedback branch circuit is used for regulating the amplitude of the driving signal through the regulation and control clock driving circuit according to the size relation between the high-voltage signal and the preset threshold value, and finally enabling the high-voltage signal to tend to the preset threshold value.
Optionally, the clock driving circuit includes: a clock circuit and a drive circuit; wherein:
the output end of the clock circuit is connected with the input end of the driving circuit, and the output end of the driving circuit is used as the output end of the clock driving circuit;
the input terminal of the clock circuit receives a supply voltage.
Optionally, the positive electrode of the power supply end of the driving circuit receives the power supply voltage, and the negative electrode of the power supply end of the driving circuit is used as the regulation end of the clock driving circuit.
Optionally, the driving circuit includes: a first inverter and a second inverter; wherein:
the input end of the first inverter is used as the input end of the driving circuit; the output end of the first phase inverter is connected with the input end of the second phase inverter, and the connection point is used as one pole of the output end of the driving circuit; the output end of the second inverter is used as the other pole of the output end of the driving circuit;
and the power supply end anodes of the first phase inverter and the second phase inverter are used as the power supply end anodes of the driving circuit, and the power supply end cathodes of the first phase inverter and the second phase inverter are used as the power supply end cathodes of the driving circuit.
Optionally, the feedback branch includes: the circuit comprises a sampling circuit, an operational amplifier and a common source amplifier; wherein:
the sampling end of the sampling circuit is used as the sampling end of the feedback branch circuit, and the output end of the sampling circuit is connected with the inverting input end of the operational amplifier;
the non-inverting input end of the operational amplifier receives a reference voltage, the output end of the operational amplifier is connected with the input end of the common source amplifier, and the output end of the common source amplifier serves as the output end of the feedback branch.
Optionally, the sampling circuit includes: a first voltage dividing resistor and a second voltage dividing resistor; wherein:
the first voltage-dividing resistor and the second voltage-dividing resistor are connected in series, one end of the series connection is used as a sampling end of the sampling circuit, and the other end of the series connection is grounded;
and the connection point of the first voltage-dividing resistor and the second voltage-dividing resistor is used as the output end of the sampling circuit.
Optionally, the common-source amplifier includes: an NMOS tube; wherein:
the grid electrode of the NMOS tube is used as the input end of the common source amplifier, the source electrode of the NMOS tube is grounded, and the drain electrode of the NMOS tube is used as the output end of the common source amplifier.
Optionally, the preset threshold is any value of the high-voltage signal for implementing the erasing function of the memory.
Optionally, the method further includes: at least one other of said charge pumps; wherein:
all the charge pumps are connected in series or in parallel.
Optionally, the charge pump includes: the device comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first capacitor and a second capacitor; wherein:
the drain electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, and the connection point is the output end of the charge pump;
the source electrode of the first NMOS tube, the source electrode of the first PMOS tube, the grid electrode of the second NMOS tube, the grid electrode of the second PMOS tube and one end of the first capacitor are all connected, and the other end of the first capacitor is used as one pole of the driving end of the charge pump;
the source electrode of the second NMOS tube, the source electrode of the second PMOS tube, the grid electrode of the first NMOS tube, the grid electrode of the first PMOS tube and one end of the second capacitor are all connected, and the other end of the second capacitor is used as the other pole of the driving end of the charge pump;
and the drain electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube, and the connection point is the input end of the charge pump.
As can be seen from the above technical solutions, the present invention provides a charge pump circuit, which specifically includes: clock drive circuit, charge pump and feedback branch. In the charge pump circuit, the amplitude of the driving signal provided by the clock driving circuit is adjusted by the feedback branch circuit according to the magnitude relation between the high-voltage signal output by the charge pump and the preset threshold value through regulating the clock driving circuit, and finally the high-voltage signal tends to the preset threshold value, so that even if the process, the power supply voltage, the temperature and the load of the charge pump circuit change, the high-voltage signal output by the charge pump finally tends to be stable through the regulation.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional charge pump circuit;
FIG. 2 is a schematic diagram of a flash circuit of a memory unit;
fig. 3-6 are schematic diagrams of 4 structures of a charge pump circuit according to an embodiment of the present disclosure;
FIG. 7 is a schematic diagram of a charge pump;
fig. 8 is a schematic diagram of an inverter.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In this application, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Fig. 1 shows a specific structure and a specific connection relationship of a conventional charge pump circuit, which specifically includes: clock circuit 11, drive circuit 12, charge pump 13, resistor string 14 and comparator 15.
The specific connection relationship is as follows:
the output end of the charge pump 13 is connected with the load circuit 16, the resistor string 14 is arranged between the output end of the charge pump 13 and the ground GND, the high-voltage signal HVOUT output by the charge pump 13 is divided by the resistor string 14 to generate a sampling signal DIV and is input to the inverting input end of the comparator 15, and the sampling signal DIV is compared with the reference voltage VREF received by the non-inverting input end of the comparator 15; the comparator 15 outputs the comparison result to the control terminal of the clock circuit 11 in the form of an enable signal EN to control the switching of the clock circuit 11; the output end of the clock circuit 11 is connected with the input end of the driving circuit 12, and the output end of the clock circuit 11 is connected with the driving end of the charge pump 13.
The specific working process is as follows:
when the high voltage signal HVOUT is greater than the target value, the divided voltage signal is greater than the reference voltage VREF, the comparator 15 outputs the enable signal EN of logic low level, the clock circuit 11 is controlled to pause, that is, the clock circuit 11 does not output the clock signal CLK to the driving circuit 12 any more, the driving circuit 12 does not output the CK and CKB signals to drive the charge pump 13 after receiving the clock signal CLK, and thus the high voltage signal HVOUT output by the charge pump 13 is reduced.
When the high voltage signal HVOUT is smaller than the target value, the comparator 15 outputs an enable signal EN of a logic high level to control the clock circuit 11 to start, i.e. the clock circuit 11 outputs a clock signal CLK to the driving circuit 12; the drive circuit 12 outputs CK and CKB signals to the charge pump 13 to drive the charge pump 13 after receiving the clock signal CLK, so that the high voltage signal HVOUT output by the charge pump 13 rises.
However, the conventional charge pump circuit has a problem that a ripple formed in a high voltage signal HVOUT output by itself is large when a process, a power supply voltage, a temperature, and a load of itself are changed.
In order to reduce the size of a ripple formed in a high voltage signal HVOUT output by a charge pump circuit when the process, the power supply voltage, the temperature and the load of the charge pump circuit vary, embodiments of the present application provide a charge pump circuit, which is applied to a memory, such as a memory cell flash circuit.
The specific structure of the memory unit flash circuit is shown in fig. 2, and specifically includes: an operation unit MN0 and a selection unit MN 1; the gate of the operation cell MN0 is used as SG, the drain is used as BL, the source is connected to the drain of the selection cell MN1, the substrate SPW is connected to the substrate SPW of the selection cell MN1, the gate of the selection cell MN1 is used as CG, and the source is used as SL.
A special data storage layer exists between the gate of the operation unit MN0 and the substrate SPW for storing electrons or holes, i.e., read operation, write operation, and erase operation of the flash circuit of the memory cell can be realized by applying operation voltages to the ports SG, CG, BL, SL, and SPW.
The specific structure of the charge pump circuit provided in the embodiment of the present application is shown in fig. 3, and includes: clock driver circuit 20, charge pump 30 and feedback branch 40.
In the charge pump circuit, the output terminal of the clock drive circuit 20 is connected to the drive terminal of the charge pump 30 and outputs a drive signal Dr; the output terminal of the charge pump 30 is connected to the load circuit 50 and outputs a high voltage signal HVOUT; the sampling terminal of the feedback branch 40 is connected to the output terminal of the charge pump 30, and the output terminal of the feedback branch 40 is connected to the regulation terminal of the clock driving circuit 20.
During operation, the feedback branch circuit 40 samples the high voltage signal HVOUT, and adjusts the amplitude of the driving signal Dr by regulating the clock driving circuit 20 according to the magnitude relationship between the high voltage signal HVOUT and the preset threshold, and finally makes the high voltage signal HVOUT tend to the preset threshold.
Specifically, when the charge pump circuit is just started, the high voltage signal HVOUT output by the charge pump 30 is low, that is, the high voltage signal HVOUT is lower than the preset threshold, and at this time, the feedback branch circuit 40 adjusts the amplitude of the driving signal Dr to be large by regulating and controlling the clock driving circuit 20, so that the high voltage signal HVOUT gradually increases; when the high voltage signal HVOUT rises to be greater than the preset threshold, the feedback branch circuit 40 adjusts the amplitude of the driving signal Dr to be smaller by regulating the clock driving circuit 20 at the moment, so that the high voltage signal HVOUT is gradually reduced; when the high voltage signal HVOUT is decreased to be less than the preset threshold value again, the feedback branch circuit 40 increases the amplitude of the driving signal Dr by regulating the clock driving circuit 20, so that the high voltage signal HVOUT is gradually increased; by repeating this operation, the high voltage signal HVOUT output by the charge pump 30 tends to reach the preset threshold, i.e., the amplitude of the driving signal Dr tends to be stable.
As can be derived from the above description, after the process, the power supply voltage, the temperature, and the load of the charge pump circuit change, the high voltage signal HVOUT output by the charge pump 30 finally tends to be stable through the above adjustment, so that, compared with the conventional charge pump circuit, the ripple formed in the high voltage signal HVOUT output by the charge pump circuit is smaller, and thus, the charge pump circuit can reduce the ripple formed in the high voltage signal HVOUT output by the charge pump circuit when the process, the power supply voltage, the temperature, and the load change.
In another embodiment of the charge pump 30, the predetermined threshold is any value that the high voltage signal HVOUT can realize the memory erasing function, and is not specifically limited herein, and is within the protection scope of the present application as the case may be.
It should be noted that, in this way, the charge pump circuit can also ensure that the erase and write functions of the memory can be normally realized all the time when the process, the power supply voltage, the temperature and the load of the charge pump circuit change; in addition, it is preferable that the preset threshold is the minimum value of the high voltage signal HVOUT that can implement the memory erasing function, so that the size of the ripple formed in the self-output high voltage signal HVOUT can be further reduced.
In another embodiment of the charge pump 30, in addition to the above embodiment, the charge pump further includes: the number of the charge pumps 30 is not specifically limited, and may be selected according to specific situations, and all of the charge pumps 30 are within the protection scope of the present application; wherein all charge pumps 30 are connected in series or in parallel.
Another embodiment of the present application provides a specific implementation of the clock driving circuit 20, which has a specific structure as shown in fig. 4, and includes: a clock circuit 21 and a drive circuit 22.
In the clock driving circuit 20, an input terminal of the clock circuit 21 receives a power supply voltage VCC; the output end of the clock circuit 21 is connected with the input end of the drive circuit 22, and outputs a clock signal CLK; the output terminal of the driving circuit 22 serves as the output terminal of the clock driving circuit 20, and outputs a driving signal Dr; the positive terminal of the power supply terminal of the driving circuit 22 receives the power supply voltage VCC, and the negative terminal of the power supply terminal of the driving circuit 22 serves as the regulation terminal of the clock driving circuit 20.
In operation, the clock circuit 21 provides a clock signal CLK for the driving circuit 22, and the driving circuit 22 outputs a driving signal Dr according to the clock signal CLK, wherein the amplitude of the driving signal Dr depends on the difference between the power supply voltage VCC and the power supply terminal negative electrode potential of the driving circuit 22; when the high voltage signal HVOUT output by the charge pump 30 is smaller than the preset threshold, the potential of the negative terminal of the power source terminal of the driving circuit 22 is lowered under the regulation of the feedback branch 40, so that the amplitude of the driving signal Dr is increased; when the high voltage signal HVOUT output by the charge pump 30 is greater than the preset threshold, the potential of the negative terminal of the power source terminal of the driving circuit 22 is increased under the regulation of the feedback branch 40, so that the amplitude of the driving signal Dr becomes smaller.
The above is only one embodiment of the clock driving circuit 20, and in practical applications, the embodiments include but are not limited to the above two embodiments, which are not specifically limited herein, and may be selected according to specific situations, and all of them are within the scope of the present application.
The present embodiment further provides a specific implementation of the driving circuit 22, which has a structure as shown in fig. 5, and includes: a first inverter 01 and a second inverter 02.
In this embodiment of the drive circuit 22, the input of the first inverter 01 serves as the input of the drive circuit 22; the output end of the first inverter 01 is connected with the input end of the second inverter 02, and the connection point is used as one pole of the output end of the driving circuit 22 to output CKB signals; the output end of the second inverter 02 serves as the other pole of the output end of the driving circuit 22, and outputs a CK signal; the power source terminal anodes of the first inverter 01 and the second inverter 02 serve as the power source terminal anodes of the drive circuit 22, and the power source terminal cathodes of the first inverter 01 and the second inverter 02 serve as the power source terminal cathodes of the drive circuit 22.
The level of the CK signal is the same as that of the clock signal CLK, and the level of the CKB signal is opposite to that of the clock signal CLK, namely the CK signal and the CKB signal are opposite phase signals; the difference between the two is the amplitude of the driving signal Dr output by the driving circuit 22.
The above is only one specific embodiment of the driving circuit 22, and in practical applications, including but not limited to the above embodiments, the embodiments are not limited herein, and may be within the protection scope of the present application as the case may be.
The present embodiment further provides a specific implementation of an inverter, a specific structure of which is shown in fig. 8, and the implementation includes: a third PMOS transistor P3 and a third NMOS transistor N3; the connection point of the grid electrode of the third PMOS pipe P3 and the grid electrode of the third NMOS pipe N3 is used as the input end of the phase inverter; the drain electrode of the third PMOS tube P3 is connected with the drain electrode of the third NMOS tube N3, and the connection point is used as the output end of the phase inverter; the source of the third PMOS pipe P3 is used as the power supply end anode of the inverter; the source of the third NMOS transistor N3 acts as the power supply terminal cathode of the inverter.
The above is only one specific embodiment of the inverter, and in practical applications, including but not limited to the above embodiments, the embodiments are not specifically limited herein, and may be within the protection scope of the present application.
Another embodiment of the present application provides a specific implementation manner of the feedback branch circuit 40, and the specific structure thereof is shown in fig. 6, and includes: a sampling circuit 41, an operational amplifier OPA and a common source amplifier 42.
In this embodiment of the feedback branch 40, the sampling terminal of the sampling circuit 41 serves as the sampling terminal of the feedback branch 40, and the output terminal of the sampling circuit 41 is connected to the inverting input terminal of the operational amplifier OPA; the non-inverting input terminal of the operational amplifier OPA receives the reference voltage VREF, the output terminal of the operational amplifier OPA is connected to the input terminal of the common source amplifier 42, and the output terminal of the common source amplifier 42 serves as the output terminal of the feedback branch 40.
During operation, the sampling circuit 41 samples the high voltage signal HVOUT output by the charge pump 30, and the sampling result is output to the inverting input terminal of the operational amplifier OPA in the form of the sampling signal DIV; the operational amplifier OPA amplifies a difference between the reference voltage VREF and the sampling signal DIV and outputs the amplified result in the form of an output signal OUTA; the common-source amplifier 42 adjusts the regulation terminal potential of the clock driving circuit 20 according to the output signal OUTA.
Preferably, the common-source amplifier 42 is an NMOS transistor, that is, the source of the NMOS transistor is connected to ground GND, the gate of the NMOS transistor is used as the input terminal of the common-source amplifier 42, and the drain of the NMOS transistor is used as the output terminal of the common-source amplifier 42; in practical applications, including but not limited to the above embodiments, the specific situation may be determined, and the specific limitations are not specifically limited herein.
Taking the common-source amplifier 42 as an NMOS transistor as an example, when the high-voltage signal HVOUT is smaller than the preset threshold, the sampling signal DIV is smaller than the reference voltage VREF, the output signal OUTA is larger than zero, if the sampling signal DIV is smaller than the previous time, the output signal OUTA is increased, the NMOS transistor pulls down the potential of the negative terminal of the power source of the driving circuit 22, if the sampling signal DIV is larger than the previous time, the output signal OUTA is decreased, and the NMOS transistor pulls up the potential of the negative terminal of the power source of the driving circuit 22; when the high voltage signal HVOUT is greater than the preset threshold, the sampling signal DIV is greater than the reference voltage VREF, the output signal OUTA is less than zero, and at this time, the NMOS transistor is in a weak on-state or off-state, so that the potential of the negative electrode of the power terminal of the driving circuit 22 is further pulled high.
In another embodiment of the feedback branch 40, the operational amplifier OPA may be replaced by other circuits or electrical components, which are not specifically limited herein and are within the protection scope of the present application as the case may be.
The above two embodiments of the feedback branch circuit 40 are only described, and in practical applications, including but not limited to the above embodiments, the embodiments are not limited herein, and may be within the protection scope of the present application as the case may be.
The present embodiment further provides a specific implementation of the sampling circuit 41, which has a structure as shown in fig. 6, and includes: a first divider resistor R1 and a second divider resistor R2.
In this embodiment of the sampling circuit 41, the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 are connected in series, one end of the series being a sampling end of the sampling circuit 41, the other end being connected to ground GND; the connection point of the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 serves as the output end of the sampling circuit 41, and outputs the sampling signal DIV.
When the sampling circuit works, the first voltage division resistor R1 and the second voltage division resistor R2 divide the voltage of the high-voltage signal HVOUT and output the high-voltage signal HVOUT in the form of a sampling signal DIV; the resistances of the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 need to be set in combination with the actual application scenario of the charge pump circuit, so as to ensure the normal operation of the charge pump circuit.
The above is only one specific embodiment of the sampling circuit 41, and in practical applications, including but not limited to the above embodiments, the embodiments are not limited herein, and may be within the protection scope of the present application as the case may be.
Another embodiment of the present application provides an implementation of the charge pump 30, which has a specific structure as shown in fig. 7, and includes: the circuit comprises a first PMOS tube P1, a second PMOS tube P2, a first NMOS tube N1, a second NMOS tube N2, a first capacitor C1 and a second capacitor C2.
In this embodiment of the charge pump 30, the drain of the first NMOS transistor N1 is connected to the drain of the second NMOS transistor N2, and the connection point is the output terminal of the charge pump 30;
the source electrode of the first NMOS transistor N1, the source electrode of the first PMOS transistor P1, the grid electrode of the second NMOS transistor N2, the grid electrode of the second PMOS transistor P2 and one end of a first capacitor C1 are all connected, and the other end of the first capacitor C1 is used as the first electrode of the driving end of the charge pump 30; the source electrode of the second NMOS transistor N2, the source electrode of the second PMOS transistor P2, the gate electrode of the first NMOS transistor N1, the gate electrode of the first PMOS transistor P1, and one end of the second capacitor C2 are all connected, and the other end of the second capacitor C2 is used as the other end of the driving end of the charge pump 30; the drain of the first PMOS transistor P1 is connected to the drain of the second PMOS transistor P2, and the connection point receives the power supply voltage VCC.
The above is only one embodiment of the charge pump 30, and in practical applications, including but not limited to the above embodiments, the embodiments are not limited herein, and may be within the protection scope of the present application as the case may be.
In the above description of the disclosed embodiments, features described in various embodiments in this specification can be substituted for or combined with each other to enable those skilled in the art to make or use the present application. The foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention in any manner. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims (10)

1. A charge pump circuit, comprising: the device comprises a clock driving circuit, a charge pump and a feedback branch circuit; wherein:
the clock driving circuit outputs driving signals to the charge pump, and the output end of the charge pump is connected with the load circuit and outputs high-voltage signals;
the sampling end of the feedback branch circuit is connected with the output end of the charge pump, the output end of the feedback branch circuit is connected with the regulation end of the clock driving circuit, and the feedback branch circuit is used for regulating the amplitude of the driving signal through the regulation and control clock driving circuit according to the size relation between the high-voltage signal and the preset threshold value, and finally enabling the high-voltage signal to tend to the preset threshold value.
2. The charge pump circuit of claim 1, wherein the clock driver circuit comprises: a clock circuit and a drive circuit; wherein:
the output end of the clock circuit is connected with the input end of the driving circuit, and the output end of the driving circuit is used as the output end of the clock driving circuit;
the input terminal of the clock circuit receives a supply voltage.
3. The charge pump circuit of claim 2, wherein the positive power terminal of the driving circuit receives the power voltage, and the negative power terminal of the driving circuit serves as a regulation terminal of the clock driving circuit.
4. The charge pump circuit of claim 2, wherein the driver circuit comprises: a first inverter and a second inverter; wherein:
the input end of the first inverter is used as the input end of the driving circuit; the output end of the first phase inverter is connected with the input end of the second phase inverter, and the connection point is used as one pole of the output end of the driving circuit; the output end of the second inverter is used as the other pole of the output end of the driving circuit;
and the power supply end anodes of the first phase inverter and the second phase inverter are used as the power supply end anodes of the driving circuit, and the power supply end cathodes of the first phase inverter and the second phase inverter are used as the power supply end cathodes of the driving circuit.
5. The charge pump circuit according to any of claims 1-4, wherein the feedback branch comprises: the circuit comprises a sampling circuit, an operational amplifier and a common source amplifier; wherein:
the sampling end of the sampling circuit is used as the sampling end of the feedback branch circuit, and the output end of the sampling circuit is connected with the inverting input end of the operational amplifier;
the non-inverting input end of the operational amplifier receives a reference voltage, the output end of the operational amplifier is connected with the input end of the common source amplifier, and the output end of the common source amplifier serves as the output end of the feedback branch.
6. The charge pump circuit of claim 5, wherein the sampling circuit comprises: a first voltage dividing resistor and a second voltage dividing resistor; wherein:
the first voltage-dividing resistor and the second voltage-dividing resistor are connected in series, one end of the series connection is used as a sampling end of the sampling circuit, and the other end of the series connection is grounded;
and the connection point of the first voltage-dividing resistor and the second voltage-dividing resistor is used as the output end of the sampling circuit.
7. The charge pump circuit of claim 5, wherein the common-source amplifier comprises: an NMOS tube; wherein:
the grid electrode of the NMOS tube is used as the input end of the common source amplifier, the source electrode of the NMOS tube is grounded, and the drain electrode of the NMOS tube is used as the output end of the common source amplifier.
8. The charge pump circuit according to any of claims 1-4, wherein the predetermined threshold is any value at which the high voltage signal implements a memory erase function.
9. The charge pump circuit of any of claims 1-4, further comprising: at least one other of said charge pumps; wherein:
all the charge pumps are connected in series or in parallel.
10. The charge pump circuit of claim 9, wherein the charge pump comprises: the device comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first capacitor and a second capacitor; wherein:
the drain electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, and the connection point is the output end of the charge pump;
the source electrode of the first NMOS tube, the source electrode of the first PMOS tube, the grid electrode of the second NMOS tube, the grid electrode of the second PMOS tube and one end of the first capacitor are all connected, and the other end of the first capacitor is used as one pole of the driving end of the charge pump;
the source electrode of the second NMOS tube, the source electrode of the second PMOS tube, the grid electrode of the first NMOS tube, the grid electrode of the first PMOS tube and one end of the second capacitor are all connected, and the other end of the second capacitor is used as the other pole of the driving end of the charge pump;
and the drain electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube, and the connection point is the input end of the charge pump.
CN202110779715.1A 2021-07-09 2021-07-09 Charge pump circuit Pending CN113315369A (en)

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CN113991999A (en) * 2021-10-18 2022-01-28 上海华虹宏力半导体制造有限公司 Charge pump boosting system
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Application publication date: 20210827