CN113314550A

CN113314550A - Image sensor, forming method thereof and integrated chip

Info

Publication number: CN113314550A
Application number: CN202010960076.4A
Authority: CN
Inventors: 蓝浚恺; 金海光; 匡训冲
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2020-02-27
Filing date: 2020-09-14
Publication date: 2021-08-27

Abstract

Various embodiments of the present disclosure relate to an image sensor. The image sensor includes an image sensor element disposed within a substrate. The substrate comprises a first material. The image sensor element includes an active layer containing a second material different from the first material. The buffer layer is disposed between the active layer and the substrate. The buffer layer extends along the outer sidewall and the bottom surface of the active layer. The cap structure overlies the active layer. The outer sidewalls of the active layer are laterally spaced apart between the outer sidewalls of the cap structure such that the cap structure extends continuously over the outer edges of the active layer.

Description

Image sensor, forming method thereof and integrated chip

Technical Field

The embodiment of the invention relates to an image sensor, a forming method thereof and an integrated chip.

Background

Integrated Circuits (ICs) with image sensors are used in various modern electronic devices. In recent years, a complementary metal-oxide semiconductor (CMOS) image sensor (CIS) has come into wide use, and has largely replaced a charge-coupled device (CCD) image sensor. Compared to a CCD image sensor, CIS is increasingly favored due to low power consumption, small size, fast data processing, direct data output, and low manufacturing cost.

Disclosure of Invention

An embodiment of the present invention provides an image sensor, including: a substrate comprising a first material; an image sensor element disposed within the substrate, wherein the image sensor element comprises an active layer comprising a second material different from the first material; a buffer layer disposed between the active layer and the substrate, wherein the buffer layer extends along outer sidewalls and a bottom surface of the active layer; and a cap structure overlying the active layer, wherein the outer sidewalls of the active layer are laterally spaced apart between outer sidewalls of the cap structure such that the cap structure extends continuously over an outer edge of the active layer.

An embodiment of the present invention provides an integrated chip, including: a substrate comprising a first material, wherein the substrate comprises opposing sidewalls and a lower surface defining a trench extending into a frontside surface of the substrate; an active layer disposed within the trench, wherein the active layer comprises a second material different from the first material; a buffer layer lining the trench such that the buffer layer is disposed between the substrate and the trench, wherein the buffer layer comprises a compound of the first material and the second material; a cap structure extending continuously over the active layer and the buffer layer, wherein the cap structure overlies the opposing sidewalls of the substrate defining the trench, wherein the cap structure includes the first material; and a silicide layer disposed within the cap structure.

An embodiment of the present invention provides a method of forming an image sensor, including: forming a dielectric layer along a surface of a substrate, wherein the substrate comprises a first material; etching the dielectric layer and the substrate to define a trench in the substrate; forming a buffer layer in the trench such that the dielectric layer contacts the buffer layer; forming an active layer within the trench, wherein the active layer comprises a second material different from the first material; and forming a cap structure over the active layer such that the cap structure extends continuously along a top surface of the active layer, wherein the cap structure comprises the first material, and wherein the cap structure overlies an uppermost edge of the active layer.

Drawings

Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates a cross-sectional view of some embodiments of an image sensor including a cap structure that extends continuously over an outer edge of an image sensor element.

Fig. 2A-2E illustrate cross-sectional views of some embodiments of an image sensor according to some alternative embodiments of the image sensor of fig. 1.

Fig. 3A-3B illustrate cross-sectional views of some embodiments of an integrated chip including an interconnect structure over a substrate, wherein a cap structure extends continuously over a top surface of an image sensor element.

Fig. 4-14 illustrate cross-sectional views of some embodiments of a first method of forming an image sensor including a capping structure along an image sensor element.

Fig. 15-17B illustrate cross-sectional views of some embodiments of a second method of forming an image sensor including a capping structure along an image sensor element.

FIG. 18 illustrates, in flow chart format, a method showing some embodiments of forming an image sensor including a cap structure along an image sensor element.

Detailed Description

The present disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "under.. talbelow", "lower", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another (other) element or feature as illustrated in the figures for ease of description. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.

A CMOS Image Sensor (CIS) generally includes a pixel area array having image sensor elements arranged in a semiconductor substrate, respectively. Upon receiving incident radiation, the image sensor element is configured to generate an electrical signal corresponding to the received incident radiation. The electrical signals from the image sensor elements may be processed by a signal processing unit. The semiconductor substrate may include a first material (e.g., silicon) and the image sensor elements may include an active layer including a second material (e.g., germanium) different from the first material. The active layer is disposed within the semiconductor substrate. Further, the second material may be selected to enhance absorption of incident electromagnetic radiation within a first wavelength range (e.g., the first wavelength range includes Infrared (IR) radiation). This may increase the ability of the image sensor element to perform depth detection and/or phase detection. The enhanced ability to capture incident electromagnetic radiation in the first wavelength range may improve the performance of the image sensor element in time of flight (TOF) applications.

One challenge of the above-described CIS is damage to the active layer during fabrication of the image sensor element. For example, fabrication of a CIS may include forming trenches within a semiconductor substrate and subsequently forming a buffer layer lining the trenches. An active layer is deposited over the buffer layer and fills the trench, and a planarization process (e.g., a Chemical Mechanical Planarization (CMP) process) is performed into the active layer. A cap structure is formed over the active layer such that outer sidewalls of the cap structure are aligned with and/or laterally spaced between outer sidewalls of the active layer. An upper dielectric layer is formed over the cap structure and the semiconductor substrate. In addition, one or more silicide layers may be formed in the cap structure and/or the semiconductor substrate. Forming the one or more silicide layers may include depositing a conductive layer (e.g., comprising nickel) over the cap structure and/or the semiconductor substrate and performing an annealing process to form the one or more silicide layers. Subsequently, a removal process (e.g., a wet etching process) is performed on the semiconductor substrate to remove the remaining portion of the conductive layer that is not formed into silicide. The removal process includes exposing the semiconductor substrate to one or more etchants (e.g., hydrogen peroxide (e.g., H)₂O₂)). The one or more etchants can damage the active layer by penetrating seams located at an upper edge of the active layer. The seam is located at an interface between the dielectric layer and the active layer. This may result in the formation of voids in the active layer and/or damage to the active layer, thereby degrading the performance of the image sensor element.

Accordingly, some embodiments of the present disclosure relate to an image sensor including a cap structure overlying an active layer, and an associated method of forming an image sensor. For example, a method of forming an image sensor may include forming a trench within a semiconductor substrate and subsequently forming a trenchA buffer layer of row liners. An active layer is deposited over the buffer layer and fills the trench, and a planarization process (e.g., a Chemical Mechanical Planarization (CMP) process) is performed into the active layer. A cap structure is formed over the active layer such that outer sidewalls of the active layer are laterally spaced between outer sidewalls of the cap structure. Thus, the width of the top cover structure is greater than the width of the active layer and the top cover structure covers directly and extends continuously over the outer edge of the active layer. An upper dielectric layer is formed over the cap structure and the semiconductor substrate. In addition, one or more silicide layers may be formed in the cap structure and/or the semiconductor substrate. Subsequently, a removal process (e.g., a wet etching process) is performed on the semiconductor substrate (e.g., to remove the remaining portions of the conductive layer that are not formed as silicide). The removal process includes exposing the semiconductor substrate to one or more etchants (e.g., hydrogen peroxide (e.g., H)₂O₂)). Since the cap structure covers the outer edges of the active layer, the one or more etchants may be prevented from reaching the active layer during the removal process. This in turn can mitigate damage to the active layer by the one or more etchants, thereby improving the performance of the image sensor.

Fig. 1 shows a cross-sectional view of some embodiments of the image sensor 100, the image sensor 100 comprising a cap structure 112 extending continuously over the outer edges 108e1, 108e2 of the active layer 108.

The image sensor 100 includes a dielectric structure 116 overlying the substrate 102. An image sensor element 106 is provided within the substrate 102. Image sensor elements 106 are configured to convert electromagnetic radiation 120 (e.g., photons) into electrical signals (i.e., electron-hole pairs (electron-hole pairs) are generated from electromagnetic radiation 120). Electromagnetic radiation 120 may be disposed on the backside surface 102b of the substrate. Thus, in some embodiments, electromagnetic radiation 120 is backside-illuminated (BSI) on the image sensor 100. In some embodiments, image sensor elements 106 may, for example, be configured to generate electrical signals from Infrared (IR) radiation (e.g., electromagnetic radiation having a wavelength in a range of about 800 nanometers (nm) to 2,500 nm).

In some embodiments, the substrate 102 is composed of a first material (e.g., silicon). In addition, the image sensor element 106 includes an active layer 108 disposed within the groove of the substrate 102 and a buffer layer 110 disposed between the active layer 108 and the substrate 102. In still other embodiments, the active layer 108 includes a second material (e.g., germanium) different from the first material. In still other embodiments, the buffer layer 110 includes a combination of a first material and a second material and provides a transition region between the substrate 102 and the active layer 108. A first isolation structure 104 is disposed within the substrate 102 and the first isolation structure 104 provides electrical isolation to the image sensor element 106 from other devices and/or doped regions (not shown) disposed within/on the substrate 102. The first isolation structure 104 may laterally surround the image sensor element 106. The active layer 108 may, for example, include photodetector regions and/or layers (e.g., charge storage regions, floating nodes, surface pinning regions, contact regions, guard rings, etc. (not shown)) configured to convert electromagnetic radiation 120 (e.g., photons) into electrical signals and/or facilitate readout of the electrical signals. In some embodiments, the second material (e.g., germanium) of the active layer 108 is selected to ensure a high Quantum Efficiency (QE) of the IR radiation of the image sensor elements 106, thereby improving the performance of the image sensor 100.

The cap structure 112 overlies the frontside surface 102f of the substrate 102 and extends continuously over the top surface of the active layer 108 and the top surface of the buffer layer 110. A dielectric layer 114 overlies the front side surface 102f of the substrate 102 and the cap structure 112. A dielectric structure 116 overlies the dielectric layer 114. In still other embodiments, the thickness of the cap structure 112 is greater than the thickness of the dielectric layer 114. In some embodiments, the cap structure 112 may be or include, for example, a first material (e.g., silicon), epitaxial silicon, amorphous silicon, crystalline silicon, a high-k dielectric material (e.g., aluminum oxide, hafnium oxide), another suitable material, or any combination of the foregoing. In addition, the cap structure 112 extends continuously over the opposing sidewalls of the image sensor element 106. Thus, the cap structure 112 directly covers the outer edges 108e1, 108e2 of the active layer 108 and overlies the outer edges 108e1, 108e2 of the active layer 108. In still other embodiments, the maximum width of the cap structure 112 is greater than the maximum width of the image sensor element 106.

In some embodiments, during fabrication of the image sensor 100, a silicide layer (not shown) may be formed within the cap structure 112 to facilitate electrical connection between conductive contacts (not shown) and photodetector regions and/or layers (not shown) disposed within the active layer 108. Forming the silicide layer may include depositing a conductive layer (e.g., comprising nickel) over the cap structure 112 and performing an annealing process to form a silicide layer (e.g., comprising nickel silicide (NiSi)) within the cap structure 112. Subsequently, a removal process (e.g., a wet etching process) is performed on the cap structure 112 to remove excess material that is not converted into a silicide layer from the conductive layer. The removal process includes exposing the substrate 102 and the cap structure 112 to one or more etchants, such as hydrogen peroxide (e.g., H)₂O₂)). Since the cap structure 112 covers the outer edges 108e1, 108e2 of the active layer 108, the one or more etchants may not reach the active layer 108 and/or react with the active layer 108 during the removal process. This, in turn, may mitigate damage to the active layer 108 by the one or more etchants, thereby improving performance of the image sensor 100. In still other embodiments, another silicide layer (not shown) may be formed within the substrate 102 such that the cap structure 112 protects the active layer during formation of the other silicide layer.

Fig. 2A illustrates a cross-sectional view of an image sensor 200a according to some alternative embodiments of the image sensor 100 of fig. 1.

In some embodiments, image sensor 200a includes substrate 102, where substrate 102 includes protrusions 102p disposed laterally adjacent to image sensor elements 106. The top surface of the protrusion 102p is located above the top surface of the image sensor element 106 in the vertical direction. In still other embodiments, the cap structure 112 and the dielectric layer 114 overlie the protrusion 102p and conform to the shape of the protrusion 102 p. A height h1 of the active layer 108 is defined between the backside surface 102b of the substrate 102 and the top surface of the active layer 108, and a height h2 of the buffer layer 110 is defined between the backside surface 102b of the substrate 102 and the top surface of the buffer layer 110. In some embodiments, height h1 is less than height h 2.

Fig. 2B illustrates a cross-sectional view of an image sensor 200B according to some alternative embodiments of the image sensor 200a of fig. 2A.

In some embodiments, the image sensor 200b includes a top cover structure 112 overlying the active layer 108. The active layer 108 includes a curved upper surface 108us such that the cap structure 112 includes a protrusion that contacts the curved upper surface 108us of the active layer 108. The curved upper surface 108us of the active layer 108 is disposed below the top surface of the active layer 108.

Fig. 2C shows a cross-sectional view of an image sensor 200C according to some alternative embodiments of the image sensor 200a of fig. 2A.

In some embodiments, the image sensor 200c includes an oxide layer 202 disposed between a portion of the active layer 108 and the top cap structure 112. Further, an oxide layer 202 is disposed between the buffer layer 110 and the cap structure 112. In some embodiments, the oxide layer 202 may be or include an oxide of a second material (e.g., germanium oxide (e.g., GeO)₂) ) or another material. The oxide layer 202 may extend from the top surface of the buffer layer 110 to the curved upper surface 108us of the active layer 108 along the sidewalls of the buffer layer 110.

Fig. 2D illustrates a cross-sectional view of an image sensor 200D according to some alternative embodiments of the image sensor 200a of fig. 2A.

The image sensor 200d includes a top cover structure 112 overlying the active layer 108. In some embodiments, the cap structure 112 includes a plurality of protrusions 112p, wherein the protrusions 112p each overlie an edge and/or a sidewall of the active layer 108. The dielectric layer 114 extends continuously along the protrusion 112p of the cap structure 112. The protrusion 112p may directly overlie the oxide layer 202. In still other embodiments, the oxide layer 202 may be omitted (not shown).

Fig. 2E illustrates a cross-sectional view of an image sensor 200E according to some alternative embodiments of the image sensor 200D of fig. 2D, wherein the outer sidewall of the cap structure 112 is laterally offset from the sidewall of the image sensor element 106 by one or more non-zero distances. Thus, in some embodiments, the width of the cap structure 112 is greater than the width of the image sensor element 106. In still other embodiments, the oxide layer 202 may be omitted (not shown).

Fig. 3A illustrates a cross-sectional view of some embodiments of an integrated chip 300a, the integrated chip 300a including an interconnect structure 302 overlying the substrate 102.

The interconnect structure 302 is disposed along the frontside surface 102f of the substrate 102 and an anti-reflective coating (ARC) structure 314 is disposed along the backside surface 102b of the substrate 102. In some embodiments, the substrate 102 may be or include, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, crystalline silicon, P-type doped silicon, or another suitable material. Thus, the substrate 102 may comprise a first material, such as, for example, silicon. Interconnect structure 302 includes dielectric structure 116, conductive contact 303, plurality of vias 306, and plurality of conductive lines 304. In some embodiments, the interconnect structure 302 may be or include, for example, silicon dioxide, a low-k dielectric material, a very low-k dielectric material, another material, or any combination thereof. In still other embodiments, the conductive contacts 303, the plurality of vias 306, and/or the plurality of conductive lines 304 may be, for example, each or comprise aluminum, copper, ruthenium, tungsten, titanium nitride, tantalum nitride, another suitable material, or any combination of the foregoing. The interconnect structure 302 is configured to electrically couple doped regions and/or semiconductor devices disposed within the integrated chip 300a to each other. Further, a dielectric layer 114 is disposed between the substrate 102 and the dielectric structure 116. In some embodiments, the dielectric layer 114 may be or include, for example, an oxide (e.g., silicon dioxide), another suitable material, or any combination of the preceding.

Image sensor elements 106 are disposed within the substrate 102 and the image sensor elements 106 include an active layer 108 and a buffer layer 110. The buffer layer 110 is disposed between the active layer 108 and the substrate 102. The image sensor elements 106 are configured to generate electrical signals from Infrared (IR) radiation (e.g., electromagnetic radiation having a wavelength in a range of about 700 nanometers (nm) to about 2,500 nm), for example. It should be understood that it is within the scope of the present disclosure for image sensor element 106 to be configured to generate electrical signals from other frequency wavelength values. In some embodiments, the active layer 108 may be or include a second material (e.g., germanium), or another suitable material, for example. In still other embodiments, the buffer layer 110 is composed of a first material (e.g., silicon) and a second material (e.g., germanium) such that the concentration of the first material continuously decreases from the inner surface of the substrate 102 to the outer surface of the active layer 108 and the concentration of the second material continuously increases from the inner surface of the substrate 102 to the outer surface of the active layer 108.

A first isolation structure 104 is provided within the substrate 102 and the first isolation structure 104 laterally surrounds the image sensor element 106. The first isolation structure 104 extends from the front side surface 102f of the substrate 102 to a point below the front side surface 102f of the substrate 102. The first isolation structure 104 is configured to electrically isolate the image sensor element 106 from other devices disposed on the substrate 102 and/or within the substrate 102. In some embodiments, the first isolation structure 104 is configured as a Shallow Trench Isolation (STI) structure or another suitable isolation structure. In still other embodiments, the first isolation structure 104 may be or include, for example, an oxide (e.g., silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide), another dielectric material, or any combination thereof.

Further, a top cover structure 112 is coated on the front side surface 102f of the substrate 102 and the top cover structure 112 is disposed between the image sensor element 106 and the dielectric layer 114. The outer sidewalls of the image sensor elements 106 are laterally spaced between the sidewalls of the cap structure 112. Thus, the cap structure 112 extends continuously over the top surface of the active layer 108 and the buffer layer 110. In some embodiments, the cap structure 112 may be or include, for example, a first material (e.g., silicon), epitaxial silicon, amorphous silicon, crystalline silicon, a high-k dielectric material (e.g., aluminum oxide, hafnium oxide), another suitable material, or any combination of the foregoing. The cap structure 112 is configured to protect the active layer 108 from one or more etchants used during fabrication of the integrated chip 300a, thereby increasing the reliability, durability, and performance of the image sensor element 106. In addition, a silicide layer 301 is disposed within the capping structure 112. The silicide layer 301 is configured to electrically couple the conductive contacts 303 to photodetector regions and/or layers (not shown) disposed within the active layer 108. In some embodiments, the silicide layer 301 may be or include, for example, nickel silicide, titanium silicide, another material, or any combination of the foregoing. In still other embodiments, the thickness of the silicide layer 301 may be equal to the thickness of the cap structure 112.

The second isolation structure 308 extends from the backside surface 102b of the substrate 102 to a point above the backside surface 102b of the substrate 102. In some embodiments, a top surface of the second isolation structure 308 may contact a bottom surface of the first isolation structure 104. The second isolation structure 308 laterally surrounds the image sensor element 106 and is configured to electrically isolate the image sensor element 106 from other devices disposed within the substrate 102 and/or on the substrate 102. In some embodiments, the second isolation structure 308 is configured as a Deep Trench Isolation (DTI) structure or another suitable isolation structure. The second isolation structure 308 includes a passivation layer 310 and a trench layer 312. In some embodiments, the passivation layer 310 may be or include, for example, a dielectric material (e.g., silicon dioxide, silicon oxynitride, silicon oxycarbide), another material, or any combination of the foregoing materials. Further, the passivation layer 310 may extend continuously along the backside surface 102b of the substrate 102. A passivation layer 310 is disposed between the substrate 102 and the trench layer 312. In some embodiments, the trench layer 312 may be or include aluminum, tungsten, copper, another material, or any combination of the preceding, for example. In still other embodiments, the second isolation structure 308 may be configured to direct the electromagnetic radiation 120 towards the image sensor element 106. In such embodiments, electromagnetic radiation 120 may be reflected from the sidewalls of trench layer 312 to image sensor element 106, rather than electromagnetic radiation 120 traveling to an adjacent image sensor element (not shown). In such embodiments, the second isolation structures 308 may reduce cross-talk between adjacent image sensor elements, thereby improving the performance of the integrated chip 300 a.

ARC structure 314 is disposed along backside surface 102b of substrate 102 and is configured to reduce reflection of electromagnetic radiation 120 away from substrate 102, thereby improving performance of integrated chip 300 a. A grid structure 316 is located below the ARC structure 314. The grid structure 316 may, for example, comprise a metal grid structure and/or a dielectric grid structure. The grid structure 316 is configured to direct the electromagnetic radiation 120 to the image sensor element 106. In some embodiments, when grid structure 316 comprises a metal grid structure (e.g., aluminum, copper, tungsten, another material, or any combination of the foregoing materials), electromagnetic radiation 120 may be reflected from the sidewalls of the metal grid structure to image sensor elements 106 rather than traveling to adjacent image sensor elements (not shown). In such embodiments, the grid structure 316 may reduce cross-talk between adjacent image sensor elements, thereby improving the performance of the integrated chip 300 a.

Additionally, a filter 318 (e.g., a color filter, an IR filter, etc.) is located below the ARC structure 314 and laterally disposed between sidewalls of the grid structure 316. Filter 318 is configured to transmit incident radiation of a particular wavelength. For example, filter 318 may transmit radiation having a wavelength within a first range while blocking radiation having a wavelength within a second range different from the first range. Further, a microlens 320 is disposed under the filter 318 and the grid structure 316. The microlenses 320 are configured to focus the electromagnetic radiation 120 toward the substrate 102, thereby increasing the QE of the image sensor elements 106.

Fig. 3B illustrates a cross-sectional view of some embodiments of an integrated chip 300B corresponding to some alternative embodiments of integrated chip 300a of fig. 3A.

The substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, P-doped silicon, N-doped silicon, or another suitable material. In some embodiments, the substrate 102 is lightly doped with a dopant of a first conductivity type (e.g., p-type). In various embodiments, the image sensor elements 106 are configured as Single Photon Avalanche Diodes (SPADs) that can detect incident radiation (e.g., single photons) with very low intensities. In still other embodiments, the image sensor element 106 may be used, for example, in an IR direct-time of flight (D-TOF) application. In some embodiments, the active layer 108 is lightly doped with a dopant of a first conductivity type (e.g., p-type). In still other embodiments, the active layer 108 includes a first deep well 326 of a first conductivity type and a first heavily doped region 324 of a second conductivity type (e.g., n-type) opposite the first conductivity type. A first deep well 326 is disposed below the first heavily doped region 324. A multiplication junction region (multiplication junction region) is formed at an interface between the first heavily doped region 324 and the first deep well 326. In some embodiments, the first deep well 326 is vertically spaced apart from the first heavily doped region 324 (not shown) such that a multiplication junction region is formed at an interface between the first heavily doped region 324 and the active layer 108.

In some embodiments, the image sensor element 106 further includes a second deep well 322 heavily doped with a dopant of the first conductivity type. The second deep well 322 extends from the front side surface 102f of the substrate 102 to a point below the first heavily doped region 324. The second deep well 322 may be configured as a guard ring to prevent premature edge breakdown (preceding edge breakdown) of the image sensor element 106 in the SPAD configuration. Further, a buffer layer 110 is disposed between the active layer 108 and the substrate 102. The buffer layer 110 may include the same dopant and doping concentration as the active layer 108. In some embodiments, the buffer layer 110 may be omitted such that the active layer 108 directly contacts the substrate 102 (not shown). In some embodiments, the dopant of the first conductivity type is P-type (e.g., boron, some other suitable P-type dopant, or any combination of the foregoing materials), and the dopant of the second conductivity type is N-type (e.g., arsenic, phosphorus, some other suitable N-type dopant, or any combination of the foregoing materials), or vice versa.

In some embodiments, during operation in the SPAD configuration, the image sensor element 106 is reverse biased beyond its own breakdown voltage, and incident photons (e.g., wavelengths within the IR radiation range) strike the image sensor element 106 to generate charge carriers. Photon-generated charge carriers move to the multiplication region and trigger avalanche currents that amplify the photon-generated signals to make them more easily detected. In some embodiments, the doping type and/or concentration of the first deep well 326 may be configured to adjust the breakdown voltage of the image sensor element 106 in a SPAD configuration. A plurality of conductive contacts 303 are directly overlying the image sensor elements 106, and the plurality of conductive contacts 303 are electrically coupled to doped regions within the active layer 108 to facilitate readout of the photon-generated signals. Further, a plurality of silicide layers 301 are disposed within the cap structure 112 between the active layer 108 and the plurality of conductive contacts 303. The silicide layer 301 is configured to facilitate electrical connection between doped regions within the active layer 108 and the conductive contacts 303.

Fig. 4-14 illustrate cross-sectional views 400-1400 of some embodiments of a first method of forming an integrated chip having a cap structure that extends continuously over an outer edge of an image sensor element according to the present disclosure. Although the cross-sectional views 400 through 1400 shown in fig. 4 through 14 are described with reference to the first method, it should be understood that the structures shown in fig. 4 through 14 are not limited to the first method, but may be independent of the first method alone. Moreover, while fig. 4-14 are illustrated as a series of acts, it will be appreciated that the acts are not limited in this regard as the order of acts may be varied in other embodiments and the disclosed methodology may be applied to other configurations. In other embodiments, some acts shown and/or described may be omitted, in whole or in part.

As shown in the cross-sectional view 400 of fig. 4, a substrate 102 is provided and a first isolation structure 104 is formed within the substrate 102. In some embodiments, the substrate 102 may be or include, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate. In still other embodiments, the first isolation structure 104 may be formed by: the substrate 102 is selectively etched to form trenches in the substrate 102, and the trenches are subsequently filled with a dielectric material (e.g., by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or another suitable deposition or growth process). In still other embodiments, the substrate 102 is selectively etched by: a masking layer (not shown) is formed over the front side surface 102f of the substrate 102, and the substrate 102 is subsequently exposed to one or more etchants configured to selectively remove unmasked portions of the substrate 102. In some embodiments, the dielectric material may be or include, for example, an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), another dielectric material, or any combination of the foregoing. In addition, an upper dielectric layer 402 is deposited over the substrate 102. The upper dielectric layer 402 may be or include, for example, silicon dioxide, Undoped Silicon Glass (USG), another suitable material, or any combination of the preceding. In still other embodiments, the upper dielectric layer 402 may be deposited by ALD, CVD, PVD, or another suitable growth or deposition process.

As shown in cross-sectional view 500 of fig. 5, a patterning process is performed on substrate 102 to form an opening 502 within substrate 102. In some embodiments, the patterning process comprises: forming a masking layer (not shown) over the substrate 102; and exposing the substrate 102 to one or more etchants, thereby removing unmasked regions of the substrate 102 and forming openings 502. Subsequently, a removal process may be performed to remove the masking layer. In still other embodiments, the patterning process may include performing a wet etch process, a dry etch process, another suitable etch process, or any combination of the preceding.

As shown in the cross-sectional view 600 of fig. 6, the buffer layer 110 is selectively formed along the sidewall and the lower surface of the substrate 102. In addition, an active structure 602 is selectively formed over the buffer layer 110, thereby filling the opening (502 of fig. 5). In some embodiments, buffer layer 110 and/or active structure 602 may be formed, for example, by molecular-beam epitaxy (MBE), vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), some other suitable epitaxy process, or another suitable growth or deposition process. In still other embodiments, the buffer layer 110 may serve as a seed layer for forming the active structure 602.

In some embodiments, buffer layer 110 may be or include, for example, silicon germanium, another suitable material, or any combination of the preceding. In still other embodiments, the buffer layer 110 is composed of a first material (e.g., silicon) and a second material (e.g., germanium) such that the concentration of the first material continuously decreases from the inner surface of the substrate 102 to the outer surface of the active structure 602 and the concentration of the second material continuously increases from the inner surface of the substrate 102 to the outer surface of the active structure 602. In some embodiments, the active structure 602 may be or include, for example, a second material (e.g., germanium), another suitable material, or any combination of the preceding.

As shown in the cross-sectional view 700 of fig. 7, a planarization process (e.g., a Chemical Mechanical Planarization (CMP) process) is performed on the active structure (602 of fig. 6), thereby forming the active layer 108 and the image sensor elements 106. In some embodiments, during the planarization process, the active structure (602 of fig. 6) is removed faster than the upper dielectric layer 402, such that the top surface of the active layer 108 is disposed below the top surface of the upper dielectric layer 402. In addition, a planarization process may be performed such that the top surface of the active layer 108 is aligned with the front side surface 102f of the substrate 102. Additionally, forming image sensor elements 106 may include performing one or more formation processes (e.g., including selective ion implantation processes, or other suitable processing steps) to define well regions, doped regions, or other suitable regions and/or structures within active layer 108. For example, the one or more formation processes may be performed to form the second deep well 322, the first heavily doped region 324, and/or the first deep well 326 of fig. 3B in the active layer 108.

As shown in the cross-sectional view 800 of fig. 8, an etch-back process is performed on the upper dielectric layer 402, thereby removing a portion of the upper dielectric layer 402 from the front-side surface 102f of the substrate 102. In some embodiments, the etch-back process includes performing a wet etch process and/or exposing the structure of fig. 7 to one or more etchants, and forming a masking layer (not shown) over the upper dielectric layer 402. The one or more etchants can be, for example, or include hydrofluoric acid (HF), another etchant, or any combination of the foregoing. During the etch-back process, the upper dielectric layer 402 is etched at a first etch rate, the buffer layer 110 is etched at a second etch rate, and the active layer 108 is etched at a third etch rate. In some embodiments, the first etch rate is greater than the second etch rate and the third etch rate such that the upper dielectric layer 402 is removed faster than the buffer layer 110 and/or the active layer 108 during the etch-back process. For example, the first etch rate may be about 90 angstroms/minute or another suitable value and the third etch rate may be about 1.4 angstroms/minute or another suitable value. In still other embodiments, the third etch rate may be greater than the second etch rate.

In addition, after the etch-back process, a height h1 of the active layer 108 is defined between the backside surface 102b of the substrate 102 and the top surface of the active layer 108, and a height h2 of the buffer layer 110 is defined between the backside surface 102b of the substrate 102 and the top surface of the buffer layer 110. In some embodiments, height h1 is less than height h 2. It should be understood that in some embodiments, the etch-back process of fig. 8 may be omitted and/or skipped, such that the first method may proceed from fig. 4-7 to fig. 9-13 (i.e., skip the processing steps of fig. 8).

As shown in cross-sectional view 900 of fig. 9, a cap structure 112 is formed over the image sensor element 106 and the substrate 102. A cleaning process is performed on the substrate 102, the active layer 108, and the buffer layer 110 prior to forming the cap structure 112. The cleaning process may include exposing the structure of fig. 8 to one or more chemicals to clean (e.g., remove impurities and/or other materials) the surface of the substrate 102, the active layer 108, and the buffer layer 110. The one or more chemicals may be, for example, or include hydrofluoric acid (HF), Deionized (DI) water, another suitable chemical, or any combination of the foregoing. The top cap structure 112 is formed such that the top cap structure 112 continuously extends along the top surface of the active layer 108 and the top surface of the buffer layer 110. Furthermore, the cap structure 112 continuously covers the outer edges of the image sensor element 106 and extends over the outer edges of the image sensor element 106. In some embodiments, the cap structure 112 is formed, for example, by CVD, PVD, ALD, MBE, VPE, LPE, some other suitable epitaxial process, or another suitable growth or deposition process. In some embodiments, the cap structure 112 may be, for example, or include silicon, epitaxial silicon, amorphous silicon, crystalline silicon, a high-k dielectric material (e.g., aluminum oxide, hafnium oxide), another suitable material, or any combination thereof. Subsequently, a removal process is performed to remove the upper dielectric layer 402 (not shown).

As shown in cross-sectional view 1000 of fig. 10, a dielectric layer 114 is formed over the cap structure 112 and the substrate 102. The dielectric layer 114 may be deposited, for example, by CVD, ALD, PVD, or another suitable growth or deposition process. In some embodiments, the dielectric layer 114 may be or include, for example, an oxide (e.g., silicon dioxide), another suitable material, or any combination of the preceding. Subsequently, a thinning process is performed on the backside surface 102b of the substrate 102 to reduce the initial thickness Ti of the substrate 102 to a thickness Ts. A thickness Ts is defined between the front side surface 102f of the substrate 102 and the backside surface 102b of the substrate 102. In some embodiments, the thinning process may include performing a mechanical grinding process, a CMP process, another suitable thinning process, or any combination of the preceding.

As shown in cross-sectional view 1100 of fig. 11, a patterning process is performed on dielectric layer 114 to define an opening 1102. In some embodiments, the patterning process may include: dielectric layer 114 is exposed to one or more etchants according to a photomask (not shown) and/or a masking layer (not shown) to form opening 1102. The opening 1102 may expose an upper surface of the cap structure 112. Subsequently, a silicide layer 301 is formed within the cap structure 112 and the silicide layer 301 directly overlies the active layer 108. In some embodiments, the silicide layer 301 directly overlies and is electrically coupled to a doped region (not shown) of the active layer 108. In still other embodiments, the silicide layer 301 may be or include, for example, nickel silicide, cobalt silicide, titanium silicide, another suitable material, or any combination of the foregoing materials.

In still other embodiments, the process of forming the silicide layer 301 includes: depositing (e.g., by sputtering, electroless plating, electroplating, PVD, CVD, or another suitable growth or deposition process) a conductive layer (e.g., comprising nickel, titanium, cobalt, or another conductive material) over the cap structure 112, filling the opening 1102; performing a rapid thermal anneal on the conductive layer to form a silicide layer 301 within the cap structure 112; and a removal process (e.g., a wet etching process) is performed to remove material that is not converted into the silicide layer 301 from the conductive layer.The removal process includes exposing the structure of fig. 11 to one or more reactive etchants (e.g., hydrogen peroxide (e.g., H)₂O₂)). In some embodiments, if the one or more reactive etchants are in contact with the second material (e.g., germanium) of the active layer 108, it may form a compound of the second material and the reactive etchant. The compound may tend to diffuse from the active layer 108 to adjacent structures and/or layers. In such embodiments, the diffusion of the compound may result in the formation of voids within the active layer 108, thereby reducing the structural integrity and/or performance of the image sensor element 106. The compound may, for example, be or comprise germanium oxide (GeO)₂)、H₂GeO₃Another chemical compound, or any combination of the foregoing. Since the cap structure 112 extends continuously over and covers the outer edges of the active layer 108 and the buffer layer 110, the one or more reactive etchants may not reach the active layer 108 and/or react with the active layer 108 during the removal process. This, in turn, mitigates the formation of voids within the active layer 108, thereby increasing the durability, reliability, and overall performance of the image sensor element 106.

It is to be understood that one or more additional silicide layers (not shown) may be formed within the substrate 102 such that the cap structure 112 is configured to protect the active layer 108 during formation of the one or more additional silicide layers. In still other embodiments, the formation of the silicide layer 301 within the cap structure 112 may be omitted.

As shown in the cross-sectional view 1200 of fig. 12, the interconnect structure 302 is formed over the front side surface 102f of the substrate 102. The interconnect structure includes a dielectric structure 116, a conductive contact 303, a plurality of conductive wires 304, and a plurality of vias 306. In some embodiments, the dielectric structure 116 may be or include, for example, an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride), a low-k dielectric material, another suitable dielectric material, or any combination of the preceding. The dielectric structure 116 may be formed by one or more deposition processes (e.g., CVD, PVD, ALD, or another suitable deposition or growth process). The conductive contacts 303, the plurality of conductive wires 304, and/or the plurality of vias 306 may be formed, for example, by a single damascene process, a dual damascene process, or another suitable formation process. In some embodiments, the conductive contact 303, the plurality of conductive wires 304, and/or the plurality of vias 306 may be, for example, each or may comprise aluminum, copper, titanium nitride, tantalum nitride, ruthenium, another conductive material, or any combination thereof. In still other embodiments, conductive contacts 303 overlie the silicide layer 301 and are electrically coupled to the image sensor elements 106 through the silicide layer 301.

As shown in cross-sectional view 1300 of fig. 13, the structure of fig. 12 is flipped over and second isolation structures 308 are formed into backside surface 102b of substrate 102. In various embodiments, the second isolation structure 308 may be configured as a Deep Trench Isolation (DTI) structure and/or may include a passivation layer 310 and a trench layer 312. In some embodiments, the process of forming the second isolation structure 308 includes: patterning the backside surface 102b of the substrate 102, thereby forming DTI openings (not shown) extending into the backside surface 102b of the substrate; depositing (e.g., by CVD, PVD, ALD, or another suitable deposition or growth process) a passivation layer 310 over the substrate 102, lining the DTI openings; depositing (e.g., by CVD, PVD, electroless plating, sputtering, electroplating, or another suitable deposition or growth process) a trench material (e.g., aluminum, tungsten, copper, another material, or any combination of the foregoing) over the backside surface 102b of the substrate, thereby filling the DTI openings; and performing a planarization process into the trench material, thereby forming the trench layer 312 and the second isolation structure 308. In some embodiments, the passivation layer 310 may be or include a dielectric material, such as silicon dioxide, silicon oxynitride, silicon oxycarbide, another suitable dielectric material, or any combination of the foregoing.

As shown in cross-sectional view 1400 of fig. 14, an anti-reflective coating (ARC) structure 314 is formed over the backside surface 102b of the substrate 102. In some embodiments, ARC structure 314 may be deposited, for example, by CVD, PVD, ALD, or another suitable deposition or growth process. In addition, a grid structure 316 is formed over ARC structure 314. The grid structure 316 may comprise a metal grid structure and/or a dielectric grid structure. In some embodiments, the metal grid structure and/or the dielectric grid structure may be formed by, for example, CVD, PVD, ALD, sputtering, electroless plating, or another suitable deposition or growth process. Furthermore, after depositing the metal grid structure and/or the dielectric grid structure, a patterning process is performed on the metal grid structure and/or the dielectric grid structure to define openings directly overlying the image sensor elements 106. Subsequently, a filter 318 (e.g., a color filter, an IR filter, etc.) is formed within the opening and over the ARC structure 314. Filter 318 is formed of a material that allows transmission of incident electromagnetic radiation (e.g., light) having a particular range of wavelengths while blocking incident wavelengths having another wavelength outside the particular range. In still other embodiments, the filter 318 can be formed by CVD, PVD, ALD, sputtering, etc., and/or can be planarized after formation (e.g., by a Chemical Mechanical Planarization (CMP) process). In addition, a microlens 320 is formed over the filter 318 and the grid structure 316. In some embodiments, the microlenses 320 can be formed by depositing (e.g., by CVD, PVD, etc.) a lens material on the filters 318. A lens template (not shown) having a curved upper surface is patterned over the lens material. The microlenses 320 are then formed by selectively etching the lens material according to a lens template.

Fig. 15-17B illustrate cross-sectional views 1500-1700B of some embodiments of a second method of forming an integrated chip having a cap structure that extends continuously over an outer edge of an image sensor element according to the present disclosure. Although the cross-sectional views 1500 through 1700B shown in fig. 15 through 17B are described with reference to the second method, it is to be understood that the structure shown in fig. 15 through 17B is not limited to the second method, but may be independently of the second method. Further, while fig. 15-17B are illustrated as a series of acts, it will be appreciated that the acts are not so limited, as the order of acts may be varied in other embodiments and the disclosed methods are applicable to other configurations. In other embodiments, some acts shown and/or described may be omitted, in whole or in part.

The second method of fig. 15-17B may illustrate some alternative embodiments of the first method of fig. 4-14. For example, fig. 15-17B show cross-sectional views 1500-1700B of some embodiments of actions that may be performed in place of the actions at fig. 8-9, such that the first method of fig. 4-16 may alternatively proceed from fig. 4-7 to fig. 15-17B and then from fig. 17A or 17B to fig. 10-14 (jump fig. 8-9).

As shown in cross-sectional view 1500 of fig. 15, an oxide layer 202 may be formed along the upper surface 108us of the active layer 108. In some embodiments, the upper surface 108us may be curved and may be formed as a result of the planarization process performed in fig. 7. In still other embodiments, the oxide layer 202 may extend from the top surface of the buffer layer 110 to the upper surface 108us of the active layer 108 along the sidewalls of the buffer layer 110. In some embodiments, the oxide layer 202 may be or include an oxide of a second material (e.g., germanium oxide (e.g., GeO)₂) Or another material).

As shown in cross-sectional view 1600 of fig. 16, a removal process is performed to remove the oxide layer (202 of fig. 15). In some embodiments, the removal process includes exposing the structure of fig. 15 to one or more etchants (e.g., H) configured to remove the oxide layer (202 of fig. 15)₂O₂). In still other embodiments, the removal process may include utilizing a chemistry (e.g., hydrogen (H) configured to remove the oxide layer (202 of fig. 15)₂) A baking process is performed on the structure of fig. 15. Accordingly, the removal process is configured to remove the oxide layer (202 of fig. 15) from the upper surface 108us of the active layer 108.

As shown in the cross-sectional view 1700a of fig. 17A, a cap structure 112 is formed over the active layer 108 and the substrate 102. The top cover structure 112 is formed such that the top cover structure 112 continuously extends along the top surface of the active layer 108 and covers the outer edges of the active layer 108. In some embodiments, the cap structure 112 is formed, for example, by CVD, PVD, ALD, MBE, VPE, LPE, some other suitable epitaxial process, or another suitable growth or deposition process. Subsequently, a removal process may be performed to remove the upper dielectric layer 402 (not shown).

Fig. 17B illustrates a cross-sectional view 1700B of some alternative embodiments of the processing step of cross-sectional view 1700a of fig. 17A. As shown in the cross-sectional view 1700B of fig. 17B, the cap structure 112 can be formed such that the cap structure 112 includes a protrusion 112p directly overlying an outer edge of the active layer 108. For example, the cap structure 112 may be formed by CVD, PVD, ALD, MBE, VPE, LPE, some other suitable epitaxial process, or another suitable growth or deposition process.

Fig. 18 illustrates a method 1800 of forming an image sensor including a capping structure along an image sensor element according to the present disclosure. While method 1800 is illustrated and/or described as a series of acts or events, it will be appreciated that method 1800 is not limited by the illustrated ordering or acts. Thus, in some embodiments, the acts may be performed in an order different than that shown, and/or may be performed simultaneously. Further, in some embodiments, illustrated acts or events may be sub-divided into multiple acts or events, which may be performed at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other acts or events not illustrated may be included.

At act 1802, a first isolation structure is formed into a front side of a substrate, wherein the substrate comprises a first material. Fig. 4 illustrates a cross-sectional view 400 corresponding to some embodiments of act 1802.

At act 1804, an image sensor element is formed in a substrate, wherein the image sensor element includes an active layer and a buffer layer, the active layer including a second material different from the first material. The buffer layer is disposed between the active layer and the substrate. Figures 5 through 8 illustrate cutaway 500 through cutaway 800, corresponding to some embodiments of act 1804.

At act 1806, a cap structure is formed over the image sensor element and the substrate such that the cap structure extends continuously over the top surface and outer edges of the active layer. Fig. 9 illustrates a cross-sectional view 900 corresponding to some embodiments of act 1806. Fig. 17A and 17B illustrate a cross-sectional view 1700a and a cross-sectional view 1700B corresponding to some alternative embodiments of act 1806.

At act 1808, one or more silicide layers are formed within the substrate and/or within the cap structure. Fig. 11 illustrates a cross-sectional view 1100 corresponding to some embodiments of act 1808.

At act 1810, an interconnect structure is formed over a front side of a substrate. Fig. 12 illustrates a cut-away view 1200 corresponding to some embodiments of act 1810.

At act 1812, an anti-reflective coating (ARC) structure is formed over the backside of the substrate. Figure 14 illustrates a cross-sectional view 1400 that corresponds to some embodiments of act 1812.

At act 1814, a filter is formed over the ARC structure and a microlens is formed over the filter. Figure 14 illustrates a cross-sectional view 1400 that corresponds to some embodiments of act 1814.

Accordingly, in some embodiments, the present disclosure relates to an image sensor element disposed within a substrate, wherein the image sensor element comprises an active layer. The cap structure extends continuously over the top surface of the active layer and overlies the outer edges of the active layer.

In some embodiments, the present application provides an image sensor comprising: a substrate comprising a first material; an image sensor element disposed within the substrate, wherein the image sensor element comprises an active layer comprising a second material different from the first material; a buffer layer disposed between the active layer and the substrate, wherein the buffer layer extends along outer sidewalls and a bottom surface of the active layer; and a cap structure overlying the active layer, wherein the outer sidewalls of the active layer are laterally spaced apart between outer sidewalls of the cap structure such that the cap structure extends continuously over an outer edge of the active layer.

In some other embodiments, in the image sensor, a maximum width of the cap structure is greater than a maximum width of the active layer.

In some other embodiments, in the image sensor, wherein the cap structure comprises the first material.

In some other embodiments, in the image sensor, wherein the first material is silicon and the second material is germanium.

In some other embodiments, in the image sensor, wherein a width of the active layer continuously decreases in a direction extending from a bottom surface of the top cap structure to a bottom surface of the buffer layer.

In some other embodiments, in the image sensor, further comprising: a dielectric layer disposed over the cap structure and the substrate, wherein the dielectric layer extends continuously from a top surface of the substrate to a top surface of the cap structure along sidewalls of the cap structure.

In some other embodiments, in the image sensor, wherein the top cap structure comprises a protrusion extending below a top surface of the active layer and contacting an upper surface of the active layer, wherein the upper surface of the active layer is curved.

In some other embodiments, in the image sensor, further comprising: a silicide layer disposed within the cap structure, wherein the silicide layer comprises a silicide of the first material and a conductive material, wherein the silicide layer directly overlies and is electrically coupled to the active layer.

In some other embodiments, in the image sensor, further comprising: an interconnect structure overlying the substrate, wherein the interconnect structure comprises a conductive contact directly overlying the cap structure and electrically coupled to the active layer through the silicide layer. In some embodiments, the present application provides an integrated chip comprising: a substrate comprising a first material, wherein the substrate comprises opposing sidewalls and a lower surface defining a trench extending into a frontside surface of the substrate; an active layer disposed within the trench, wherein the active layer comprises a second material different from the first material; a buffer layer lining the trench such that the buffer layer is disposed between the substrate and the trench, wherein the buffer layer comprises a compound of the first material and the second material; a cap structure extending continuously over the active layer and the buffer layer, wherein the cap structure directly overlies the opposing sidewalls of the substrate that define the trench, wherein the cap structure includes the first material; and a silicide layer disposed within the cap structure.

In some other embodiments, the integrated chip further comprises: an interconnect structure overlying the frontside surface of the substrate, wherein the interconnect structure comprises a plurality of vias and a plurality of conductive wires disposed within a dielectric structure, wherein the vias and the conductive wires are electrically coupled to the active layer through the silicide layer.

In some other embodiments, in the integrated chip, wherein a doped region is disposed within the active layer, wherein the silicide layer directly overlies and is electrically coupled to the doped region.

In some other embodiments, in the integrated chip, wherein the substrate comprises a crystalline form of the first material and the cap structure comprises an amorphous form of the first material.

In some other embodiments, in the integrated chip, a top surface of the active layer is vertically below a top surface of the buffer layer, and the top surface of the buffer layer is vertically below the front side surface of the substrate.

In some other embodiments, in the integrated chip, the top cap structure extends continuously from the front side surface of the substrate along a top surface of the buffer layer to a top surface of the active layer.

In some other embodiments, the integrated chip further comprises: an oxide layer disposed between the cap structure and the active layer, wherein the oxide layer comprises an oxide of the second material.

In some embodiments, the present application provides a method of forming an image sensor, the method comprising: forming a dielectric layer along a surface of a substrate, wherein the substrate comprises a first material; etching the dielectric layer and the substrate to define a trench in the substrate; forming a buffer layer in the trench such that the dielectric layer contacts the buffer layer; forming an active layer within the trench, wherein the active layer comprises a second material different from the first material; and forming a cap structure over the active layer such that the cap structure extends continuously along a top surface of the active layer, wherein the cap structure comprises the first material, and wherein the cap structure directly overlies an uppermost edge of the active layer.

In some other embodiments, the method further comprises: performing an etch-back process on the dielectric layer such that the dielectric layer is laterally offset from the buffer layer by a non-zero distance, wherein the dielectric layer etches faster than the active layer during the etch-back process.

In some other embodiments, in the method, the cap structure, the active layer, and the buffer layer are each formed by an epitaxial process.

In some other embodiments, the method further comprises: forming a silicide layer within the cap structure such that the silicide layer directly overlies the active layer, wherein the silicide layer comprises a compound of the first material and a conductive material.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. An image sensor, comprising:

a substrate comprising a first material;

an image sensor element disposed within the substrate, wherein the image sensor element comprises an active layer comprising a second material different from the first material;

a buffer layer disposed between the active layer and the substrate, wherein the buffer layer extends along outer sidewalls and a bottom surface of the active layer; and

a cap structure overlying the active layer, wherein the outer sidewalls of the active layer are laterally spaced apart between outer sidewalls of the cap structure such that the cap structure extends continuously over outer edges of the active layer.

2. The image sensor of claim 1, wherein a maximum width of the cap structure is greater than a maximum width of the active layer.

3. The image sensor of claim 1, wherein a width of the active layer continuously decreases in a direction extending from a bottom surface of the top cap structure to a bottom surface of the buffer layer.

4. The image sensor of claim 1, wherein the cap structure comprises a protrusion extending below a top surface of the active layer and contacting an upper surface of the active layer, wherein the upper surface of the active layer is curved.

5. The image sensor of claim 1, further comprising:

a silicide layer disposed within the cap structure, wherein the silicide layer comprises a silicide of the first material and a conductive material, wherein the silicide layer directly overlies and is electrically coupled to the active layer.

6. An integrated chip, comprising:

a substrate comprising a first material, wherein the substrate comprises opposing sidewalls and a lower surface defining a trench extending into a frontside surface of the substrate;

an active layer disposed within the trench, wherein the active layer comprises a second material different from the first material;

a buffer layer lining the trench such that the buffer layer is disposed between the substrate and the trench, wherein the buffer layer comprises a compound of the first material and the second material;

a cap structure extending continuously over the active layer and the buffer layer, wherein the cap structure overlies the opposing sidewalls of the substrate defining the trench, wherein the cap structure includes the first material; and

a silicide layer disposed within the cap structure.

7. The integrated chip of claim 6, further comprising:

an interconnect structure overlying the frontside surface of the substrate, wherein the interconnect structure comprises a plurality of vias and a plurality of conductive wires disposed within a dielectric structure, wherein the vias and the conductive wires are electrically coupled to the active layer through the silicide layer.

8. The integrated chip of claim 6, wherein a top surface of the active layer is vertically below a top surface of the buffer layer, and the top surface of the buffer layer is vertically below the frontside surface of the substrate.

9. The integrated chip of claim 6, wherein the cap structure extends continuously from the frontside surface of the substrate along a top surface of the buffer layer to a top surface of the active layer.

10. A method of forming an image sensor, comprising:

forming a dielectric layer along a surface of a substrate, wherein the substrate comprises a first material;

etching the dielectric layer and the substrate to define a trench in the substrate;

forming a buffer layer in the trench such that the dielectric layer contacts the buffer layer;

forming an active layer within the trench, wherein the active layer comprises a second material different from the first material; and

forming a cap structure over the active layer such that the cap structure extends continuously along a top surface of the active layer, wherein the cap structure comprises the first material, and wherein the cap structure overlies an uppermost edge of the active layer.