CN113314518B - Motor H bridge driving circuit chip layout - Google Patents
Motor H bridge driving circuit chip layout Download PDFInfo
- Publication number
- CN113314518B CN113314518B CN202010120611.5A CN202010120611A CN113314518B CN 113314518 B CN113314518 B CN 113314518B CN 202010120611 A CN202010120611 A CN 202010120611A CN 113314518 B CN113314518 B CN 113314518B
- Authority
- CN
- China
- Prior art keywords
- hvnw
- nbl
- driving circuit
- bridge driving
- motor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002955 isolation Methods 0.000 claims description 54
- 238000010586 diagram Methods 0.000 description 14
- 230000003071 parasitic effect Effects 0.000 description 11
- 239000000758 substrate Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000004804 winding Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Control Of Direct Current Motors (AREA)
Abstract
A motor H bridge driving circuit chip layout is characterized in that a low side area of an H bridge driving circuit is arranged at the far end of other circuit module areas in the layout, and a high side area of the H bridge driving circuit is arranged at the near end of the other circuit module areas, so that the influence of negative pressure at a low side drain electrode end caused by inductance follow current after motor abrupt change from running to sliding can be weakened, negative pressure can be isolated by arranging a plurality of NBL+HVNW isolating rings or isolating layers, and the work stability of a chip can be guaranteed.
Description
Technical Field
The invention relates to a motor driving circuit chip layout technology, in particular to a motor H-bridge driving circuit chip layout, wherein a low side area of an H-bridge driving circuit is arranged at the far end of other circuit module areas in the layout, and a high side area of the H-bridge driving circuit is arranged at the near end of other circuit module areas, so that the negative pressure influence of a low side drain electrode end caused by the follow current of an inductance after motor suddenly changes from running to sliding can be weakened, and the negative pressure can be isolated by arranging a plurality of NBL+HVNW isolating rings or isolating layers, thereby being beneficial to guaranteeing the working stability of chips.
Background
Fig. 1 is a schematic diagram of a typical H-bridge driver-level chip circuit for motor-driven products. As shown in fig. 1, mp1 and Mp2 are High-side (PMOS tubes), and Mn1 and Mn2 are Low-side (NMOS tubes); when Mp1, mn2 or Mp2, mn1 is opened, the motor is in a running state; when Mp1, mp2, mn1, mn2 are all off, the motor coast state is reached. As shown in fig. 1, when the motor is in an operating state, a current Iload exists in the motor winding coil, and at this time, the motor winding coil immediately enters a sliding state, and since the inductor current Iload cannot be suddenly changed, iload needs to freewheel to VCC through the body diode D2 of Mp2 (i.e., raise the point OUT2 potential, VOUT2> vcc+vdiod), and freewheel to GND through the body diode D3 of Mn1 (i.e., pull the point OUT1 potential low, VOUT1< GND-Vdiod). It can be seen that, due to existence of the follow current, overvoltage and negative voltage may occur in the output stage OUT potential, that is, negative voltage may occur in the Drain end of the N-type of the Low-side, at this time, parasitic NPN triode Qn1 is formed together with other surrounding N-type devices and PSUB (P-type substrate) (as shown in fig. 2, the surrounding N-type device n+ is a collector, the PSUB end is a base, and the Drain end of the Low-side is an emitter), that is, the surrounding N-type device leaks electricity to OUT, the potential of itself is pulled down, and thus malfunction occurs, and in the whole chip Die, the layout area of the output stage is the largest, if no processing is performed, the negative voltage has a great influence on the surrounding devices, especially, in order to pursue Low power consumption, the branch current is smaller and smaller (nA-level), and the chip cannot work normally. The inventor considers that if the low side region of the H-bridge driving circuit is arranged at the far end of the other circuit module region and the high side region of the H-bridge driving circuit is arranged at the near end of the other circuit module region in the layout, the influence of the negative pressure of the low side drain electrode end caused by the inductance follow current after the motor suddenly changes from running to sliding (for example, devices around the drain electrode end cannot normally work due to negative pressure leakage current) is weakened, and the negative pressure is isolated by arranging a plurality of NBL+HVNW isolating rings or isolating layers, so that the working stability of the chip is ensured. In view of this, the present inventors have completed the present invention.
Disclosure of Invention
Aiming at the defects or shortcomings in the prior art, the invention provides a layout of a motor H-bridge driving circuit chip, wherein the low side area of the H-bridge driving circuit is arranged at the far end of other circuit module areas in the layout, and the high side area of the H-bridge driving circuit is arranged at the near end of other circuit module areas, so that the negative pressure influence of the low side drain end caused by the follow current of an inductance after the motor suddenly changes from running to sliding can be weakened, and the negative pressure can be isolated by arranging a plurality of NBL+HVNW isolating rings or isolating layers, thereby being beneficial to ensuring the working stability of the chip.
The technical scheme of the invention is as follows:
the motor H-bridge driving circuit chip layout is characterized by comprising an H-bridge driving circuit high side area, an H-bridge driving circuit low side area and other circuit module areas, wherein the H-bridge driving circuit low side area is positioned at the far ends of the other circuit module areas, and the H-bridge driving circuit high side area is positioned at the near ends of the other circuit module areas.
The H bridge driving circuit low side region comprises a left half first NMOS tube and a right half second NMOS tube, and the first NMOS tube and the second NMOS tube are respectively surrounded by two first NBL+HVNW isolation rings in a one-to-one mode. And the first NBL+HVNW isolation ring is connected with a fixed strong source grounding end.
And a second NBL+HVNW isolation layer is arranged between the low side region of the H bridge driving circuit and the high side region of the H bridge driving circuit, and the second NBL+HVNW isolation layer is connected with a fixed strong source grounding end.
The H bridge driving circuit high side region comprises a left half first PMOS tube and a right half second PMOS tube, the first PMOS tube and the second PMOS tube are respectively surrounded by two third NBL+HVNW isolating rings in a one-to-one mode, and the third NBL+HVNW isolating rings are connected with a power supply voltage end.
And a fourth NBL+HVNW isolation layer is arranged between the high side region of the H-bridge driving circuit and the other circuit module regions, and the fourth NBL+HVNW isolation layer is connected with a power supply voltage end.
The other circuit block region includes a left half high voltage device surrounded by a high voltage device nbl+hvnw isolation ring and a right half low voltage device surrounded by a low voltage device nbl+hvnw isolation ring, the high voltage device nbl+hvnw isolation ring being connected to a relatively strong source to protect the branch current, the low voltage device nbl+hvnw isolation ring being connected to a relatively strong source to protect the internal devices.
The geometric center of the H-bridge driving circuit is provided with a fourth temperature-sensing PNP triode.
And a fourth temperature-sensing PNP triode is arranged between the lower edge of the middle part of the second NBL+HVNW isolation layer and the outer edge of the upper part of the third NBL+HVNW isolation ring.
The invention has the following technical effects: the invention discloses a motor H-bridge driving circuit chip layout, aiming at the phenomenon that negative pressure at the Drain end of a Low-side of an H-bridge affects other devices most, the Low side is deliberately placed at the far end of a Die and is as far away from other circuit modules (a bias circuit, a control circuit and a protection circuit) as possible, so that the negative pressure effect can be weakened as much as possible. For multi-channel NBL+HVNW isolation, the isolation ring can play a role in isolating negative pressure, for example, the first channel NBL+HVNW isolation ring is connected with a fixed strong source grounding end GND, so that the negative pressure can be isolated, the power consumption can be reduced, the isolation layer is connected with the fixed strong source GND, and the impact of an output end OUT (through parasitic capacitance) of violent action on a P-type substrate PSUB can be shielded.
Drawings
Fig. 1 is a schematic diagram of a typical H-bridge driver-level chip circuit for motor-driven products. In fig. 1, the first PMOS transistor Mp1 and the second PMOS transistor Mp2 are High-side, and the first NMOS transistor Mn1 and the second NMOS transistor Mn2 are Low-side. When Mp1, mn2 are on or Mp2, mn1 are on, the motor is in operation. When Mp1, mp2, mn1, mn2 are all closed, the motor is in a sliding state. In fig. 1, when the motor is running, a load current Iload (i.e., an inductor current Iload) exists in the winding coil L (i.e., the inductor L).
Fig. 2 is a schematic diagram of a first parasitic NPN transistor Qn1 formed when the motor of fig. 1 is suddenly changed from running to coasting. Qn1 in fig. 2 uses a surrounding N-type device n+ as a collector, a P-type substrate terminal (i.e., PSUB terminal) as a base, and a drain of Low-side (e.g., mn 1) as an emitter. Since the inductor current Iload cannot be suddenly changed, iload needs to freewheel to the power supply voltage terminal VCC through the second body diode D2 of Mp2 (i.e. raise the potential VOUT2 of the second output node OUT2 to make VOUT2> vcc+vdiod), and at the same time, freewheel pulls the potential VOUT1 of the first output node OUT1 low to make VOUT1< GND-Vdiod. VOUT1 is negative, i.e., negative occurs at the drain of Mn 1.
Fig. 3 is a schematic diagram of a second parasitic PNP transistor Qp2 formed when the motor of fig. 1 is suddenly turned from running to coasting. Qp2 in fig. 3 has the drain of High side (e.g., mp 2) as the emitter, the power supply voltage terminal VCC as the base, and the P-type substrate terminal (i.e., PSUB terminal) as the collector.
Fig. 4 is a schematic diagram of a layout of a motor H-bridge driving circuit chip embodying the present invention.
Fig. 5 is a schematic diagram of the temperature sensing principle of the fourth temperature sensing PNP transistor Qp4 in fig. 4. In fig. 5, when Ib is a fixed current, the VBE voltage difference of the transistor varies almost linearly with temperature.
Fig. 6 is a schematic diagram of the temperature sensing principle of the third temperature sensing NPN triode Qn 3. In fig. 6, when Ib is a fixed current, the VBE voltage difference of the transistor varies almost linearly with temperature. When the temperature sensor is used for sensing temperature, the base electrode and the collector electrode of the NPN triode are connected together to form a Diod (diode) form.
The reference numerals are listed below: VCC-supply voltage or supply voltage terminal; GND-ground; OUT 1-a first output node; OUT 2-a second output node; l-motor winding coils or inductances; iload-load current or inductor current; MP 1-a first PMOS tube; MP 2-second PMOS tube; mn 1-a first NMOS tube; mn 2-a second NMOS tube; d1 to D4-first to fourth body diodes (parasitic diodes); qn 1-a first parasitic NPN transistor; n+ -surrounding N-type devices; a PSUB-P-type substrate; an OUT-output stage; qp 2-a second parasitic PNP transistor; qn 3-third temperature sensing NPN triode; vt-temperature-sensitive voltage; ib-temperature sensing triode current; qp 4-fourth temperature sensitive PNP transistor; die-chip; HVD-high voltage devices; LVD-low voltage devices; an A-first NBL+HVNW isolation ring (NBL refers to an N buried layer and HVNW refers to a high-voltage N well); b-a second NBL+HVNW isolation layer; c-third NBL+HVNW spacer; d-fourth nbl+hvnw isolation layer; e-high voltage device NBL+HVNW isolation ring; f-low voltage device NBL+HVNW isolation ring.
Detailed Description
The invention will be described with reference to the accompanying drawings (fig. 1-6).
Fig. 1 is a schematic diagram of a typical H-bridge driver-level chip circuit for motor-driven products. Fig. 2 is a schematic diagram of a first parasitic NPN transistor Qn1 formed when the motor of fig. 1 is suddenly changed from running to coasting. Fig. 3 is a schematic diagram of a second parasitic PNP transistor Qp2 formed when the motor of fig. 1 is suddenly turned from running to coasting. Fig. 4 is a schematic diagram of a layout of a motor H-bridge driving circuit chip embodying the present invention. Fig. 5 is a schematic diagram of the temperature sensing principle of the fourth temperature sensing PNP transistor Qp4 in fig. 4. Fig. 6 is a schematic diagram of the temperature sensing principle of the third temperature sensing NPN triode Qn 3. Referring to fig. 4, referring to other drawings simultaneously, a layout of a motor H-bridge driving circuit chip includes an H-bridge driving circuit high side region and an H-bridge driving circuit low side region, and other circuit module regions (lower part of the drawing in fig. 4), the H-bridge driving circuit low side region is located at a far end (upper part of the drawing in fig. 4) of the other circuit module regions, and the H-bridge driving circuit high side region is located at a near end (middle part of the drawing in fig. 4) of the other circuit module regions. The H-bridge driving circuit low side area comprises a left half first NMOS tube Mn1 and a right half second NMOS tube Mn2, and the first NMOS tube Mn1 and the second NMOS tube Mn2 are respectively surrounded by two first NBL+HVNW isolation rings A in a one-to-one mode. The first NBL+HVNW isolation ring A is connected with a fixed strong source grounding end GND. A second NBL+HVNW isolation layer B is arranged between the low side region of the H-bridge driving circuit and the high side region of the H-bridge driving circuit, and the second NBL+HVNW isolation layer B is connected with a fixed strong source grounding end GND. The high side region of the H-bridge driving circuit comprises a left half first PMOS tube Mp1 and a right half second PMOS tube Mp2, the first PMOS tube Mp1 and the second PMOS tube Mp2 are respectively surrounded by two third NBL+HVNW isolating rings C in a one-to-one mode, and the third NBL+HVNW isolating rings C are connected with a power supply voltage end VCC. A fourth NBL+HVNW isolation layer D is arranged between the high side region of the H-bridge driving circuit and the other circuit module regions, and the fourth NBL+HVNW isolation layer D is connected with a power supply voltage end VCC. The other circuit block region includes a left half high voltage device HVD surrounded by a high voltage device nbl+hvnw isolation ring E and a right half low voltage device LVD surrounded by a low voltage device nbl+hvnw isolation ring F, the high voltage device nbl+hvnw isolation ring E being connected to a relatively strong source to protect the branch current and the low voltage device nbl+hvnw isolation ring F being connected to a relatively strong source to protect the internal devices. The geometric center of the H-bridge driving circuit is provided with a fourth temperature-sensing PNP triode Qp4. And a fourth temperature-sensing PNP triode Qp4 is arranged between the lower edge of the middle part of the second NBL+HVNW isolation layer B and the outer edge of the upper part of the third NBL+HVNW isolation ring C.
From the analysis of fig. 1 in the background art, the negative pressure of the Drain end of the H bridge Low-side has the greatest influence on other devices. The Low side is placed at the most distal end of Die in fig. 4, as far as possible from other circuit blocks (bias circuit, control circuit, protection circuit), as much as possible to weaken the negative pressure effect.
As shown in fig. 4 a, the nbl+hvnw forms a "bathtub", and the Low side is isolated once, the nbl+hvnw forms an NPN with the Drain terminal of the Low side (as shown in fig. 2, the nbl+hvnw is a collector, the BULK terminal is a base, and the Drain terminal of the Low side is an emitter), so as to provide negative leakage current, and the higher the nbl+hvnw potential, the stronger the current providing capability, i.e. the stronger the shielding negative voltage capability, but the larger the power loss (p=v×i), and the easier the isolation layer is burned. Therefore, the NBL+HVNW is connected with the strong source GND in a compromise design, so that negative pressure can be isolated, and power consumption can be reduced. The isolation layer is connected with a fixed strong source GND, and can also shield impact influence of the strong action OUT (through parasitic capacitance) on PSUB.
As shown in fig. 4B, an nbl+hvnw is added under the Low side, and the voltage is connected to the GND potential of the source to provide a residual negative leakage current, so as to perform secondary isolation negative pressure, and the isolation principle is the same as above.
As is clear from the above analysis, during the freewheeling process, overvoltage is generated at the Drain terminal of the High side, and a PNP parasitic triode is formed with PSUB (as shown in fig. 3, the Drain terminal of the High side is an emitter, the BULK terminal is a base, and the PSUB is a collector), so that electric leakage to the PSUB occurs, so that the PSUB which is negatively pulled by the negative pressure of the Low side can be exactly counteracted, and the isolation ring of the High side is NBL+HVNW connected with VCC (as shown in fig. 4C), so that the effect of isolating the negative pressure for three times can be achieved.
As shown in fig. 4, the fourth temperature-sensitive PNP transistor Qp4 is placed in the geometric center of the H-bridge, and the temperature in the geometric center is the average temperature because the H-bridge is normally operated to turn on the diagonally opposite switching transistors (Mp 1, mn2 or Mp2, mn1 are turned on).
As shown in fig. 5 and 6, which are schematic diagrams of the operation of the temperature sensing transistor, when the current Ib of the temperature sensing transistor is a fixed current, the VBE voltage difference of the transistor is almost linearly changed with temperature, and due to this characteristic, the transistor can be used for detecting the temperature. If the temperature is detected by an NPN transistor (e.g., the third temperature sensing NPN transistor Qn3 in fig. 6), when the negative voltage occurs in the H-bridge Low side, the N-type collector will leak, which interferes with the detected temperature (e.g., VBE in fig. 6 will be pulled Low), and malfunction occurs. The invention adopts PNP triode (such as the fourth temperature-sensing PNP triode Qp4 in figure 5) to detect temperature, the end B of the N type is at the outermost layer and is connected with the strong source GND to provide negative voltage leakage current, so that the negative voltage can not influence the temperature detection of the temperature-sensing section of the emitter E and the base B.
As shown in fig. 4D, finally, an nbl+hvnw isolation layer is added under the H-bridge driving stages Low side and High side with intense motion to perform four times of isolation, and the VCC is connected to High potential.
As shown in E of fig. 4, the isolation ring potential of all high voltage devices HVD in other circuit modules needs to be connected with a relatively strong source to protect the branch current, and the isolation principle is the same as that described above. As shown in F in fig. 4, all low-voltage devices LVD in other circuit blocks need to be protected by the nbl+hvnw isolation ring, and are connected to a relatively strong source to protect the internal devices, the isolation principle is the same as above.
It is noted that the above description is helpful for a person skilled in the art to understand the present invention, but does not limit the scope of the present invention. Any and all such equivalent substitutions, modifications and/or deletions as may be made without departing from the spirit and scope of the invention.
Claims (5)
1. The motor H-bridge driving circuit chip layout is characterized by comprising an H-bridge driving circuit high side area, an H-bridge driving circuit low side area and other circuit module areas, wherein the H-bridge driving circuit low side area is positioned at the far ends of the other circuit module areas, and the H-bridge driving circuit high side area is positioned at the near ends of the other circuit module areas;
the H bridge driving circuit low side region comprises a left half part first NMOS tube and a right half part second NMOS tube, the first NMOS tube and the second NMOS tube are respectively surrounded by two first NBL+HVNW isolating rings in a one-to-one mode, and the first NBL+HVNW isolating rings are connected with a fixed strong source grounding end;
a second NBL+HVNW isolation layer is arranged between the low side region of the H-bridge driving circuit and the high side region of the H-bridge driving circuit, and the second NBL+HVNW isolation layer is connected with a fixed strong source grounding end;
the H bridge driving circuit high side region comprises a left half first PMOS tube and a right half second PMOS tube, the first PMOS tube and the second PMOS tube are respectively surrounded by two third NBL+HVNW isolating rings in a one-to-one mode, and the third NBL+HVNW isolating rings are connected with a power supply voltage end.
2. The motor H-bridge driving circuit chip layout according to claim 1, wherein a fourth nbl+hvnw isolation layer is disposed between the H-bridge driving circuit high side region and the other circuit module region, and the fourth nbl+hvnw isolation layer is connected to a power supply voltage terminal.
3. The motor H-bridge driver circuit chip layout of claim 1, wherein the other circuit block areas comprise a left half high voltage device surrounded by a high voltage device nbl+hvnw isolation ring and a right half low voltage device surrounded by a low voltage device nbl+hvnw isolation ring, the high voltage device nbl+hvnw isolation ring being connected to a relatively strong source to protect the branch current, the low voltage device nbl+hvnw isolation ring being connected to a relatively strong source to protect the internal devices.
4. The motor H-bridge driver circuit chip layout of claim 1, wherein a fourth temperature sensitive PNP transistor is disposed in a geometric center of the H-bridge driver circuit.
5. The motor H-bridge driving circuit chip layout according to claim 1, wherein a fourth temperature-sensing PNP transistor is disposed between the lower edge of the middle portion of the second nbl+hvnw isolation layer and the upper edge of the third nbl+hvnw isolation ring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010120611.5A CN113314518B (en) | 2020-02-26 | 2020-02-26 | Motor H bridge driving circuit chip layout |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010120611.5A CN113314518B (en) | 2020-02-26 | 2020-02-26 | Motor H bridge driving circuit chip layout |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113314518A CN113314518A (en) | 2021-08-27 |
| CN113314518B true CN113314518B (en) | 2023-10-13 |
Family
ID=77369877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010120611.5A Active CN113314518B (en) | 2020-02-26 | 2020-02-26 | Motor H bridge driving circuit chip layout |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113314518B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1681194A (en) * | 2004-04-09 | 2005-10-12 | 圆创科技股份有限公司 | Motor controlling circuit with controllable driven voltage supply |
| JP2010007317A (en) * | 2008-06-25 | 2010-01-14 | Panasonic Electric Works Co Ltd | Toilet bowl system |
| CN202586764U (en) * | 2012-03-05 | 2012-12-05 | 绍兴光大芯业微电子有限公司 | H bridge output circuit driven by motor |
| CN202633322U (en) * | 2012-06-15 | 2012-12-26 | 江苏派特科技发展有限公司 | Negative pressure energy storage follow current module |
| WO2016002508A1 (en) * | 2014-07-02 | 2016-01-07 | 富士電機株式会社 | Semiconductor integrated-circuit device |
| WO2016080950A1 (en) * | 2014-11-17 | 2016-05-26 | Cummins Inc. | Mode 7 push-pull structure with external pwm |
| CN106782405A (en) * | 2017-02-07 | 2017-05-31 | 武汉华星光电技术有限公司 | Display driver circuit and liquid crystal display panel |
| JP2017112294A (en) * | 2015-12-18 | 2017-06-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device and motor driver |
| CN107769629A (en) * | 2017-12-07 | 2018-03-06 | 绍兴光大芯业微电子有限公司 | The current stabilization drive system and its method of unicoil fan motor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4975898B2 (en) * | 2000-08-24 | 2012-07-11 | 富士通株式会社 | Trading system |
| JP4438608B2 (en) * | 2004-02-16 | 2010-03-24 | 株式会社デンソー | H-bridge circuit drive device and H-bridge circuit protection method |
| US10396167B2 (en) * | 2015-12-15 | 2019-08-27 | Fuji Electric Co., Ltd. | Semiconductor device |
-
2020
- 2020-02-26 CN CN202010120611.5A patent/CN113314518B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1681194A (en) * | 2004-04-09 | 2005-10-12 | 圆创科技股份有限公司 | Motor controlling circuit with controllable driven voltage supply |
| JP2010007317A (en) * | 2008-06-25 | 2010-01-14 | Panasonic Electric Works Co Ltd | Toilet bowl system |
| CN202586764U (en) * | 2012-03-05 | 2012-12-05 | 绍兴光大芯业微电子有限公司 | H bridge output circuit driven by motor |
| CN202633322U (en) * | 2012-06-15 | 2012-12-26 | 江苏派特科技发展有限公司 | Negative pressure energy storage follow current module |
| WO2016002508A1 (en) * | 2014-07-02 | 2016-01-07 | 富士電機株式会社 | Semiconductor integrated-circuit device |
| WO2016080950A1 (en) * | 2014-11-17 | 2016-05-26 | Cummins Inc. | Mode 7 push-pull structure with external pwm |
| JP2017112294A (en) * | 2015-12-18 | 2017-06-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device and motor driver |
| CN106782405A (en) * | 2017-02-07 | 2017-05-31 | 武汉华星光电技术有限公司 | Display driver circuit and liquid crystal display panel |
| CN107769629A (en) * | 2017-12-07 | 2018-03-06 | 绍兴光大芯业微电子有限公司 | The current stabilization drive system and its method of unicoil fan motor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113314518A (en) | 2021-08-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7106568B2 (en) | Substrate-triggered ESD circuit by using triple-well | |
| CN105789201B (en) | Low drain Two direction clamp and the method for forming it | |
| US8633563B2 (en) | High-voltage integrated circuit device | |
| US7916439B2 (en) | Semiconductor switch arrangement and an electronic device | |
| EP0505191B1 (en) | Semiconductor device with low concentration n region to improve dV/dt capability | |
| CN100444378C (en) | Electrostatic protection circuit | |
| US20130032882A1 (en) | Bi-directional blocking voltage protection devices and methods of forming the same | |
| Liang et al. | Design of a gate diode triggered SCR for dual-direction high-voltage ESD protection | |
| JP5015509B2 (en) | Electrostatic protection circuit and semiconductor device | |
| KR20050107753A (en) | Low voltage nmos-based electrostatic discharge clamp | |
| US10573638B2 (en) | ESD protection circuit assembly for CMOS manufacturing process | |
| US5821797A (en) | Protection circuit for semiconductor devices | |
| US7838941B2 (en) | Electrostatic discharge protection device having a dual triggered transistor | |
| US9236733B2 (en) | Electrostatic discharge protection | |
| US20130161750A1 (en) | N-Channel Laterally Diffused Metal-Oxide-Semiconductor Device | |
| KR20020079565A (en) | Overvoltage protection circuit | |
| EP2515334B1 (en) | ESD protection circuit | |
| CN113314518B (en) | Motor H bridge driving circuit chip layout | |
| US7068482B2 (en) | BiCMOS electrostatic discharge power clamp | |
| US6624479B2 (en) | Semiconductor device having a protective circuit | |
| US20120069479A1 (en) | Power transistor device with electrostatic discharge protection and low dropout regulator using same | |
| JP2009021622A (en) | Semiconductor device | |
| US6707653B2 (en) | Semiconductor controlled rectifier for use in electrostatic discharge protection circuit | |
| CN109979929B (en) | High-voltage electrostatic discharge clamping protection element and integrated circuit chip | |
| JP2006245405A (en) | Semiconductor device and motor driving device using same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |