CN113312001A

CN113312001A - Chip data copying device and method

Info

Publication number: CN113312001A
Application number: CN202110628208.8A
Authority: CN
Inventors: 林示麟
Original assignee: Shenzhen Angke Technology Co ltd
Current assignee: Shenzhen Angke Technology Co ltd
Priority date: 2021-06-06
Filing date: 2021-06-06
Publication date: 2021-08-27
Anticipated expiration: 2041-06-06
Also published as: CN113312001B

Abstract

The invention relates to a chip data copying device and a method, wherein a logic control unit is adopted to analyze each subarea of a master to obtain a master analysis result file, the participation of a processor is reduced, the data processing speed can be improved, the logic control unit is also used for executing copying, the data caching space of the processor is not needed, the hardware cost is saved, the data processing speed is further accelerated, the processor can be matched with the master analysis result file for copying, the copying data quantity is effectively reduced, the copying time is reduced, the logic control unit can realize different chip communication protocols, and therefore, the data copying among chips with various protocols is supported, a corresponding chip data copying device can maximally use the bandwidth of a chip hardware bus, and the purpose of improving the data copying speed of a large-capacity chip is achieved.

Description

Chip data copying device and method

Technical Field

The present disclosure relates to the field of semiconductor memory chip technology, and in particular, to a chip data copying apparatus and method.

Background

At present, for large-capacity chip data writing (for example, the capacity of chip storage data is greater than 4GBytes), most of the data writing operations are performed by directly writing data from a computer into a chip, the data writing operations are performed under the participation of software, the bandwidth of a hardware bus cannot be well utilized, and when a plurality of chips are operated at the same time, the data copying speed is often slow; some devices adopt hardware for data writing, but the completion time is too long due to large data volume; therefore, when a plurality of chips need to write copy data, the traditional chip data copying scheme has the problem of low speed.

Disclosure of Invention

In view of the above, it is desirable to provide a chip data copying apparatus with a high copying speed.

One aspect of the present application provides a chip data copying apparatus, including a processor and a logic control unit; the logic control unit is respectively connected with the master slice and each chip to be written;

the logic control unit analyzes each subarea of the master to obtain a master analysis result file, sends the master analysis result file to the processor, receives each execution address setting command returned by the processor, starts a data reading and data writing command, and respectively reads back effective data of each subarea from the master and writes the effective data into each chip to be written by taking the minimum read data volume as a unit; the master analysis result file records an effective data storage table of each partition; the effective data storage table records the length of effective data in a corresponding partition, a check value and the initial position of the minimum read data volume;

the processor obtains each effective data storage table of the master analysis result file, obtains the length, the check value and the initial position of the minimum read data amount of the effective data in each partition of the master, generates an execution address setting command of each partition, and sends each execution address setting command to the logic control unit.

In one embodiment, the processor analyzes each valid data storage table of the master analysis result file one by one to obtain the length of valid data, a check value and a starting position of a minimum read data amount in each partition of the master, generates an ith execution address setting command of an ith partition, and sends the ith execution address setting command to the logic control unit; wherein i is a partition serial number, and the initial value of i is 1;

the logic control unit receives an ith execution address setting command, starts a data reading and data writing command, reads the effective data of an ith partition from the master slice by taking the minimum read data volume as a unit, writes the effective data of the ith partition into each chip to be written, and feeds back writing completion information to the processor;

and the processor receives the write-in completion information, updates i to i +1, and returns to execute the process of generating the ith execution address setting command of the ith partition until the execution address setting commands of all the partitions in the master slice are issued to the logic control unit.

In one embodiment, the acquiring process of the master analysis result file includes:

s11, identifying each subarea of the master slice and the subarea capacity of each subarea;

s12, analyzing the ith partition by taking the minimum read data volume as a unit, marking the Sector position as a first identifier if the minimum read data volume is all blank data, marking the corresponding Sector position as a second identifier if the minimum read data volume has effective data, generating Bit tables corresponding to the Sector positions marked as the second identifiers, and calculating check values corresponding to the Bit tables; wherein the Sector position is a storage position for recording a corresponding minimum read data volume; i is a partition serial number, and the initial value of i is 1;

s13, generating an effective data storage table of the ith partition according to each Bit table and each check value of the ith partition, and enabling the effective data storage table to record the length of effective data in the corresponding partition, the check value and the initial position of the minimum read data volume;

and S14, updating i to i +1, returning to execute the step S12 until the valid data storage tables of all the partitions are obtained, and generating a master analysis result file according to each valid data storage table.

Specifically, the calculation process of the check value includes:

wherein Bits represents a check value, AreaSize represents a partition capacity of a corresponding partition, and Sector represents a minimum read data amount.

In one embodiment, after writing the valid data of each partition into each chip to be written, the logic control unit reads each group of chip data from each chip to be written, respectively calculates the check value of each valid data in each group of chip data, obtains each group of test check values, obtains a group of check values of the master, obtains a reference check value, and determines that the data of each chip to be written is copied successfully if each group of test check values is consistent with the reference check value.

Specifically, the logic control unit sends check value acquisition information to the processor;

and the processor receives the check value acquisition information, reads each check value of each partition from each effective data storage table of the master analysis result file to obtain the reference check value, and returns the reference check value to the logic control unit.

Specifically, the chip data copying device further comprises a display module; and the logic control unit controls the display module to display information representing successful data copying after judging that the data copying of each chip to be written is successful.

Specifically, the display module comprises a first indicator light, a second indicator light and a third indicator light; the colors of the first indicator light, the second indicator light and the third indicator light are different from each other;

the logic control unit controls the first indicator light to be turned on after judging that the data copying of each chip to be written succeeds, controls the second indicator light to be turned on after judging that the data copying of each chip to be written fails, and controls the third indicator light to be turned on when the data is written into each chip to be written.

In one embodiment, the logic control unit is an FPGA.

One aspect of the present application provides a method for copying chip data, including:

the logic control unit analyzes each subarea of the master to obtain a master analysis result file, and sends the master analysis result file to the processor; the master analysis result file records an effective data storage table of each partition; the effective data storage table records the length of effective data in a corresponding partition, a check value and the initial position of the minimum read data volume; the logic control unit is respectively connected with the master slice and each chip to be written; the protocol types of the chips to be written and the master slice are consistent;

the processor obtains each effective data storage table of the master analysis result file, obtains the length, the check value and the initial position of the minimum read data amount of the effective data in each partition of the master, generates an execution address setting command of each partition, and issues each execution address setting command to the logic control unit;

and the logic control unit receives each execution address setting command, starts a data reading command and a data writing command, and respectively reads the effective data of each partition from the master slice and writes the effective data into each chip to be written by taking the minimum read data amount as a unit.

The chip data copying device and the method thereof adopt the logic control unit to analyze each subarea of the master slice to obtain a master slice analysis result file, reduce the participation of a processor, can improve the data processing speed, also use the logic control unit to execute the copying, do not need the data cache space of the processor, save the hardware cost, further accelerate the data processing speed, the processor can be matched with the master slice analysis result file to copy, effectively reduce the copy data volume, reduce the copying time, the logic control unit can realize different chip communication protocols, thereby supporting the data copying among chips with various protocols, and the corresponding chip data copying device can maximally use the chip hardware bus bandwidth, thereby achieving the purpose of improving the data copying speed of large-capacity chips.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:

FIG. 1 is a block diagram of a chip data copying apparatus according to an embodiment;

FIG. 2 is a schematic diagram of an embodiment of a chip data copying apparatus;

FIG. 3 is a flowchart of the operation of the chip data copying apparatus according to one embodiment.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

Specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

As shown in fig. 1, a first aspect of the present application provides a chip data copying apparatus, which includes a processor 105 and a logic control unit 104; the logic control unit 104 is respectively connected with the master 101 and each chip to be written 102;

the logic control unit 104 analyzes each partition of the master 101 to obtain a master analysis result file, and sends the master analysis result file to the processor 105;

the processor 105 obtains each effective data storage table of the master analysis result file, obtains the length of effective data, the check value and the initial position of the minimum read data amount in each partition of the master 101, generates an execution address setting command of each partition, and issues each execution address setting command to the logic control unit 104; the master analysis result file records an effective data storage table of each partition; the effective data storage table records the length of effective data in a corresponding partition, a check value and the initial position of the minimum read data volume;

the logic control unit 104 receives each execution address setting command returned by the processor 105, starts a data reading and data writing command, and reads back the valid data of each partition from the master 101 and writes the valid data into each chip to be written 102 by taking the minimum read data amount as a unit.

The logic control unit 104 may be an FPGA, and the processor 105 may be an MCU main control chip and is mainly responsible for running programs including an operating system, a burning application program, and a driver program. The logic control unit 104 is mainly responsible for reading and writing data of a large-capacity chip, and the processor 105 is connected with the logic control unit 104 by a high-speed bus.

In practical applications, the processor 105 and the logic control unit 104 may be disposed in a copy device, and the copy device is connected to the master 101 and each chip to be written 102 respectively. The master 101, i.e. where the chip raw data is present, is accessed by the logic control unit 104 by a read operation. The number of chips 102 to be written may be N; if the current device (logic control unit 104) is designed to allow a maximum of 8 chips to be connected at a time, the value of N is 1-8; in other application examples, the above operation method is not limited to 8 chips, and may be more. Corresponding data can be written from the logic control unit 104 to the chip to be written by a write operation, and data of the chip to be written can be read to the logic control unit 104 by a read operation. Optionally, each chip to be written 102 and the master 101 are powered by a copying device. Specifically, the protocol types of the chip to be written 102 and the master 101 may be the same; or else, if the two protocol types are not consistent, the data copy between different protocol chips can be realized by loading different FPGA programs.

The chip data copying device adopts the logic control unit 104 to analyze each subarea of the master, a master analysis result file is obtained, the participation of a processor is reduced, the data processing speed can be improved, the logic control unit is also used for executing copying, the data caching space of the processor is not needed, the hardware cost is saved, the data processing speed is further accelerated, the processor 105 can be matched with the master analysis result file for copying, the effective copy data amount is reduced, the copying time is shortened, the logic control unit 104 can realize different chip communication protocols, thereby supporting the data copying among chips with various protocols, the corresponding chip data copying device can use the bandwidth of a chip hardware bus to the maximum, and the purpose of improving the data copying speed of a large-capacity chip is achieved.

Specifically, if the logic control unit is an FPGA, the processor is an MCU, and the working schematic diagram of the chip data copying apparatus can also refer to fig. 2, the MCU 105 is responsible for running programs including an operating system, a burning application program and a driver, the FPGA 104 is responsible for reading and writing large-capacity chip data, and calculating a data check value (such as CRC16), and the MCU and the FPGA are connected by a high-speed bus (106). The master 101 is where the original data of the chip exists, and can be accessed by the FPGA through the read operation 107, the chip N shown in fig. 2 represents each chip to be written, if the current device is designed to allow connection of 8 chips at most once, the value of N is 1-8; the protocol type of the chip is consistent with the protocol type of the master, but data copying between different protocol chips can be realized by loading different FPGA programs. In other examples, the number of chips to be written is not limited to 8 chips, and may be more. Data may be written from the FPGA to the chip by a write operation 108 and read into the FPGA by a read operation 109. The master 101 and the chip 102 are powered by the copying device (110 shown in fig. 2). The master analysis result file may be an MIF file, the suffix name of the master analysis result file is MIF, and the valid data writing process shown in fig. 2 may refer to fig. 3, where the master analysis only needs to be performed once, and then the master copy stage is performed, and the FPGA is connected to the empty chip during the copy process, and the valid data writing process is generally achieved by placing the chip in a corresponding chip holder. The driver running in the MCU 105 calls the MIF file and then copies it as follows:

1. the MCU 105 parses the valid data table stored in the MIF file one by one, and obtains StartSector (start position of Sector of valid data), Length (Length of valid data) and CRC16 information (check value of valid data) of the valid data.

2. By telling the FPGA 104 to execute the address setting command through 108, the FPGA 104 sets the data reading address of the master 101 to StartSector, the FPGA 104 sets the data writing address of the chip 102 to StartSector, and then the FPGA 104 starts the data reading and data writing commands to read data from the master 101 and write the data to the FPGA 104 in units of sectors, in the 108 implementation process, 107 can also be implemented synchronously, because the writing speed of the chip is generally lower than the reading speed, except for the first reading, the later 107 implementation time can be ignored, and it seems that the data writing action is always performed. The number of times of write execution is Length/Sector, and then the write execution is automatically stopped. The FPGA 104 informs the MCU 105 that a record copy action has been performed through the flag bit. If there is a problem in the middle of the process, setting an error flag. MCU 105 can set multiple records to FPGA 104 at a time. The intermediate MCU no longer intervenes and can do other things.

3. After all records of one effective data table are completely copied, the step 1 is carried out to copy the effective data of other partition tables until the data of all the data tables are completely copied.

The effective data is non-blank data; the first flag may be 0, the second flag may be 1, and the first flag and the second flag may be set to other values according to requirements.

The calculation process of the check value comprises the following steps:

Bits＝AreaSize/(Sector×8)，

Specifically, the process of acquiring the master analysis result file in this embodiment may also refer to the working process shown in fig. 2, which specifically includes the following contents:

1. the FPGA 104 reads the master slice information through 107 and determines the master slice chip and the capacity of each partition;

2. the method comprises the steps of completely reading partition data, marking the partition data with a partition minimum read data volume (a Sector can be 512Bytes) as a unit, determining the partition minimum read volume generally according to a minimum write unit of a high-capacity chip as a set value, wherein the partition minimum read volume can be obtained from a chip manual, confirming whether effective data (non-blank data and common chip default blank data are 0) exist in the current Sector by an FPGA (field programmable gate array), marking the position of the Sector as 0 if the current Sector is completely blank data, and marking the position of the Sector as 1 if the non-blank data exist. Wherein the mark of each Sector accounts for 1 Bit, and a Bit table with the size of partition capacity (area size)/(Sector × 8) bits can be obtained finally. And simultaneously obtaining the check value of each Sector.

3. Combining the bits which are continuously 1 according to the Bit table information in the step 2, recording the starting Sector position and the continuous number of each 1, and obtaining the check value of the corresponding data. The software is used for arranging to obtain an effective data storage table, and each record of the table comprises the information of the starting position of the Sector of the effective data A (StartSector), the Length of the effective data B (Length), the check value of the effective data C (CRC16), and the number of 1 s after the continuous 1 s of the Bit table are combined, and the number of effective data records.

4. One partition obtains an effective data storage table, the step 2 is returned to, other data partitions are analyzed, effective data tables of other partitions are obtained, and finally the tables are stored in an MIF file; therefore, the MIF file can be generated by completing the analysis process.

In one embodiment, after writing the valid data of each partition into each chip to be written, the logic control unit reads each group of chip data from each chip to be written, respectively calculates a check value of each valid data in each group of chip data, obtains each group of test check values, obtains a group of check values of the master, obtains a reference check value, and determines that the data of each chip to be written is copied successfully if each group of test check values is consistent with the reference check value.

Specifically, if all the groups of test check values are consistent with the reference check value, the data copying success of all the chips to be written is indicated; if the test check values of each group are not completely consistent with the reference check values (such as the characteristics of the sizes or the sequences of some check values and the like), the data copying failure of each chip to be written is indicated.

In this embodiment, after the valid data is written into each chip to be written, the data needs to be read back from the chip to be written to determine whether the data copying of each chip to be written is successful, so as to perform a corresponding prompt and inform a user of a data copying result. The above process may also adopt the related operations shown in fig. 2, wherein the process 109 of reading and writing data in the chip to be written is similar to the process 107, except that 107 is for the master and 109 is for multiple empty chips; the specific operation method can be as follows: according to the partition valid data table in the MIF file (master analysis results file), the FPGA 104 reads the data back through 109 and performs CRC16 (test check value) calculation. If the CRC16 value matches the reference check value in the record, this indicates that the data is completely stored in the chip and matches the master. If the two are not consistent, the reading or writing process has at least one problem, and an error is reported directly. And displaying the related result through a result indicator so that a user can classify the burning chips according to the display result of the indicator.

The display module provided in this embodiment may be a result indicator 111 as shown in fig. 2, so as to accurately indicate each result determined by the logic control unit.

Further, the display module comprises a first indicator light, a second indicator light and a third indicator light; the colors of the first indicator light, the second indicator light and the third indicator light are different from each other;

In one example, the first indicator light may be set to a red light, the second indicator light may be set to a green light, and the third indicator light may be set to a yellow light, where the red light indicates success, the green light indicates failure, and the yellow light indicates that the operation is in progress. In other examples, the first indicator light, the second indicator light and the third indicator light can be set to other colors according to specific requirements.

Another aspect of the present application provides a method for burning a chip serial number, including:

The chip serial number burning method provided by the application has all the beneficial effects of each chip data copying device provided by the embodiment, and is not repeated here.

In the above description of the present specification, the terms "fixed," "mounted," "connected," or "connected," and the like, are to be construed broadly unless otherwise expressly specified or limited. For example, with the term "coupled", it can be fixedly coupled, detachably coupled, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship. Therefore, unless the specification explicitly defines otherwise, those skilled in the art can understand the specific meaning of the above terms in the present invention according to specific situations.

From the above description of the present specification, those skilled in the art will also understand the terms used below, terms indicating orientation or positional relationship such as "upper", "lower", "front", "rear", "left", "right", "length", "width", "thickness", "vertical", "horizontal", "top", "bottom", "inner", "outer", "axial", "radial", "circumferential", "central", "longitudinal", "transverse", "clockwise" or "counterclockwise" and the like are based on the orientation or positional relationship shown in the drawings of the present specification, it is for the purpose of facilitating the explanation of the invention and simplifying the description, and it is not intended to state or imply that the devices or elements involved must be in the particular orientation described, constructed and operated, therefore, the above terms of orientation or positional relationship should not be construed or interpreted as limiting the present invention.

In addition, the terms "first" or "second", etc. used in this specification are used to refer to numbers or ordinal terms for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In the description of the present specification, "a plurality" means at least two, for example, two, three or more, and the like, unless specifically defined otherwise.

While various embodiments of the present invention have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous modifications, changes, and substitutions will occur to those skilled in the art without departing from the spirit and scope of the present invention. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. It is intended that the following claims define the scope of the invention and that the module compositions, equivalents, or alternatives falling within the scope of these claims be covered thereby.

Claims

1. The chip data copying device is characterized by comprising a processor and a logic control unit; the logic control unit is respectively connected with the master slice and each chip to be written;

2. The chip data copying device according to claim 1, wherein the processor parses each valid data storage table of the master analysis result file one by one, obtains a length of valid data, a check value, and a start position of a minimum read data amount in each partition of the master, generates an ith execution address setting command of an ith partition, and issues the ith execution address setting command to the logic control unit; wherein i is a partition serial number, and the initial value of i is 1;

3. The chip data copying apparatus according to claim 1, wherein the acquiring of the master analysis result file includes:

4. The chip data copying apparatus according to claim 3, wherein the calculation of the check value includes:

5. The chip data copying device according to any one of claims 1 to 4, wherein the logic control unit reads each set of chip data from each chip to be written after writing the valid data of each partition into each chip to be written, calculates a check value of each valid data in each set of chip data, obtains each set of test check values, and the processor obtains a set of check values of the master to obtain a reference check value, and determines that the data copying of each chip to be written is successful if each set of test check values is consistent with the reference check value.

6. The chip data copying apparatus according to claim 5, wherein the logic control unit sends check value acquisition information to the processor;

7. The chip data copying apparatus according to claim 5, further comprising a display module; and the logic control unit controls the display module to display information representing successful data copying after judging that the data copying of each chip to be written is successful.

8. The chip data copying apparatus according to claim 7, wherein the display module includes a first indicator light, a second indicator light, and a third indicator light; the colors of the first indicator light, the second indicator light and the third indicator light are different from each other;

9. The chip data copying device according to any one of claims 1 to 4, wherein the logic control unit is an FPGA.

10. A method for copying chip data, comprising: