CN113299605A - Display panel and preparation method thereof - Google Patents
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- CN113299605A CN113299605A CN202110501650.4A CN202110501650A CN113299605A CN 113299605 A CN113299605 A CN 113299605A CN 202110501650 A CN202110501650 A CN 202110501650A CN 113299605 A CN113299605 A CN 113299605A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 131
- 239000000463 material Substances 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
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- 238000000576 coating method Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 238000009826 distribution Methods 0.000 abstract description 16
- 230000000694 effects Effects 0.000 abstract description 7
- 238000002161 passivation Methods 0.000 description 17
- 239000010408 film Substances 0.000 description 7
- 239000007772 electrode material Substances 0.000 description 6
- 230000035515 penetration Effects 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000011049 filling Methods 0.000 description 4
- 229910010272 inorganic material Inorganic materials 0.000 description 4
- 239000011147 inorganic material Substances 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
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- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Abstract
The application discloses a display panel and a preparation method thereof, wherein the preparation method of the display panel comprises the following steps: providing a substrate; preparing a substrate layer on the substrate; preparing a plurality of grooves on the substrate layer; and preparing electrode wires on the substrate layer and in the groove, wherein the electrode wires are embedded electrode wires. The technical effect of this application lies in, and embedded electrode is walked and is reduced the linewidth, increases the distribution density that the electrode was walked, increases sub-pixel's distribution density, improves display panel's aperture ratio.
Description
Technical Field
The application relates to the field of display, in particular to a display panel and a preparation method thereof.
Background
The TFT-LCD is popular with people because of its advantages of low price, light weight, convenient carrying, long service life, clear picture, high reliability, etc. TFT-LCD products are widely visible in our daily lives, ranging from commercial advertising to smart watches. Because of its high reliability, it is also used in military industry, such as space flight and aviation, etc. Although many advanced display modes such as OLED, QD, LED, Micro-LED, ink screen, etc. are emerging, they do not fully replace the position of TFT-LCD due to various reasons such as cost, lifetime, reliability, materials, technical barriers, etc. TFT-LCDs still occupy a large market share.
With the progress of social science and technology and the improvement of life quality of people, especially the expansion of application scenes, people put forward more and higher requirements on display screens. The display screen has the advantages of initial simple display to present readable and writable, interactive and high response speed, high color gamut, high contrast ratio and the like. These high requirements for display quality have led panel manufacturers to continue technological innovation and to seek new solutions to meet consumer needs. The OLED display technology not only can meet the requirements of high response speed, high color gamut, high contrast ratio, etc., but also can integrate many functions, such as TP, sensor, etc. Moreover, the OLED can be thinner and lighter, can realize flexible display, and the like. The disadvantage of OLEDs is the lifetime of the light emitting material, as well as the higher cost, which reduces the market competitiveness of OLEDs.
Although the advent of OLEDs segmented the TFT-LCD market, resulting in a reduction in TFT-LCD market share, the steps of TFT-LCD innovation never stopped. In recent years, the display quality of the TFT-LCD has been greatly improved to stabilize the market share. Such as dual cell technology, mini backlight technology, etc.
The common methods for improving the pixel aperture ratio at present include:
(1) the electrode routing is made thinner, but the resistance is increased, so that the delay phenomenon of the RC is more serious;
(2) replacing BM shading by shading with DBS technology;
(3) the size of the TFT is reduced by adopting a novel semiconductor material;
(4) transparent electrode wiring is adopted, but transparent electrode wiring materials are immature, and the like;
therefore, new methods are needed to further enhance the aperture ratio of the pixel.
Disclosure of Invention
An object of the present application is to provide a display panel and a manufacturing method thereof, which can solve the technical problem that the effect of improving the pixel aperture ratio of the existing display panel is not good.
The application provides a preparation method of a display panel, which comprises the following steps: providing a substrate; preparing a substrate layer on the substrate; preparing a plurality of grooves on the substrate layer; and preparing electrode wires on the substrate layer and in the groove, wherein the electrode wires are embedded electrode wires.
Further, in the step of preparing the plurality of grooves on the substrate layer, the substrate layer is sequentially subjected to exposure, development and curing treatment to form the grooves; the depth of the groove is 2-5 microns.
Further, in the step of preparing the electrode wire on the substrate layer and in the groove, a metal film is formed on the substrate layer and the whole surface in the groove; patterning the metal film by adopting exposure, development and etching modes to form an electrode wire; the electrode routing is filled into the groove and extends to the substrate layer.
Further, the thickness of the metal film is larger than the depth of the groove; the thickness of the metal film arranged on the substrate layer is 0.2-0.5 micrometer.
Further, the step of preparing the electrode trace on the substrate layer and in the groove comprises sequentially preparing a gate trace and a source-drain electrode trace.
Further, in the step of preparing the gate wire, a first substrate layer is prepared on the substrate; preparing a plurality of first grooves on the first substrate layer; and preparing the grid routing on the first substrate layer and in the first groove.
Further, the step of preparing the gate trace further includes: preparing a grid electrode insulating layer on the first substrate layer and the grid electrode routing; and depositing a layer of semiconductor material on the grid electrode insulating layer to form an active layer, wherein the active layer is arranged opposite to the grid electrode routing.
Further, in the step of preparing the source-drain electrode routing, a layer of transparent substrate material is coated on the active layer and the gate insulating layer to form a second substrate layer, and a second groove is formed on the second substrate layer; and forming the source and drain electrode routing in the second deposition layer and the second groove.
The present application also provides a display panel, including: a substrate; the substrate layer is arranged on the substrate; the substrate layer is provided with a plurality of grooves; and the electrode routing is filled in the groove and extends to the upper surface of the substrate layer, and the electrode routing is embedded electrode routing.
Further, the line width of the electrode routing line is a vertical line width, and the vertical line width is 2-5 micrometers.
The technical effect of this application lies in, and embedded grid is walked and/or is leaked the electrode and walk the line and become vertical line width with its most horizontal line width, reduces the electrode and walks the area occupied on the substrate layer, increases the distribution density that the electrode was walked further increases sub-pixel's distribution density, strengthens the aperture opening ratio of pixel, and then can improve display panel's contrast, penetration rate or transparency.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure;
FIG. 2 is a schematic representation after a groove preparation step provided in an embodiment of the present application;
FIG. 3 is a cross-sectional view of an embodiment of the present application after a step of preparing an electrode trace;
FIG. 4 is a top view of an electrode trace provided by an embodiment of the present application;
fig. 5 is a schematic cross-sectional view of a display panel provided in an embodiment of the present application;
fig. 6 is a top view of a display panel provided in an embodiment of the present application.
Description of reference numerals:
1. a substrate; 2. a first substrate layer; 3. routing a grid; 4. a gate insulating layer; 5. an active layer; 6. a second substrate layer; 7. routing the source and drain electrodes; 8. a passivation layer; 9. a sub-pixel;
21. a first groove;
31. a first gate trace; 32. a second gate trace;
61. a second groove; 62. a contact hole;
71. routing a first source drain electrode; 72. routing a second source drain electrode; 73. a third source drain electrode trace;
81. and a passivation layer through hole.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The embodiment of the application provides a display panel and a preparation method thereof. The following are detailed below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
The application provides a preparation method of a display panel, which comprises the following steps: providing a substrate; preparing a substrate layer on the substrate; preparing a plurality of grooves on the substrate layer; and preparing electrode wiring on the substrate layer and in the groove.
As shown in fig. 1, the preparation method of the display panel provided in this embodiment includes the above preparation steps, where the electrode traces include a gate trace and a source-drain electrode trace, and both the preparation steps of the gate trace and/or the source-drain electrode trace may adopt the above methods, in this embodiment, taking the above preparation methods for both the two electrode traces as an example, this embodiment specifically includes steps S1 to S8.
S1 provides a substrate 1, wherein the substrate 1 is a hard substrate, generally a glass substrate, and plays a role of supporting the thin film.
S2 a first substrate layer 2 is prepared on the substrate 1 and a number of first grooves 21 (see fig. 2) are prepared on the substrate layer 2. Specifically, whole one deck transparent substrate material of coating forms on base plate 1 the substrate layer 2 adopts modes such as exposure, development, solidification processing in proper order form a plurality of first recesses 21 on the first substrate layer 2, first recess 21 can be for running through the through-hole structure of first substrate layer 2, also can be for not running through the groove structure of first substrate layer 2, the degree of depth of first recess 21 is 2 ~ 5 microns, first recess 21 is rectangular shape recess, first recess 21 is used for filling electrode material.
S3, preparing electrode traces on the first substrate layer 2 and in the first groove 21, where the electrode traces are gate traces 3, and the gate traces 3 are embedded electrode traces. Specifically, a metal film is formed on the upper surface of the first substrate layer 2 and the entire surface inside the first groove 21, and is patterned by sequentially performing exposure, development and etching to form the gate trace 3 (see fig. 3 and 4), the gate trace 3 is filled in the first groove 21 and extends to the upper surface of the first substrate layer 2, in this embodiment, the gate trace arranged in the first groove 21 is defined as a first gate trace 31, the gate trace arranged on the upper surface of the first substrate layer 2 is defined as a second gate trace 32, and the first gate trace 31 and the second gate trace 32 are arranged perpendicular to each other in a top view (see fig. 4).
At this time, since the first groove 21 is a strip-shaped groove and has a deeper depth, the volume of the first groove 21 is larger, that is, the proportion of the first gate trace 31 disposed in the first groove 21 is larger, therefore, the second gate trace 32 occupies a smaller proportion, the thickness of the second gate trace 32 is 0.2 to 0.5 μm, and the area of the orthographic projection of the second gate trace 32 on the first substrate layer 2 is also in the micron order, namely, the line width of the gate trace 3 prepared in this embodiment is changed from the original horizontal line width to the vertical line width, on the premise of providing the same amount of gate materials, due to the existence of the first gate wire 31, the thickness and the surface area of the second gate wire 32 are greatly reduced, the horizontal line width of the gate wire 3 is reduced to less than 2 microns, which is equivalent to greatly reducing the line width of the gate wire 3 and enhancing the distribution density of the gate wire 3.
S4 is to prepare a gate insulating layer 4 on the first substrate layer 2 and the gate trace 3, specifically, deposit a layer of inorganic insulating material on the first substrate layer 2 and the gate trace 3, where the inorganic insulating material may include one or more mixed materials such as silicon oxide, silicon nitride, and silicon oxynitride, to form the gate insulating layer 4, and the gate insulating layer 4 has a good insulating effect, so as to prevent a short circuit problem between the gate trace 3 and the source/drain electrode trace 7.
S5 is to form an active layer 5 on the gate insulating layer 4, specifically, deposit a layer of semiconductor material on the upper surface of the gate insulating layer 4, in this embodiment, the semiconductor material includes amorphous silicon (a-Si) to form the active layer 5, and the active layer 5 is disposed opposite to the gate trace 3.
S6 preparing a second substrate layer 6 on the upper surfaces of the active layer 5 and the gate insulating layer 4, and forming a plurality of second grooves 61 on the second substrate layer 6. Specifically, a layer of transparent substrate material is deposited on the upper surfaces of the active layer 5 and the gate insulating layer 4 to form a second substrate layer 6, and the second substrate layer 6 is made of the same or different material as the first substrate layer 2, and plays a role of a substrate and a support.
Adopt modes such as exposure, development, solidification processing in proper order form a plurality of second recesses 61 on the second substrate layer 6, second recess 61 can be for running through the through-hole structure of second substrate layer 6 also can be for not running through the groove structure of second substrate layer 6, the degree of depth of second recess 61 is 2 ~ 5 microns, second recess 61 is rectangular shape recess, second recess 61 is used for filling electrode material.
When the second groove 61 is prepared, a contact hole 62 can be prepared, the contact hole 62 is arranged opposite to the active layer 5, part of the active layer 5 is exposed, and the contact hole 62 is used as a connecting channel between the source/drain electrode wiring 7 and the active layer 5. After the contact hole 62 is formed, a conductor processing may be performed, and after a portion of the active layer 5 exposed in the contact hole 62 is made into a conductor, the active layer 5 may be electrically connected to the source/drain electrode trace 7, and a portion of the active layer 5 not exposed still maintains semiconductor characteristics and serves as a channel region.
S7, preparing electrode traces on the second substrate layer 6, in the second groove 61 and in the contact hole 62, where the electrode traces are the source/drain electrode traces 7, and the source/drain electrode traces 7 are embedded electrode traces. Specifically, a metal film is formed on the upper surface of the second substrate layer 6, the second groove 61 and the contact hole 62 on the whole surface, the metal film is subjected to patterning treatment in the modes of exposure, development and etching in sequence to form the source/drain electrode wire 7, and the source/drain electrode wire 7 is filled into the second groove 61 and the contact hole 62 and extends to the upper surface of the second substrate layer 6. In this embodiment, the source-drain electrode trace disposed in the second groove 61 is defined as a first source-drain electrode trace 71, the source-drain electrode trace disposed on the upper surface of the second substrate layer 6 is defined as a second source-drain electrode trace 72, the source-drain electrode trace disposed in the contact hole 62 is defined as a third source-drain electrode trace 73, from a top view, the first source-drain electrode trace 71 and the second source-drain electrode trace 72 are perpendicular to each other (see fig. 6), and the third source-drain electrode 73 serves as an electrical connection channel between the source-drain electrode trace 7 and the active layer 5.
At this time, in a similar manner, since the second groove 61 is a long-strip-shaped groove and has a deeper depth, the volume of the second groove 61 is larger, that is, the proportion occupied by the first source/drain electrode trace 71 disposed in the second groove 61 is larger, the proportion occupied by the second source/drain electrode trace 72 is smaller, the thickness of the second source/drain electrode trace 72 is 0.2 to 0.5 micrometers, and the area of the orthographic projection of the second source/drain electrode trace on the second substrate layer 6 is also micrometer-sized, that is, the line width of the source/drain electrode trace 7 prepared in this embodiment is changed from the original horizontal line width to a vertical line width, on the premise of providing an equal amount of source/drain electrode material, due to the existence of the first source/drain electrode 71, the thickness and the surface area of the second source/drain electrode 72 are greatly reduced, and the horizontal line width of the source/drain electrode trace 7 is reduced to less than 2 micrometers, the line width of the source drain electrode wire 7 is greatly reduced, and the distribution density of the source drain electrode wire 7 is enhanced.
S8 prepares a passivation layer 8 and a sub-pixel 9 on the source/drain electrode trace 7 (see fig. 5 and 6), and specifically, deposits a layer of inorganic material on the upper surface of the source/drain electrode trace 7, where the inorganic material is an insulating material, to form the passivation layer 8. A hole is formed in the passivation layer 8 to form a passivation layer through hole 81 (see fig. 6), and the passivation layer through hole 81 facilitates connection between the electrode of the sub-pixel 9 and the source/drain electrode trace 7.
Because one sub-pixel 9 corresponds to one source drain electrode wire 7 and one gate wire 3, when the line widths of the gate wire 3 and the source drain electrode wire 7 are reduced, the distribution density of the gate wire 3 and the source drain electrode wire 7 is increased, the distribution density of the sub-pixel 9 is further increased, the aperture opening ratio of the pixel is greatly improved under the condition that the resistance is not additionally increased, and the contrast ratio, the penetration rate or the transparency of the prepared display panel can be improved.
The manufacturing method of the display panel has the technical effects that most of horizontal line width of the embedded grid wire and/or source drain electrode wire is changed into vertical line width, the occupied area of the electrode wire on the substrate layer is reduced, the distribution density of the electrode wire is increased, the distribution density of sub-pixels is further increased, the aperture opening ratio of pixels is enhanced, and the contrast ratio, the penetration rate or the transparency of the manufactured display panel can be further improved.
The present embodiment also provides a display panel, including: the electrode wiring structure comprises a substrate, a substrate layer and electrode wiring, wherein the substrate layer is provided with a plurality of grooves, the electrode wiring is partially arranged in the grooves and extends to the upper surface of the substrate layer, the electrode wiring is embedded electrode wiring, the electrode wiring comprises a grid wiring and source and drain electrode wiring, and the grid wiring and/or the source and drain electrode wiring is embedded electrode wiring.
As shown in fig. 2 to 6, in this embodiment, taking the example that the gate trace and the source-drain electrode trace both adopt embedded electrode traces, the display panel includes a substrate 1, a first substrate layer 2, a gate trace 3, a gate insulating layer 4, an active layer 5, a second substrate layer 6, a source-drain electrode trace 7, a passivation layer 8, and a sub-pixel 9.
The substrate 1 is a hard substrate, generally a glass substrate, and plays a role in supporting a thin film.
As shown in fig. 2, the first substrate layer 2 is disposed on the upper surface of the substrate 1, and the substrate layer 2 has a plurality of first grooves 21. First recess 21 can be for running through the through-hole structure of first substrate layer 2 also can be for not running through the groove structure of first substrate layer 2, the degree of depth of first recess 21 is 2 ~ 5 microns, first recess 21 is rectangular shape recess, first recess 21 is used for filling electrode material.
As shown in fig. 3 and 4, the gate trace 3 is disposed on the first substrate layer 2 and in the first groove 21, the gate trace 3 is an embedded electrode trace, and the gate trace 3 is made of a metal material. The gate trace 3 is filled in the first groove 21 and extends to the upper surface of the first substrate layer 2, in this embodiment, the gate trace arranged in the first groove 21 is defined as a first gate trace 31, the gate trace arranged on the upper surface of the first substrate layer 2 is defined as a second gate trace 32, and the first gate trace 31 and the second gate trace 32 are perpendicular to each other in a top view.
At this time, since the first groove 21 is a strip-shaped groove and has a deeper depth, the volume of the first groove 21 is larger, that is, the proportion of the first gate trace 31 disposed in the first groove 21 is larger, therefore, the second gate trace 32 occupies a smaller proportion, the thickness of the second gate trace 32 is 0.2 to 0.5 μm, and the area of the orthographic projection of the second gate trace 32 on the first substrate layer 2 is also in the micron order, namely, the line width of the gate trace 3 prepared in this embodiment is changed from the original horizontal line width to the vertical line width, on the premise of providing the same amount of gate materials, due to the existence of the first gate wire 31, the thickness and the surface area of the second gate wire 32 are greatly reduced, the horizontal line width of the gate wire 3 is reduced to less than 2 microns, which is equivalent to greatly reducing the line width of the gate wire 3 and enhancing the distribution density of the gate wire 3.
The grid insulation layer 4 is arranged on the first substrate layer 2 and the grid wiring 3, the grid insulation layer 4 is made of inorganic insulation materials, the inorganic insulation materials can comprise one or more mixed materials such as silicon oxide, silicon nitride and silicon oxynitride, the grid insulation layer 4 has a good insulation effect, and the grid wiring 3 and the source drain electrode wiring 7 are prevented from being short-circuited.
The active layer 5 is disposed on the gate insulating layer 4, the active layer 5 is disposed opposite to the gate trace 3, and the active layer 5 is made of a semiconductor material, in this embodiment, the semiconductor material includes an amorphous silicon material (a-Si).
The second substrate layer 6 is disposed on the active layer 5 and the upper surface of the gate insulating layer 4, and the second substrate layer 6 has a plurality of second grooves 61 and contact holes 62. The second substrate layer 6 is made of the same or different material as the first substrate layer 2, and serves as a substrate and a support.
The second groove 61 can be a through hole structure penetrating through the second substrate layer 6, and can also be a groove structure not penetrating through the second substrate layer 6, the depth of the second groove 61 is 2-5 microns, the second groove 61 is a long-strip-shaped groove, and the second groove 61 is used for filling electrode materials.
The contact hole 62 is arranged opposite to the active layer 5, a part of the active layer 5 is exposed, and the contact hole 62 is used as a connecting channel between the source/drain electrode trace 7 and the active layer 5. After the part of the active layer 5 exposed in the contact hole 62 is made into a conductor, the electrical connection between the active layer 5 and the source/drain electrode trace 7 can be realized, and the part of the active layer 5 not exposed still maintains the semiconductor characteristic and is used as a channel region.
As shown in fig. 5 and 6, the source/drain electrode trace 7 is disposed on the second substrate layer 6, in the second groove 61 and the contact hole 62, and the source/drain electrode trace 7 is an embedded electrode trace. The source/drain electrode trace 7 is filled in the second groove 61 and the contact hole 62, and extends to the upper surface of the second substrate layer 6. In this embodiment, the source-drain electrode trace disposed in the second groove 61 is defined as a first source-drain electrode trace 71, the source-drain electrode trace disposed on the upper surface of the second substrate layer 6 is defined as a second source-drain electrode trace 72, the source-drain electrode trace disposed in the contact hole 62 is defined as a third source-drain electrode trace 73, from a top view, the first source-drain electrode trace 71 and the second source-drain electrode trace 72 are perpendicular to each other, and the third source-drain electrode 73 serves as an electrical connection channel between the source-drain electrode trace 7 and the active layer 5.
At this time, in a similar manner, since the second groove 61 is a long-strip-shaped groove and has a deeper depth, the volume of the second groove 61 is larger, that is, the proportion occupied by the first source/drain electrode trace 71 disposed in the second groove 61 is larger, the proportion occupied by the second source/drain electrode trace 72 is smaller, the thickness of the second source/drain electrode trace 72 is 0.2 to 0.5 micrometers, and the area of the orthographic projection of the second source/drain electrode trace on the second substrate layer 6 is also micrometer-sized, that is, the line width of the source/drain electrode trace 7 prepared in this embodiment is changed from the original horizontal line width to a vertical line width, on the premise of providing an equal amount of source/drain electrode material, due to the existence of the first source/drain electrode 71, the thickness and the surface area of the second source/drain electrode 72 are greatly reduced, and the horizontal line width of the source/drain electrode trace 7 is reduced to less than 2 micrometers, the line width of the source drain electrode wire 7 is greatly reduced, and the distribution density of the source drain electrode wire 7 is enhanced.
The passivation layer 8 is arranged on the source/drain electrode wiring 7 to prepare a passivation layer 8, the passivation layer 8 is made of an inorganic material, and the inorganic material is an insulating material to form the passivation layer 8. And forming a hole on the passivation layer 8 to form a passivation layer through hole 81, wherein the passivation layer through hole 81 is convenient for the electrode of the sub-pixel 9 to be connected with the source/drain electrode trace 7.
The sub-pixels 9 are arranged on the passivation layer 8 and extend into the passivation layer through holes 81, and the sub-pixels can achieve the light emitting function of the display panel.
Because one sub-pixel 9 corresponds to one source drain electrode wire 7 and one gate wire 3, when the line widths of the gate wire 3 and the source drain electrode wire 7 are reduced, the distribution density of the gate wire 3 and the source drain electrode wire 7 is increased, the distribution density of the sub-pixel 9 is further increased, the aperture opening ratio of the pixel is greatly improved under the condition that the resistance is not additionally increased, and the contrast ratio, the penetration rate or the transparency of the prepared display panel can be improved.
The display panel has the technical effects that most of horizontal line width is changed into vertical line width by the embedded grid routing and/or source-drain electrode routing, the occupied area of the electrode routing on the substrate layer is reduced, the distribution density of the electrode routing is increased, the distribution density of sub-pixels is further increased, the aperture opening ratio of pixels is enhanced, and the contrast ratio, the penetration rate or the transparency of the display panel can be further improved.
The display panel and the manufacturing method thereof provided by the embodiments of the present application are described in detail above, and the principle and the embodiment of the present application are explained herein by applying specific examples, and the description of the embodiments above is only used to help understanding the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A preparation method of a display panel is characterized by comprising the following steps:
providing a substrate;
preparing a substrate layer on the substrate;
preparing a plurality of grooves on the substrate layer; and
preparing electrode wires on the substrate layer and in the groove, wherein the electrode wires are embedded electrode wires.
2. The method for manufacturing a display panel according to claim 1, wherein in the step of manufacturing a plurality of grooves on the substrate layer,
carrying out exposure, development and curing treatment on the substrate layer in sequence to form the groove; the depth of the groove is 2-5 microns.
3. The method for fabricating a display panel according to claim 1, wherein in the step of fabricating electrode traces on the substrate layer and within the grooves,
forming a metal film on the substrate layer and the whole surface in the groove;
patterning the metal film by adopting exposure, development and etching modes to form the electrode wiring;
the electrode routing is filled into the groove and extends to the substrate layer.
4. The method for manufacturing a display panel according to claim 3,
the thickness of the metal film is larger than the depth of the groove;
the thickness of the metal film arranged on the substrate layer is 0.2-0.5 micrometer.
5. The method for manufacturing a display panel according to claim 1,
the step of preparing the electrode wires on the substrate layer and in the groove comprises the steps of preparing the grid wires and preparing the source and drain electrode wires in sequence.
6. The method for manufacturing a display panel according to claim 5, wherein in the step of manufacturing the gate wire,
preparing a first substrate layer on the substrate;
preparing a plurality of first grooves on the first substrate layer; and
and preparing the grid wire on the first substrate layer and in the first groove.
7. The method for manufacturing a display panel according to claim 6, wherein the step of manufacturing the gate trace further comprises:
preparing a grid electrode insulating layer on the first substrate layer and the grid electrode routing;
and depositing a layer of semiconductor material on the grid electrode insulating layer to form an active layer, wherein the active layer is arranged opposite to the grid electrode routing.
8. The method for manufacturing a display panel according to claim 7, wherein in the step of manufacturing source-drain electrode traces,
coating a layer of transparent substrate material on the active layer and the gate insulating layer to form a second substrate layer, and forming a second groove on the second substrate layer;
and forming the source and drain electrode routing in the second deposition layer and the second groove.
9. A display panel, comprising:
a substrate;
the substrate layer is arranged on the substrate; the substrate layer is provided with a plurality of grooves; and
and the electrode routing is filled in the groove and extends to the upper surface of the substrate layer, and the electrode routing is embedded electrode routing.
10. The display panel of claim 9,
the line width of the electrode routing is a vertical line width, and the vertical line width is 2-5 micrometers.
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| CN208766968U (en) * | 2018-09-29 | 2019-04-19 | 昆山国显光电有限公司 | A kind of flexible display panels and flexible display apparatus |
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| CN110752222A (en) * | 2019-10-31 | 2020-02-04 | 厦门天马微电子有限公司 | Display panel, manufacturing method thereof and display device |
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| CN109192761A (en) * | 2018-08-31 | 2019-01-11 | 深圳市华星光电半导体显示技术有限公司 | A kind of display panel and preparation method thereof |
| CN208766968U (en) * | 2018-09-29 | 2019-04-19 | 昆山国显光电有限公司 | A kind of flexible display panels and flexible display apparatus |
| CN109994534A (en) * | 2019-04-23 | 2019-07-09 | 武汉华星光电半导体显示技术有限公司 | The peripheral circuit structure and OLED display panel of OLED display panel |
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