CN113285434A

CN113285434A - Device, system and method for suppressing start-up impact current

Info

Publication number: CN113285434A
Application number: CN202110700857.4A
Authority: CN
Inventors: 黄敏超
Original assignee: Minye Information Technology Shanghai Co Ltd
Current assignee: Minye Information Technology Shanghai Co Ltd
Priority date: 2021-06-23
Filing date: 2021-06-23
Publication date: 2021-08-20

Abstract

The invention provides a device, a system and a method for restraining starting-up impact current. The suppression device has an encapsulated housing with tapped-off input, output and control terminals, and the interior of the suppression device includes: the power supply comprises a control circuit and a transistor, wherein one end of the control circuit is connected with a control end, the transistor comprises a first electrode, a second electrode and a control electrode, the first electrode and the second electrode are respectively connected with an input end and an output end, the control electrode is connected with the control circuit, and the control circuit is suitable for inhibiting start-up impact current. The device, the system and the method for restraining the starting-up impact current have high reliability and strong universality, and can simply and conveniently restrain the starting-up impact current.

Description

Device, system and method for suppressing start-up impact current

Technical Field

The invention mainly relates to the field of control circuits, in particular to a device, a system and a method for suppressing start-up impact current.

Background

The power supply of the electronic device is mainly through an alternating current network or a direct current power supply system, and in order to realize stable power supply, a large-capacity capacitor is usually adopted at the input side for energy storage. However, when the electronic device is turned on, the large-capacity capacitor of the input port is charged instantly, resulting in a huge Inrush Current, called as an Inrush Current (Inrush Current).

When the starting-up impact current occurs, the rear-stage circuit does not start to work, and the soft start function of the rear-stage circuit does not play a role. On the basis, the starting-up impact current can generate instant short circuit on an alternating current power grid or a direct current power supply system, further influences peripheral electronic equipment, and can cause faults of restarting, code disorder, crash and the like of the peripheral electronic equipment in serious cases. The performance indexes of the electronic equipment include a starting-up impact current index which is used for selecting the type of the fuse in the system integration. It follows that the suppression of the inrush current is an important operation in favor of circuit protection and control.

At present, a common method in the field is to connect a thermistor in series at an input end of an electronic device, and to suppress a start-up inrush current by using a negative temperature characteristic of the thermistor that is high resistance at normal temperature and low resistance at high temperature. However, connecting thermistors in series can cause additional losses in the system, significantly reducing overall energy efficiency. Moreover, when the starting is repeated, the thermistor cannot recover high resistance because the thermistor cannot be rapidly cooled to normal temperature, and a large starting impact current still can be caused. In addition, when the electronic device works in a steady state, the thermistor needs to be kept in a low-resistance state, the temperature of the thermistor body needs to be kept at about 80-100 ℃, so that the temperature rise and the reliability of peripheral devices are influenced, and the thermistor can be damaged due to overheating in severe cases.

In order to avoid the above problems, technicians in the field have to use a relay to short-circuit the thermistor after the device is started, so that on one hand, the power consumption of the thermistor can be saved, and on the other hand, the thermistor can be kept in a normal temperature state, thereby maintaining a high resistance state and satisfying the effect of suppressing the starting-up impulse current during repeated starting-up.

However, the addition of the relay brings 2 new disadvantages: firstly, the relay is pulled in and out to generate arc discharge, and the arc discharge can generate electromagnetic interference to cause abnormal work of peripheral equipment. In addition to this, new problems of relay contact reliability are brought about. The relay contacts can be oxidized, which causes the impedance of the short circuit of the relay to increase, and further causes higher power consumption, especially for electronic equipment working for a long time on the coast or outdoors, such as an air conditioner, a photovoltaic inverter and the like. Meanwhile, the elastic sheet of the relay has a fatigue effect, and can cause poor contact closure and even failure after long-term work, so that the purpose of short-circuiting the thermistor cannot be realized, and even the thermistor can be damaged due to overheating in severe cases. Because the thermistor is connected in series at the input end, the aging of the thermistor can directly cause the power supply of the electronic equipment to be cut off and the electronic equipment cannot work, and serious consequences are brought.

Therefore, there is still a lack of a method and means for suppressing the start-up inrush current, which has high versatility and little influence on the entire circuit.

Disclosure of Invention

The invention aims to provide a device, a system and a method for restraining starting-up impact current, which have high reliability and strong universality and can simply and conveniently restrain the starting-up impact current.

In order to solve the above technical problem, the present invention provides a device for suppressing a power-on rush current, wherein the device has a packaged housing, the housing has an input terminal, an output terminal and a control terminal connected thereto, and the interior of the device includes: the power supply comprises a control circuit and a transistor, wherein one end of the control circuit is connected with the control end, the transistor comprises a first electrode, a second electrode and a control electrode, the first electrode and the second electrode are respectively connected with the input end and the output end, the control electrode is connected with the control circuit, and the control circuit is suitable for inhibiting starting-up impact current.

In an embodiment of the present invention, the control circuit includes a first resistor, a second resistor, and a capacitor connected in parallel with the second resistor, where one end of the first resistor is connected to the control terminal, one end of the second resistor is connected to the first resistor, and the other end of the second resistor is connected to the input terminal and the first electrode.

In an embodiment of the present invention, the suppression device further includes a diode connected in parallel with the capacitor.

In an embodiment of the invention, the suppression device further includes a third resistor connected in series between the capacitor and the second resistor.

The invention also provides a system for suppressing the start-up inrush current, which comprises a power supply, a post-stage circuit and a device for suppressing the start-up inrush current, wherein the device is positioned between the power supply and the post-stage circuit, the input end of the device is connected with the power supply, the output end of the device is connected with the post-stage circuit, the control end of the device is connected with the power supply or an external control circuit, and the external control circuit is suitable for independently controlling the voltage of the control end.

In order to solve the above technical problem, the present invention further provides a method for suppressing a power-on inrush current, including the following steps: providing a starting-up impact current suppression device, and connecting an input end, an output end and a control end on a shell of the encapsulated suppression device; connecting the input end to a power supply, connecting the output end to a post-stage circuit, and connecting the control end to the power supply or an external control circuit; and controlling the voltage of the control end to enable the transistor in the suppression device to be in a cut-off area, an impedance change area and an on-state area in sequence when the transistor is started.

In an embodiment of the invention, when the control terminal is connected to the external control circuit, controlling the voltage of the control terminal includes the external control circuit controlling the voltage of the control terminal separately, so that the transistor is in the turn-off region, the impedance change region and the on-state region in turn when the transistor is turned on.

In an embodiment of the present invention, when the power source is an ac output, the input terminal and the output terminal are respectively connected to the power source and a negative electrode of the post-stage circuit, and when the power source is a dc output, the input terminal and the output terminal are respectively connected to the power source and a positive electrode of the post-stage circuit.

Compared with the prior art, the invention has the following advantages: the suppression device, the suppression system and the suppression method of the startup impulse current suppress the startup impulse current according to the impedance characteristic of the transistor impedance change area, further reduce the on-state power consumption during normal operation by using the low-resistance characteristic of the on-state area, and simultaneously realize the protection function of a post-stage circuit by cutting off the connection of the post-stage circuit in the cut-off and turn-off area; on the basis, the suppression means of the startup impulse current only adopts simple circuit arrangement and selects the packaging mode of the external pin, thereby effectively improving the reliability and the universality of the suppression means of the startup impulse current.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the principle of the invention. In the drawings:

fig. 1 is an external view of a device for suppressing a start-up inrush current according to an embodiment of the present invention;

fig. 2 is a schematic diagram of an internal structure of a device for suppressing a start-up inrush current according to an embodiment of the present invention;

FIGS. 3a to 3c are schematic diagrams of internal structures of a device for suppressing a power-on surge current according to another embodiment of the present invention

Fig. 4a and fig. 4b are schematic external views of a system for suppressing a power-on rush current according to an embodiment of the present invention;

fig. 5a and 5b are schematic internal structural diagrams of a system for suppressing a power-on rush current according to an embodiment of the present invention;

fig. 6 is a flowchart illustrating a method for suppressing a power-on rush current according to an embodiment of the present invention.

FIG. 7 is a waveform diagram of a simulation of a circuit; and

fig. 8 is a waveform diagram of a simulation of a system for suppressing a power-on rush current according to an embodiment of the present invention.

Detailed Description

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only examples or embodiments of the application, from which the application can also be applied to other similar scenarios without inventive effort for a person skilled in the art. Unless otherwise apparent from the context, or otherwise indicated, like reference numbers in the figures refer to the same structure or operation.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

The relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

In the description of the present application, it is to be understood that the orientation or positional relationship indicated by the directional terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc., are generally based on the orientation or positional relationship shown in the drawings, and are used for convenience of description and simplicity of description only, and in the case of not making a reverse description, these directional terms do not indicate and imply that the device or element being referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be considered as limiting the scope of the present application; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.

Spatially relative terms, such as "above … …," "above … …," "above … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited. Further, although the terms used in the present application are selected from publicly known and used terms, some of the terms mentioned in the specification of the present application may be selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Further, it is required that the present application is understood not only by the actual terms used but also by the meaning of each term lying within.

It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present. Similarly, when a first component is said to be "in electrical contact with" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow even without direct contact between the conductive components.

An embodiment of the present invention provides a device for suppressing a power-on inrush current, which has high reliability and strong versatility, and can simply and conveniently suppress the power-on inrush current.

Fig. 1 is a schematic external view of a device 10 for suppressing a power-on rush current according to an embodiment of the present invention.

As can be seen in fig. 1, the suppression device 10 has an encapsulated housing (shown using dashed lines) with an input terminal 11, an output terminal 12 and a control terminal 13 connected thereto. The suppression device comprises a control circuit and a transistor, wherein the transistor comprises a first electrode 21, a second electrode 22 and a control electrode 23, the first electrode 21 and the second electrode 22 are respectively connected with the input end 11 and the output end 12, the control electrode 23 is connected with the control circuit, and the control circuit is suitable for suppressing the power-on impact current.

More specifically, in an embodiment of the present invention, an internal structure of the suppression device 10 shown in fig. 1 is schematically shown in fig. 2. As can be seen in fig. 2, the control circuit portion inside the suppression device 10 includes a first resistor R1 and a second resistor R2 connected in series, wherein one end of the first resistor R1 is connected to the control terminal 13, one end of the second resistor R2 is connected to the first resistor R1, and the other end is connected to the input terminal 11. On this basis, the internal control circuit portion of the suppression device 10 also has a capacitor C1 connected in parallel with the second resistor R2. And transistor Q1 within suppression device 10 is connected between input 11 and output 12.

In the embodiment shown in fig. 2, the transistor Q1 has a first electrode 21, a second electrode 22 and a control electrode 23, the first electrode 21 and the second electrode 22 being connected to the input 11 and the output 12, respectively, of the suppression device 10, the control electrode 23 being connected to a control circuit, in particular to the other end of the first resistor R1, in particular to the first resistor R1 having one end connected to the control terminal 13 and the other end connected to the control electrode 23.

Illustratively, in the embodiment shown in fig. 2, the transistor Q1 is an NMOS, the gate of the NMOS (i.e., the control electrode 23) is connected between the first resistor R1 and the second resistor R2, the source of the NMOS (i.e., the input electrode 21) is connected to the input terminal 11, and the drain of the NMOS (i.e., the output electrode 22) is connected to the output terminal 12.

It is to be understood that the present invention is not limited to the kind of the transistor Q1. For example, as shown in fig. 3 a-3 c, the internal structure of the suppressor device 10 with different types of transistors for on-current in other embodiments of the present invention is illustrated. In this case, elements shown in fig. 1 and 2 may be used for other elements except for the type of the transistor, and therefore, the same reference numerals are used for the same parts.

Illustratively, in the embodiment shown in fig. 3a, the transistor Q2 is a PNP transistor, wherein the base (i.e., the control electrode 23) of the PNP transistor is connected between the first resistor R1 and the second resistor R2, the emitter (i.e., the input electrode 21) of the PNP transistor is connected to the input terminal 11, and the collector (i.e., the output electrode 22) of the PNP transistor is connected to the output terminal 12.

In the embodiment shown in fig. 3b, the transistor Q3 is a PMOS, wherein the gate (i.e., the control electrode 23) of the PMOS is connected between the first resistor R1 and the second resistor R2, the source (i.e., the input electrode 21) of the PMOS is connected to the input terminal 11, and the drain (i.e., the output electrode 22) of the PMOS is connected to the output terminal 12.

In the embodiment shown in fig. 3c, the transistor Q4 is an NPN transistor, wherein a base (i.e., the control electrode 23) of the NPN transistor is connected between the first resistor R1 and the second resistor R2, an emitter (i.e., the input electrode 21) of the NPN transistor is connected to the input terminal 11, and a collector (i.e., the output electrode 22) of the NPN transistor is connected to the output terminal 12.

On the basis, in order to further improve the accuracy and the stability of the device for suppressing the power-on rush current according to the present invention, in some embodiments of the present invention, it is preferable that the device further includes a diode (not shown) connected in parallel with the capacitor C1 shown in fig. 2. Further, in some embodiments of the present invention, the suppression device further includes a third resistor (not shown) connected in series between the capacitor C1 and the second resistor R2. However, the present invention is not limited thereto.

The device 10 for suppressing the power-on rush current of the present invention can be simply and conveniently connected to an application circuit through 3 simple external pins (i.e., the input terminal 11, the output terminal 12, and the control terminal 13), so as to suppress the power-on rush current of the circuit. Specifically, the external power supply or other power supply circuit can control the voltage of the control electrode of the transistor, and the transistor characteristics in the suppression device are applied to make the suppression device in different impedance change areas, so that the start-up rush current of the application circuit where the suppression device is located at the time of start-up can be effectively controlled. The principle and effect of the suppression device will be explained in more detail below.

The starting-up impact current suppression device overcomes the limitation of the traditional starting-up impact current suppression mode, adopts a simple integrated circuit arrangement mode and an application mode of an external pin after packaging, has strong universality and high reliability, can adopt an integrated mode for the suppression device in each application circuit, and thus, can simply and conveniently suppress the starting-up impact current.

On the basis of the application of the starting-up impact current suppression device, the suppression system can effectively suppress the starting-up impact current for circuits involved in different application scenes.

Fig. 4a and 4b are schematic external views of a

system

41 and 42 for suppressing a power-on rush current according to an embodiment of the present invention. The

suppression systems

41 and 42 differ only in the connection position of the suppression devices in the system, and therefore, the same reference numerals and signs are used for other identical parts.

As shown in fig. 4a and 4b, when the suppression device 10 of the power-on rush current shown in fig. 1 is applied, the

suppression systems

41 and 42 each include a power supply, a subsequent stage circuit, and the suppression device 10 shown in fig. 1, the suppression device 10 being located between the power supply and the subsequent stage circuit. Specifically, the input terminal 11 of the suppression device 10 is connected to the power supply, the output terminal 12 of the suppression device is connected to the subsequent circuit, and the control terminal 13 of the suppression device is also connected to the power supply.

Specifically, as shown in fig. 4a, the input terminal 11 and the output terminal 12 of the suppression device 10 are connected between the positive output terminal of the power supply and the positive input terminal of the subsequent circuit, and the control terminal 13 of the suppression device 10 is connected between the negative output terminal of the power supply and the negative input terminal of the subsequent circuit.

In contrast, in the embodiment shown in fig. 4b, the input terminal 11 and the output terminal 12 of the suppression device 10 are connected between the output cathode of the power supply and the input cathode of the subsequent circuit, while the control terminal 13 of the suppression device 10 is connected between the output anode of the power supply and the input anode of the subsequent circuit.

It can be understood that when the suppression system of the startup rush current is applied to different application scenarios, the suppression device can be connected between the positive electrode and the negative electrode as required. This may depend on the input characteristics, such as the ac input electronic products, which usually use the cathode series connection to facilitate the driving design. And electronic products with direct current input, such as automotive electronics, photovoltaics and communications, adopt an anode connection mode, because a cathode is a reference ground of a system, all internal components are connected through the cathode, and if a suppression device is connected in series with the cathode, the suppression device is short-circuited by a common ground bypass between the system components, so that the start-up impact current suppression function is lost.

However, the present invention is not limited to the above connection method, and in some other embodiments of the suppression system of the present invention, the suppression device may be connected between the negative input of the power supply and the negative input of the subsequent circuit when the power supply is a dc input, and similarly, the suppression device may be connected between the positive output of the power supply and the positive input of the subsequent circuit when the power supply is an ac output.

Further, as shown in fig. 5a and 5b, they are schematic internal structural diagrams of a system for suppressing a power-on rush current according to an embodiment of the present invention. Fig. 5a and 5b show the internal structure and the corresponding connection in the system when the

suppression systems

41 and 42 shown in fig. 4a and 4b, respectively, are used with the suppression device 10 shown in fig. 2. For the details of the internal structure, reference may be made to the above description of the suppression device shown in fig. 1 to 3c, which is not repeated herein. Moreover, it is understood that the internal structure of a system for suppressing a turn-on rush current according to the present invention is not limited to that shown in fig. 5a and 5b, for example, the transistors shown in fig. 5a and 5b may be replaced with transistors Q2 to Q4 shown in fig. 3a to 3b or other types and kinds, and the present invention is not limited thereto.

In the embodiment shown in fig. 5a and 5b, the voltage of the control electrode 23 of the transistor Q1 can be directly controlled by the voltage input of the power supply and the parameter ratio of each element in the internal structure of the suppression device 10, so that the transistor Q1 is in different impedance change areas by utilizing the characteristics of the transistor Q1, and the damage of the system caused by the impact circuit of the standby circuit during startup can be effectively prevented.

It should be noted that preferably in the embodiment as shown in fig. 5b, the control terminal 13 of the suppression device 10 is not connected to the power supply, but to an external control circuit, and the external control circuit may control the voltage of the control terminal 13 alone. This connection may be used as a preferred mode to control the suppression effect of the suppression device 10 independently of the voltage control of the transistor Q1 in the suppression device 10 from the power supply of the system, thereby meeting the higher requirements of the system coordination control.

The invention further provides a method for restraining the starting-up impact current, the restraining device and the restraining system can be applied to restrain the starting-up impact current simply and conveniently, and the method has the advantages of high reliability and strong universality.

Fig. 6 is a schematic flow chart of a method 60 for suppressing a start-up inrush current according to the present invention. Fig. 6 uses a flowchart in this application to illustrate the operations performed by a system according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes.

As shown in fig. 6, the suppression method 60 includes the following steps.

Step 61: and providing a starting-up impact current suppression device, and connecting an input end, an output end and a control end on a shell of the encapsulated suppression device.

Step 62: the input terminal is connected to a power supply, the output terminal is connected to a subsequent stage circuit, and the control terminal is connected to the power supply or an external control circuit.

And step 63: and controlling the voltage of the control end to enable the transistor in the suppression device to be in a cut-off area, an impedance change area and an on-state area in sequence when the transistor is started.

Specifically, in some embodiments of the present invention, in the step 62, when the control terminal is connected to the external control circuit, the voltage of the control terminal includes the voltage of the control terminal controlled by the external control circuit alone, so that the transistor is in the off-state region, the impedance change region and the on-state region in turn when the transistor is turned on. As an example, as for the connection mode of the external control circuit, the connection mode shown in fig. 5b in the above description of the suppression system may be referred to.

In addition, in some embodiments of the present invention, in step 62, when the power source is an ac output, the input terminal and the output terminal are respectively connected to the power source and the negative electrode of the subsequent circuit, and when the power source is a dc output circuit, the input terminal and the output terminal are respectively connected to the power source and the positive electrode of the subsequent circuit. Such a connection can be referred to in the above description of the suppression system, as in the connection of fig. 4a and 4 b.

The suppression method 60 shown in fig. 6 may employ the suppression device and suppression system described above to perform the steps therein. Therefore, for further details of the suppression method 60 shown in fig. 6, reference may be made to the above description of a suppression device and suppression system of the present invention, which are not repeated herein.

For better understanding of the device, the system and the method for suppressing the power-on rush current of the present invention. The following is a brief description of the simulation effect and actual measurement result of the present invention for suppressing system application in an application circuit.

FIG. 7 shows a simulated waveform of a circuit. The circuit does not apply the suppression device, the suppression system or the suppression method as described above, and only includes a power supply (providing a 24V dc voltage loop), a controlled switch and a post-stage circuit. In fig. 7, AM2 is the input current waveform of the controlled switch, AM4 is the output current waveform of the controlled switch, and VG2 is the voltage waveform of the controlled switch. Where VG 2-0V is after the controlled switch is turned off, VG 2-1V is after the switch SW10 is turned on, and VM4 is the voltage waveform of the capacitor in the subsequent stage.

As can be seen from the simulated waveform diagram shown in fig. 7, when the controlled switch is closed, the input current AM2 generates 200 times of the rated output current spike, which is also the technical problem that the suppression device, the suppression system and the suppression method of the present invention address.

Further, as shown in fig. 8, a simulated waveform diagram of a system for suppressing a power-on rush current according to an embodiment of the present invention is shown.

In fig. 8, AM1 is an input current waveform, AM3 is an output circuit waveform, VF3 is a control voltage waveform of a transistor, VG1 is a voltage signal waveform of a switch, VM1 is a voltage waveform of a switch output terminal and an input negative electrode, and VM2 is a voltage waveform of a capacitor in a subsequent circuit. According to the system for suppressing the power-on rush current, the voltage of the control terminal of the suppressing device is controlled so as to control the voltage of the control electrode of the transistor, so that the transistor is in a cut-off region, an impedance change region and an on-state region in sequence after power-on (refer to the description in step 63 as shown in fig. 6 and the description related to the transistor in the description of the suppressing device and the suppressing system).

As can be seen from fig. 8, the 200 times of the power-on rush current as shown in fig. 7 is effectively suppressed by the impedance variation region of the transistor, thereby achieving the effect of suppressing the power-on rush current. Meanwhile, the low-resistance characteristic of the on-state area is utilized to further reduce the on-state power consumption during normal work, and the cut-off and turn-off area can realize the protection function of the rear-stage circuit by cutting off the connection of the rear-stage circuit.

In summary, the above-mentioned device, system and method for suppressing the power-on rush current of the present invention apply the driving control of the impedance characteristic of the impedance variation region of the transistor by the control circuit, but do not relate to the body temperature. The characteristic well overcomes the defect that the thermistor has high resistance only depending on the body temperature, and compared with the prior art, the starting-up impact current suppression requirement during repeated starting-up can be met.

On the other hand, the low resistance characteristic of the transistor in the on-state area and the body temperature are very small, so that the defect that the thermistor can meet the low resistance characteristic only when the body temperature is at a high temperature is overcome, and the requirement of reducing low on-state loss under different working temperature conditions can be met.

On the basis, the control end of the start-up inrush current suppression device controls the transistor in the internal structure to work in an impedance change region, an off-state region and an on-state low-resistance region as shown in fig. 8. When the rear-stage circuit works abnormally or fails, the control end can be used for switching off the rear-stage circuit, the rear-stage circuit is cut off and unhooked, and the safety of the system is guaranteed.

In summary, the suppression device, the suppression system and the suppression method for the power-on rush current of the present invention adopt the packaged suppression device with the appearance as shown in fig. 1, and the suppression device has three external pins to connect the suppression device in the circuit simply and conveniently without complicated circuit elements and circuit connection modes, so that the suppression of the power-on rush current of the circuit can be realized simply and conveniently.

Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing disclosure is by way of example only, and is not intended to limit the present application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the exemplary embodiments of the present application.

Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.

Similarly, it should be noted that in the preceding description of embodiments of the application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.

Numerals describing the number of components, attributes, etc. are used in some embodiments, it being understood that such numerals used in the description of the embodiments are modified in some instances by the use of the modifier "about", "approximately" or "substantially". Unless otherwise indicated, "about", "approximately" or "substantially" indicates that the number allows a variation of ± 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that may vary depending upon the desired properties of the individual embodiments. In some embodiments, the numerical parameter should take into account the specified significant digits and employ a general digit preserving approach. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the range are approximations, in the specific examples, such numerical values are set forth as precisely as possible within the scope of the application.

Although the present application has been described with reference to the present specific embodiments, it will be recognized by those skilled in the art that the foregoing embodiments are merely illustrative of the present application and that various changes and substitutions of equivalents may be made without departing from the spirit of the application, and therefore, it is intended that all changes and modifications to the above-described embodiments that come within the spirit of the application fall within the scope of the claims of the application.

Claims

1. A device for suppressing a start-up rush current,

the suppressor has an encapsulated housing with tapped-off input, output and control terminals, an

The suppression device comprises a control circuit and a transistor, one end of the control circuit is connected with the control end, the transistor comprises a first electrode, a second electrode and a control electrode, the first electrode and the second electrode are respectively connected with the input end and the output end, the control electrode is connected with the control circuit, and the control circuit is suitable for suppressing start-up impact current.

2. The suppression device according to claim 1, wherein the control circuit includes a first resistor, a second resistor, and a capacitor connected in parallel with the second resistor, wherein one end of the first resistor is connected to the control terminal, one end of the second resistor is connected to the first resistor, and the other end of the second resistor is connected to the input terminal and the first electrode.

3. The suppression device of claim 2, further comprising a diode internal to the suppression device in parallel with the capacitor.

4. The suppression device according to claim 2 or 3, further comprising a third resistor connected in series between the capacitor and the second resistor.

5. A system for suppressing a power-on rush current, comprising a power supply, a subsequent circuit, and a device for suppressing a power-on rush current according to any one of claims 1 to 4, the device being located between the power supply and the subsequent circuit,

the input end of the suppression device is connected with the power supply, the output end of the suppression device is connected with the rear-stage circuit, the control end of the suppression device is connected with the power supply or an external control circuit, and the external control circuit is suitable for independently controlling the voltage of the control end.

6. A method for suppressing start-up inrush current is characterized by comprising the following steps:

providing a starting-up impact current suppression device according to any one of claims 1 to 4, and connecting an input end, an output end and a control end to a shell of the suppression device after packaging;

connecting the input end to a power supply, connecting the output end to a post-stage circuit, and connecting the control end to the power supply or an external control circuit; and

and controlling the voltage of the control end to enable the transistor in the suppression device to be in a cut-off area, an impedance change area and an on-state area in sequence when the transistor is started.

7. The inhibit method of claim 6, wherein when the control terminal is connected to the external control circuit, controlling the voltage of the control terminal comprises the external control circuit controlling the voltage of the control terminal alone so that the transistor is in the turn-off region, the impedance variation region, and the on-state region in sequence when turned on.

8. The suppressing method according to claim 6 or 7, wherein when the power supply is an alternating current output, the input terminal and the output terminal are connected to a negative electrode of the power supply and a negative electrode of the subsequent circuit, respectively, and when the power supply is a direct current output, the input terminal and the output terminal are connected to a positive electrode of the power supply and a positive electrode of the subsequent circuit, respectively.