CN113284992B - Preparation method of light-emitting diode epitaxial wafer - Google Patents

Preparation method of light-emitting diode epitaxial wafer Download PDF

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CN113284992B
CN113284992B CN202110324236.0A CN202110324236A CN113284992B CN 113284992 B CN113284992 B CN 113284992B CN 202110324236 A CN202110324236 A CN 202110324236A CN 113284992 B CN113284992 B CN 113284992B
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CN113284992A (en
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王群
郭志琰
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HC Semitek Suzhou Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

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Abstract

The invention discloses a preparation method of an epitaxial wafer of a light-emitting diode, belonging to the field of manufacturing of light-emitting diodes. When the p-type GaN layer is grown, a first p-type GaN sublayer may be grown on the multi-quantum well layer, and after the first p-type GaN sublayer is grown, the surface of the first p-type GaN sublayer may be uniformly bombarded with an ion beam for a certain period of time. The ion beam uniformly produces more atomic defects on the surface of the first p-type GaN sublayer. When the second p-type GaN sub-layer continues to grow on the first p-type GaN sub-layer, a large amount of stress and staggered annihilation of defects occur at the interface of the second p-type GaN sub-layer and the first p-type GaN sub-layer, atomic defects on the surface, far away from the substrate, of the second p-type GaN sub-layer are fewer, the surface, far away from the substrate, of the second p-type GaN sub-layer is also smoother, the condition that light rays have different light-emitting angles due to the influence of different defects is fewer, and the improvement of the light-emitting consistency of the light-emitting diode is facilitated.

Description

Preparation method of light-emitting diode epitaxial wafer
Technical Field
The invention relates to the field of light emitting diode manufacturing, in particular to a method for preparing a light emitting diode epitaxial wafer.
Background
A light emitting diode is a semiconductor electronic component that can emit light. As a novel high-efficiency, environment-friendly and green solid-state illumination light source, the solid-state illumination light source is rapidly and widely applied, such as traffic signal lamps, automobile interior and exterior lamps, urban landscape illumination, mobile phone backlight sources and the like, and the aim of improving the light emitting efficiency of a chip is continuously pursued by light emitting diodes.
The light emitting diode epitaxial wafer is a basic structure for preparing the light emitting diode, the light emitting diode epitaxial wafer at least comprises a substrate, an n-type GaN layer, a multi-quantum well layer and a p-type GaN layer, and current carriers provided by the n-type GaN layer and the p-type GaN layer are compounded in the multi-quantum well layer to emit light. In a conventional forward light emitting diode, a surface of the p-type GaN layer away from the substrate is used as a light emitting surface. Therefore, the p-type GaN layer needs to maintain uniform flatness at each position of the surface far away from the substrate, so as to ensure that the obtained light emitting diode has high uniformity and consistency. When the p-type GaN layer grows, dislocation in the p-type GaN layer gradually moves to one surface, away from the substrate, of the p-type GaN layer along the growth direction of the p-type GaN layer, so that more atomic-level defects exist on the surface, away from the substrate, of the p-type GaN layer, light rays are affected by different defects, light emitting angles are different, and light emitting consistency of the light emitting diode is affected.
Disclosure of Invention
The embodiment of the disclosure provides a preparation method of an epitaxial wafer of a light emitting diode, which can improve the quality of a p-type GaN layer so as to improve the light emitting consistency of the light emitting diode. The technical scheme is as follows:
the embodiment of the disclosure provides a preparation method of a light emitting diode epitaxial wafer, which comprises the following steps:
providing a substrate;
growing an n-type GaN layer on the substrate;
growing a multi-quantum well layer on the n-type GaN layer;
growing a p-type GaN layer on the multi-quantum well layer;
the p-type GaN layer is grown on the multi-quantum well layer and comprises:
growing a first p-type GaN sub-layer on the multi-quantum well layer;
uniformly bombarding the surface of the first p-type GaN sublayer for 20-300 s by using an ion beam;
growing a second p-type GaN sub-layer on the first p-type GaN sub-layer to form the p-type GaN layer.
Optionally, the ion beam has an energy in a range of 5KeV to 30 KeV.
Optionally, the ion beam includes at least one of N atoms, Ar atoms, and C atoms.
Optionally, the surface of the first p-type GaN sub-layer is bombarded uniformly by using an ion beam for 20-300 s at the temperature of 25-200 ℃.
Optionally, a ratio of the thickness of the first p-type GaN sublayer to the thickness of the second p-type GaN sublayer is 1:1 to 1: 2.
Optionally, the thickness of the first p-type GaN sublayer is 2-5 nm, and the thickness of the second p-type GaN sublayer is 3-10 nm.
Optionally, the substrate is a sapphire substrate with a chamfer angle, the chamfer angle of the sapphire substrate is 0-0.3 degrees, and the chamfer angle of the sapphire substrate is in a [11-20] crystal plane of a hexagonal crystal system.
Optionally, the preparation method further comprises: growing a GaN three-dimensional nucleation layer between the substrate and the n-type GaN layer, wherein the growth rate of the GaN three-dimensional nucleation layer is reduced along the growth direction of the GaN three-dimensional nucleation layer.
Optionally, in the growth direction of the GaN three-dimensional nucleation layer, the growth rate of the GaN three-dimensional nucleation layer is reduced from a first growth rate to a second growth rate, and then from the second growth rate to a third growth rate, the ratio of the first growth rate to the second growth rate is 1: 0.7-1: 0.9, and the ratio of the first growth rate to the third growth rate is 1: 0.4-1: 0.6.
Optionally, the growth time for maintaining the first growth rate is 100-500 s; maintaining the growth time of the second growth rate to be 200-600 s; and maintaining the growth time of the third growth rate to be 300-900 s.
The technical scheme provided by the embodiment of the disclosure has the following beneficial effects:
when the p-type GaN layer is grown, a first p-type GaN sub-layer can be grown on the multi-quantum well layer, and after the first p-type GaN sub-layer is grown, the surface of the first p-type GaN sub-layer is bombarded uniformly for 20-300 s by using ion beams. The ion beam uniformly produces more atomic defects on the surface of the first p-type GaN sublayer. When the second p-type GaN sub-layer continues to grow on the first p-type GaN sub-layer, a large amount of stress and the situation of staggered annihilation of defects occur at the interface of the second p-type GaN sub-layer and the first p-type GaN sub-layer, so that the defects at the interface of the second p-type GaN sub-layer are difficult to continue to extend and grow, the internal defects of the subsequently obtained second p-type GaN sub-layer are few, and the atomic defects of the surface, far away from the substrate, of the second p-type GaN sub-layer are few, so that the surface, far away from the substrate, of the second p-type GaN sub-layer is also flat, light rays are influenced by different defects, the situations of different light-emitting angles are few, and the light-emitting consistency of the light-emitting diode is favorably improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without inventive labor.
Fig. 1 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present disclosure;
fig. 3 is a flowchart of another method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of another light emitting diode epitaxial wafer according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Fig. 1 is a flowchart of a method for manufacturing an led epitaxial wafer according to an embodiment of the present disclosure, and as shown in fig. 1, the method for manufacturing an led epitaxial wafer includes:
s101: a substrate is provided.
S102: an n-type GaN layer is grown on the substrate.
S103: and growing a multi-quantum well layer on the n-type GaN layer.
S104: and growing a p-type GaN layer on the multi-quantum well layer. And growing a p-type GaN layer on the multi-quantum well layer, including: growing a first p-type GaN sub-layer on the multi-quantum well layer; uniformly bombarding the surface of the first p-type GaN sublayer for 20-300 s by using an ion beam; and growing a second p-type GaN sub-layer on the first p-type GaN sub-layer to form a p-type GaN layer.
When the p-type GaN layer is grown, a first p-type GaN sub-layer can be grown on the multi-quantum well layer, and after the first p-type GaN sub-layer is grown, the surface of the first p-type GaN sub-layer is bombarded uniformly for 20-300 s by using ion beams. The ion beam uniformly produces more atomic defects on the surface of the first p-type GaN sublayer. When the second p-type GaN sub-layer continues to grow on the first p-type GaN sub-layer, a large amount of stress and the situation of staggered annihilation of defects occur at the interface of the second p-type GaN sub-layer and the first p-type GaN sub-layer, so that the defects at the interface of the second p-type GaN sub-layer are difficult to continue to extend and grow, the internal defects of the subsequently obtained second p-type GaN sub-layer are few, and the atomic defects of the surface, far away from the substrate, of the second p-type GaN sub-layer are few, so that the surface, far away from the substrate, of the second p-type GaN sub-layer is also flat, light rays are influenced by different defects, the situations of different light-emitting angles are few, and the light-emitting consistency of the light-emitting diode is favorably improved.
Illustratively, the ion beam has an energy in the range of 5KeV to 30 KeV.
When the energy range of the ion beam is within the above range, the ion beam can be more uniformly arranged on the surface of the first p-type GaN sublayer, reasonable atomic defects can be manufactured on the surface of the first p-type GaN sublayer, the dislocation defects can be more favorably staggered and annihilated, and the quality of the finally obtained second p-type GaN sublayer is better.
Optionally, the intensity of the ion beam is 2-80 mA. Reasonable atomic defects can be manufactured on the surface of the first p-type GaN sublayer, so that the dislocation defects can be staggered and annihilated more favorably, and the quality of the finally obtained second p-type GaN sublayer is ensured to be better.
Illustratively, when the ion beam acts on the surface of the first p-type GaN sublayer, the intensity of the ion beam varies by less than or equal to 15% in intensity per centimeter of area. And more uniform and reasonable atomic defects can be made on the surface of the first p-type GaN sublayer.
Optionally, the ion beam includes at least one of N atoms, Ar atoms, and C atoms.
When the ion beam comprises various atoms shown in the previous section, defects can be stably manufactured on the surface of the first p-type GaN sublayer, the ion beam and the gallium nitride material cannot be subjected to chemical reaction and the like, the gallium nitride material is protected to a certain extent, and the decomposition condition of the gallium nitride material is reduced.
Optionally, the ion beam is used for bombarding the surface of the first p-type GaN sub-layer uniformly for 20-300 s under the condition that the temperature is 25-200 ℃.
When ion beams are bombarded, the temperature is in the range above, the surface state of the finally obtained first p-type GaN sublayer is stable, and the quality of a second p-type GaN sublayer growing on the first p-type GaN sublayer is good.
Illustratively, the ratio of the thickness of the first p-type GaN sub-layer to the thickness of the second p-type GaN sub-layer is 1:1 to 1: 2.
The ratio of the thickness of the first p-type GaN sublayer to the thickness of the second p-type GaN sublayer is in the range, the first p-type GaN sublayer can serve as a good growth foundation, good transition from the multi-quantum well layer to a p-type GaN material is guaranteed, meanwhile, the second p-type GaN sublayer can achieve good growth on the first p-type GaN sublayer, and the quality of the finally obtained p-type GaN layer is in a high state.
Illustratively, the thickness of the first p-type GaN sublayer is 2-5 nm, and the thickness of the second p-type GaN sublayer is 3-10 nm.
The thickness of the first p-type GaN sublayer is within the range, the obtained first p-type GaN sublayer can be guaranteed to have good quality, good transition from the multiple quantum well layer to the p-type GaN material is achieved, the quality of the second p-type GaN sublayer grown on the surface after bombardment can be guaranteed, and the overall quality of the finally obtained p-type GaN layer is good. The thickness of the finally obtained p-type GaN layer is only 15nm to the maximum, holes can be effectively provided, and meanwhile, the whole thickness of the p-type GaN layer is thin, and the light absorption effect can be effectively reduced.
Optionally, the substrate is a sapphire substrate with a chamfer angle, the chamfer angle of the sapphire substrate is 0-0.3 degrees, and the chamfer angle of the sapphire substrate is in the [11-20] crystal plane of a hexagonal crystal system.
The substrate is a sapphire substrate, when the angle of the chamfer angle of the sapphire substrate is in the range, the gallium nitride material deposited on the sapphire substrate grows in a step flow mode, the number of screw dislocations generated in the growth process of the gallium nitride material is small, and the overall quality of the gallium nitride material is good.
In other implementations provided by the present disclosure, the angle of the chamfer angle can be in other ranges as well, and the present disclosure is not limited thereto.
Note that an angle between the [11-20] plane of the hexagonal system and the surface of the sapphire substrate is referred to as a chamfer angle of the sapphire substrate.
The led epitaxial wafer structure after step S104 is executed can be seen in fig. 2.
Fig. 2 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present disclosure, and as can be seen from fig. 2, an led epitaxial wafer according to an embodiment of the present disclosure includes a substrate 1, and an n-type GaN layer 2, a multi-quantum well layer 3, and a p-type GaN layer 4 sequentially stacked on the substrate 1. The multiple quantum well layer 3 includes InGaN well layers 31 and GaN barrier layers 32 alternately stacked.
It should be noted that fig. 2 is provided herein for illustrating a specific possible basic structure of the light emitting diode epitaxial wafer, and in other implementations provided by the present disclosure, the light emitting diode epitaxial wafer may also include other hierarchical structures, which are not limited by the present disclosure.
Fig. 3 is a flowchart of another method for manufacturing an led epitaxial wafer according to an embodiment of the present disclosure, and as shown in fig. 3, the method for manufacturing an led epitaxial wafer includes:
s201: a substrate is provided.
Wherein the substrate may be a sapphire substrate. Easy to realize and manufacture.
Optionally, step S201 may further include: and under the hydrogen atmosphere, the time for treating the surface of the substrate is 6-10 min.
For example, the temperature of the reaction chamber may be 1000 to 1200 ℃ and the pressure of the reaction chamber may be 200to 500Torr when processing the surface of the substrate.
In one implementation provided by the present disclosure, the temperature of the reaction chamber may also be 1100 ℃ when processing the substrate, and the time period for processing the surface of the substrate may be 8 min.
Step S201 may further include: and nitriding the surface of the substrate, and paving a layer of nitrogen atoms on the surface of the substrate. Rapid growth of gallium nitride material may be facilitated.
S202: and growing a GaN three-dimensional nucleation layer on the substrate.
In step S202, the growth temperature of the GaN three-dimensional nucleation layer may be decreased along the growth direction of the GaN three-dimensional nucleation layer.
The growth temperature of the GaN three-dimensional nucleation layer is reduced along the growth direction of the GaN three-dimensional nucleation layer, so that the GaN three-dimensional nucleation layer can be promoted to rapidly nucleate at the initial stage, and after the GaN three-dimensional nucleation layer is in an island shape at the later stage, the transverse growth of the GaN three-dimensional nucleation layer is slowed down to promote the longitudinal growth of the GaN three-dimensional nucleation layer, and the volume of each island-shaped structure is increased. A plurality of island-shaped structures which are mutually spaced and have larger volumes are formed on the substrate, and when the island-shaped structures are subsequently combined, fewer defects can be generated at grain boundaries. Compared with the island-shaped structure with small volume obtained by normal growth in the prior art, the island-shaped structure with small volume can generate a lot of defects during subsequent combination.
Illustratively, the growth temperature of the GaN three-dimensional nucleation layer can be reduced in a stepped manner, and the growth temperature of the GaN three-dimensional nucleation layer is reduced by 30-80 degrees each time. The quality of the obtained GaN three-dimensional nucleation layer can be ensured to be better.
Optionally, the growth temperature of the GaN three-dimensional nucleation layer can be reduced from the first growth temperature to the second growth temperature and then reduced from the second growth temperature to the third growth temperature. And the growth time period of the first growth temperature is maintained to be 100-500 s; maintaining the second growth temperature for growth for 200-600 s; the growth time for maintaining the third growth temperature is 300-900 s.
The growth temperature of the GaN three-dimensional nucleation layer adopts the growth conditions in the previous section, so that the quality of the finally obtained island-shaped structure is controlled to be good, the shape of the island-shaped structure is regular, and the quality of the finally obtained gallium nitride after the island-shaped structures are combined is also good.
Illustratively, in the process of maintaining the growth of the GaN three-dimensional nucleation layer at the first growth temperature, the gas environment in the reaction chamber is a pure nitrogen environment; in the process that the GaN three-dimensional nucleation layer maintains the growth at the second growth temperature, the gas environment in the reaction cavity is the mixed environment of hydrogen and nitrogen; and in the process of maintaining the growth of the GaN three-dimensional nucleation layer at the third growth temperature, the gas environment in the reaction cavity is a pure hydrogen environment.
The nitrogen has stronger viscosity, can promote the transverse growth of the island-shaped structure, can promote the longitudinal growth of the island-shaped structure in a hydrogen environment, and the obtained gallium nitride material has better quality, so that the quality of the finally obtained island-shaped structure can be ensured to be better by adopting the gas environment control in the previous section, the merging time of the island-shaped structures can be delayed, and the volume of a single island-shaped structure is increased.
For example, the ratio of hydrogen to nitrogen in the reaction chamber may be 1:1 to 1:2 during the growth of the GaN three-dimensional nucleation layer at the second growth temperature. The quality of the island-shaped structure can be ensured to be better.
In step S202, the growth rate of the GaN three-dimensional nucleation layer may be reduced along the growth direction of the GaN three-dimensional nucleation layer.
The growth rate of the GaN three-dimensional nucleation layer is reduced along the growth direction of the GaN three-dimensional nucleation layer, the rapid nucleation of the GaN three-dimensional nucleation layer at the initial stage can be promoted, the transverse growth of the GaN three-dimensional nucleation layer is slowed down after the GaN three-dimensional nucleation layer is in an island shape at the later stage, the longitudinal growth of the GaN three-dimensional nucleation layer is promoted, and the volume of each island-shaped structure is increased. A plurality of island-shaped structures which are mutually spaced and have larger volumes are formed on the substrate, and when the island-shaped structures are combined subsequently, fewer defects are generated at grain boundaries. Compared with the island-shaped structure with small volume obtained by normal growth in the prior art, the island-shaped structure with small volume can generate a lot of defects during subsequent combination.
Optionally, in the growth direction of the GaN three-dimensional nucleation layer, the growth rate of the GaN three-dimensional nucleation layer is reduced from a first growth rate to a second growth rate, and then is reduced from the second growth rate to a third growth rate, the ratio of the first growth rate to the second growth rate is 1: 0.7-1: 0.9, and the ratio of the first growth rate to the third growth rate is 1: 0.4-1: 0.6.
The quality of the obtained island-shaped structure can be controlled to be good, the shape of the island-shaped structure is regular, and the quality of the gallium nitride finally obtained after the island-shaped structures are combined is also good.
Illustratively, the growth is maintained at the first growth rate for a period of 100-500 s; maintaining the growth time of the second growth rate to be 200-600 s; the growth time for maintaining the third growth rate is 300-900 s.
The growth rate of the GaN three-dimensional nucleation layer adopts the growth conditions in the previous section, so that the quality of the finally obtained island-shaped structure is controlled to be good, the shape of the island-shaped structure is regular, and the quality of the finally obtained gallium nitride after the island-shaped structures are combined is also good.
Optionally, the growth pressure of the GaN three-dimensional nucleation layer is 200-500 torr.
Illustratively, after the growth of the GaN three-dimensional nucleation layer is completed, the GaN three-dimensional nucleation layer can be annealed for 5 to 10 minutes at the temperature of 1000 to 1200 ℃. The growth quality of the GaN three-dimensional nucleation layer can be improved.
S203: and sequentially growing undoped GaN layers on the GaN three-dimensional nucleating layer.
Optionally, the temperature of the reaction cavity is controlled to be 1000-1100 ℃, the pressure of the reaction cavity is controlled to be 100-500 torr, and the undoped GaN layer grows. And obtaining the non-doped GaN layer with better quality.
Illustratively, the thickness of the undoped GaN layer is 0.5-2 micrometers.
S204: and growing an n-type GaN layer on the undoped GaN layer.
Alternatively, the growth temperature of the n-type GaN layer may be 950 to 1200 deg.C, and the growth pressure of the n-type GaN layer may be 200to 500 Torr.
S205: and growing a multi-quantum well layer on the n-type GaN layer.
In step S205, the multiple quantum well layer includes an InGaN well layer and a GaN barrier layer that are alternately grown.
Optionally, the growth temperature and the growth pressure of the InGaN well layer are 700-800 ℃ and 100-300 torr respectively, and the growth temperature and the growth pressure of the GaN barrier layer are 700-900 ℃ and 100-300 torr respectively. The obtained MQW layer has good quality.
Optionally, the thickness of the InGaN well layer is 2-4 nm, and the thickness of the GaN barrier layer is 5-10 nm. The obtained MQW layer has good quality.
S206: and growing an AlGaN electronic barrier layer on the multi-quantum well layer.
The growth temperature of the AlGaN electron blocking layer can be 600-1000 ℃, and the growth pressure of the AlGaN electron blocking layer can be 100-300 Torr. The AlGaN electron blocking layer grown under the condition has good quality, and is beneficial to improving the luminous efficiency of the light-emitting diode.
S207: and growing a p-type GaN layer on the AlGaN electron blocking layer.
Alternatively, the growth pressure of the p-type GaN layer may be 100Torr to 300Torr, and the growth temperature of the p-type GaN layer may be 800 ℃ to 950 ℃.
In one implementation provided by the present disclosure, the growth temperature of the p-type GaN layer may be 900 ℃, and the growth pressure of the p-type GaN layer may be 200 Torr.
S208: and growing a p-type contact layer on the p-type GaN layer.
Alternatively, the growth pressure of the p-type contact layer may be 100Torr to 300Torr, and the growth temperature of the p-type contact layer may be 850 ℃ to 1050 ℃.
In one implementation provided by the present disclosure, the growth temperature of the p-type contact layer may be 950 ℃, and the growth pressure of the p-type contact layer may be 200 Torr.
It should be noted that the method for manufacturing the light emitting diode epitaxial wafer shown in fig. 3 provides a more detailed method for growing the light emitting diode epitaxial wafer compared to the method for manufacturing the light emitting diode shown in fig. 1.
S209: and annealing the light emitting diode epitaxial wafer.
Step S209 may include: adjusting the temperature to 650-850 ℃, and annealing the light-emitting diode epitaxial wafer for 5-15 minutes in a hydrogen atmosphere.
In one implementation provided by the present disclosure, the annealing temperature may be 750 ℃ and the annealing time may be 10 min.
The structure of the led epitaxial wafer after step S209 is completed can be seen in fig. 4.
Fig. 4 is a schematic structural diagram of another light emitting diode epitaxial wafer according to an embodiment of the present disclosure, and as can be seen from fig. 4, in another implementation manner provided by the present disclosure, the light emitting diode epitaxial wafer may include a substrate 1, and a GaN three-dimensional nucleation layer 5, an undoped GaN layer 6, an n-type GaN layer 2, a multi-quantum well layer 3, an AlGaN electron blocking layer 7, a p-type GaN layer 4, and a p-type contact layer 8 grown on the substrate 1.
Alternatively, the substrate 1 may be a sapphire substrate 1. Easy to manufacture and obtain.
Alternatively, the doping element of the n-type GaN layer 2 may be Si, and the doping concentration of the Si element may be 1 × 1018～1×1019cm-3. The overall quality of the n-type GaN layer 2 is good.
Illustratively, the thickness of the n-type GaN layer 2 may be 1 to 5 μm. The obtained n-type GaN layer 2 has good overall quality.
In one implementation provided by the present disclosure, the thickness of the n-type GaN layer 2 may be 3 μm. The present disclosure is not so limited.
Illustratively, the MQW layer 3 includes a plurality of InGaN well layers 31 and GaN barrier layers 32 alternately stacked, the thickness of the InGaN well layers 31 may be 2-5 nm, and the thickness of the GaN barrier layers 32 may be 8-20 nm.
Illustratively, the overall thickness of the multiple quantum well layer 3 may be 50 to 130nm, and the In molar content may be 13 to 25%.
Optionally, the Al content of the AlGaN electron blocking layer 7 may be 0.15 to 0.25. The effect of blocking electrons is better.
Optionally, the thickness of the AlGaN electron blocking layer 7 can be 20-100 nm. The obtained AlGaN electron blocking layer 7 has good quality.
Enough cavities can be provided, and the overall cost of the light-emitting diode epitaxial wafer is not too high.
Optionally, the p-type GaN layer 4 can be doped with Mg, and the thickness of the p-type GaN layer 4 can be 100-200 nm.
Illustratively, the p-type contact layer 8 may have a thickness of 10 to 50 nm.
In the light emitting diode epitaxial wafer structure shown in fig. 4, compared with the light emitting diode epitaxial wafer structure shown in fig. 2, a GaN three-dimensional nucleation layer 5 and an undoped GaN layer 6 which are sequentially stacked are added between a substrate 1 and an n-type GaN layer 2, an AlGaN electron blocking layer 7 for preventing electron overflow is added between a multi-quantum well layer 3 and a p-type GaN layer 4, and a p-type contact layer 8 is further grown on the p-type GaN layer 4. The obtained epitaxial wafer has better quality and luminous efficiency.
It should be noted that, in other implementations provided by the present disclosure, the light emitting diode epitaxial wafer may also include other hierarchical structures, which is not limited by the present disclosure.
It should be noted that, in the embodiment of the present disclosure, a VeecoK 465i or C4 or RB MOCVD (Metal Organic Chemical Vapor Deposition) apparatus is adopted to implement the growth method of the light emitting diode. By using high-purity H2(Hydrogen) or high purity N2(Nitrogen) or high purity H2And high purity N2The mixed gas of (2) is used as a carrier gas, high-purity NH3As an N source, trimethyl gallium (TMGa) and triethyl gallium (TEGa) as gallium sources, trimethyl indium (TMIn) as indium sources, silane (SiH4) as an N-type dopant, trimethyl aluminum (TMAl) as an aluminum source, and magnesium dicylocene (CP)2Mg) as a P-type dopant.
Although the present disclosure has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure.

Claims (3)

1. A preparation method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
growing a GaN three-dimensional nucleating layer on the substrate, wherein the growth rate of the GaN three-dimensional nucleating layer is reduced along the growth direction of the GaN three-dimensional nucleating layer, the growth rate of the GaN three-dimensional nucleating layer is reduced from a first growth rate to a second growth rate in the growth direction of the GaN three-dimensional nucleating layer, and then is reduced from the second growth rate to a third growth rate, the ratio of the first growth rate to the second growth rate is 1: 0.7-1: 0.9, and the ratio of the first growth rate to the third growth rate is 1: 0.4-1: 0.6;
growing an n-type GaN layer on the GaN three-dimensional nucleating layer;
growing a multi-quantum well layer on the n-type GaN layer;
growing a p-type GaN layer on the multi-quantum well layer;
the p-type GaN layer is grown on the multi-quantum well layer and comprises:
growing a first p-type GaN sub-layer on the multi-quantum well layer;
uniformly bombarding the surface of the first p-type GaN sublayer for 20-300 s by using an ion beam, wherein the energy range of the ion beam is 5 KeV-30 KeV, the ion beam at least comprises at least one of N atoms, Ar atoms and C atoms, and the surface of the first p-type GaN sublayer is uniformly bombarded by using the ion beam for 20-300 s at the temperature of 25-200 ℃;
growing a second p-type GaN sublayer on the first p-type GaN sublayer to form the p-type GaN layer, wherein the ratio of the thickness of the first p-type GaN sublayer to the thickness of the second p-type GaN sublayer is 1: 1-1: 2, the thickness of the first p-type GaN sublayer is 2-5 nm, and the thickness of the second p-type GaN sublayer is 3-10 nm.
2. The production method according to claim 1, wherein the substrate is a sapphire substrate having a chamfer angle, the chamfer angle of the sapphire substrate is 0to 0.3 degrees, and the chamfer direction of the sapphire substrate is in a [11-20] crystal plane of a hexagonal system.
3. The method of claim 1, wherein the first growth rate growth is maintained for a period of 100to 500 seconds; maintaining the growth time of the second growth rate to be 200-600 s; and maintaining the growth time of the third growth rate to be 300-900 s.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102024888A (en) * 2009-12-30 2011-04-20 比亚迪股份有限公司 Light-emitting diode and manufacturing method thereof
CN103117344A (en) * 2013-02-05 2013-05-22 海迪科（南通）光电科技有限公司 Light emitting diode (LED) light emitting device and manufacturing method thereof
CN109817776A (en) * 2017-11-22 2019-05-28 比亚迪股份有限公司 A kind of light-emitting diode chip for backlight unit and preparation method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102024888A (en) * 2009-12-30 2011-04-20 比亚迪股份有限公司 Light-emitting diode and manufacturing method thereof
CN103117344A (en) * 2013-02-05 2013-05-22 海迪科（南通）光电科技有限公司 Light emitting diode (LED) light emitting device and manufacturing method thereof
CN109817776A (en) * 2017-11-22 2019-05-28 比亚迪股份有限公司 A kind of light-emitting diode chip for backlight unit and preparation method thereof

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