CN113284840B - FD-SOI back deep channel isolation process based on bonding process - Google Patents
FD-SOI back deep channel isolation process based on bonding process Download PDFInfo
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- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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Abstract
The invention relates to the technical field of semiconductors, and discloses an FD-SOI (field-of-use-silicon on insulator) back deep channel isolation process based on a bonding process, which is characterized in that M first bonding pads are manufactured on a metal connecting line layer on the uppermost layer of a first chip, M second bonding pads are manufactured on a metal connecting line layer on the uppermost layer of a second chip, and then the first chip and the second chip are aligned and bonded, so that the M first bonding pads on the first chip and the M second bonding pads on the second chip are electrically connected one by one, the area required for integrating the first chip and the second chip can be reduced, in addition, an isolation groove in the first chip and an isolation groove in the second chip are arranged up and down, the proportion of the isolation groove in the whole chip area is reduced, and further the chip area can be reduced; and finally, the second chip is simultaneously manufactured with deep channel isolation when the through hole layer is manufactured, so that the manufacturing cost and the manufacturing period of the chip are greatly reduced, and the isolation effect of the chip device is enhanced by evolving from the shallow channel isolation to the deep channel isolation.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a FD-SOI back deep trench isolation process based on a bonding process.
Background
At present, in a chip manufacturing process, different circuit modules on a chip are mostly manufactured on different wafers according to the manufacturing process, then the circuit modules are tiled and integrated on the same bottom plate, so that the circuit modules are electrically connected, and finally the bottom plate is packaged to form a final finished product. For example, a single chip integrated with a central processing unit CPU, a random access memory RAM, a read only memory ROM, various I/O ports and interrupt systems, and a timer/counter. However, as the functions of the chip are increased, the number of circuit modules in the chip is increased, and if the circuit modules are still laid on the bottom plate, the area of the chip is increased. In addition, in the process of manufacturing the chip, isolation trenches are needed between the components of the circuit modules on the wafer to achieve insulation between the components, and if all the circuit modules are tiled on the bottom plate, the area occupied by the isolation trenches in each circuit module also increases the overall area of the chip, for example, when shallow trench isolation and deep trench isolation are laterally distributed in fig. 2, the overall area of the chip includes the area of the shallow trench isolation and the area of the deep trench isolation.
In the development process of the MOS transistor, the FD-SOI transistor based on the SOI ultra-thin silicon-on-insulator technology is more suitable for low power applications due to its small drain/source parasitic capacitance, lower delay and dynamic power consumption of the device, and independent threshold voltage on gate bias. In addition, compared with a bulk silicon-based MOS tube or a FinFET, the FD-SOI transistor can greatly improve the performance of a chip due to the flexible and adjustable back bias. However, as shown in fig. 1, the back bias control terminal of the FDSOI transistor on the conventional wafer is led out from the wafer, and the back bias control terminal competes for the metal interconnection area with the gate, the source and the drain, and this structure often results in a larger chip area for the FDSOI transistor than the conventional bulk silicon or FinFET.
In addition, in the manufacturing process of the FDSOI-based chip, an isolation trench is firstly manufactured on a wafer, then an FDSOI transistor is manufactured on the wafer, and finally a back bias through hole is manufactured on the FDSOI transistor.
Disclosure of Invention
In view of the deficiencies of the background art, the present invention provides a FD-SOI backside deep trench isolation process based on a bonding process to reduce the area of the FDSOI transistor-based chip and the manufacturing cost of the chip.
In order to solve the technical problems, the invention provides the following technical scheme: a FD-SOI back deep channel isolation process based on bonding process comprises the following steps:
s1: manufacturing a first chip on a first wafer, manufacturing M first bonding pads on a metal connecting line layer on the uppermost layer of the first chip, wherein M is a positive integer, and manufacturing contact pads on a tungsten through hole layer of the first chip;
s2: manufacturing a second chip on the second wafer, and manufacturing M second bonding pads on a metal connecting line layer on the uppermost layer of the second chip;
s3: aligning and bonding the first chip and the second chip, and electrically connecting M first bonding pads on the first chip with M second bonding pads on the second chip one by one;
s4: firstly, thinning a substrate of a second chip on a second wafer, and then injecting ions on the substrate of the second chip to form an ion layer, wherein the ion layer is arranged corresponding to an FDSOI transistor on the second chip;
s5: firstly, generating an oxide layer on a substrate of a second chip, then coating photoresist on the oxide layer, and then defining the position of a back bias through hole, the position of a silicon through hole and the position of an isolation groove on the photoresist through exposure and development processes;
s6: etching the defined back bias through hole to the substrate of the second chip, etching the defined silicon through hole to the contact Pad, and etching the isolation groove until the isolation groove passes through the top silicon of the second chip;
s7: filling an insulating medium in the isolation trench;
s8: and filling metal in the silicon through hole and the back bias through hole.
Optionally, in a certain embodiment, the M first bonding pads are uniformly distributed on the metal wiring layer of the uppermost layer of the first chip, and the M second bonding pads are uniformly distributed on the metal wiring layer of the uppermost layer of the second chip.
Optionally, in a certain embodiment, the method further includes step S9, in step S9, a second oxide layer is formed on the oxide layer, and then a first metal connection line and a second metal connection line are respectively formed in the second oxide layer, the first metal connection line is electrically connected to the metal in the through silicon via, and the second metal connection line is electrically connected to the metal in the back bias via.
Optionally, in a certain embodiment, the first metal connection line and the second metal connection line respectively include at least one metal Pad, the metal of the silicon via is electrically connected to the metal Pad on the first metal connection line, and the metal in the back bias via is electrically connected to the metal Pad on the second metal connection line.
Optionally, in an embodiment, the metal in the back-biased vias of the plurality of FDSOI transistors in the second chip is electrically connected to one metal Pad. .
Optionally, in a certain embodiment, in step S1, a shallow isolation trench is formed on the first wafer in the isolation region of the first chip, and the depth of the isolation trench is greater than that of the shallow isolation trench.
Optionally, in a certain embodiment, the isolation trench is filled with silicon dioxide by an ALD process in step S7.
Optionally, in an embodiment, the isolation trench has an inverted trapezoid shape.
Compared with the prior art, the invention has the beneficial effects that:
1: in the chip structure, the first chip and the second chip are connected in a bonding mode instead of being flatly laid on the bottom plate and then connected through the metal circuit, so that the area required by the integration of the first chip and the second chip is reduced, and in addition, the isolation groove in the first chip and the isolation groove in the second chip are vertically arranged up and down instead of transversely arranged, so that the area occupied by the isolation groove in the chip can be reduced, and the whole area of the chip is further reduced;
2: after the first wafer is bonded with the second wafer, the back bias control end of the FDSOI transistor in the second chip is led out upwards from the substrate of the second chip, so that the metal area of the FDSOI transistor does not compete with the source electrode, the drain electrode and the grid electrode of the FDSOI transistor, the area of the FDSOI transistor is reduced, and the area of the whole second chip can be further reduced.
3: the position of the back bias voltage through hole, the position of the isolation groove and the position of the silicon through hole can be simultaneously defined through one photomask, so that the processing steps are saved, the number of photomasks adopted in actual use is reduced, the cost is further saved, and in addition, the depth of the isolation groove on the second chip is larger than that of the shallow isolation groove on the first chip, and the isolation effect is enhanced.
Drawings
Fig. 1 is a schematic diagram of a lead-out structure of a back bias control terminal of an FDSOI transistor in a conventional chip;
FIG. 2 is a schematic diagram of the distribution of shallow trench isolation and deep trench isolation in a conventional chip;
FIG. 3 is a schematic diagram of the back bias control terminal of the FDSOI transistor according to the present invention;
FIG. 4 is a process flow diagram of the present invention;
fig. 5 is a schematic structural diagram illustrating a first chip, a first bonding Pad and a contact Pad fabricated on a first wafer according to an embodiment;
fig. 6 is a schematic structural view illustrating a second chip and a second bonding Pad fabricated on a second wafer according to the embodiment;
FIG. 7 is a schematic structural diagram of the bonded first and second wafers;
FIG. 8 is a schematic view of the second wafer of FIG. 7 after thinning the substrate and implanting ions;
FIG. 9 is a schematic diagram of an embodiment defining a back bias via;
FIG. 10 is a schematic diagram of an embodiment defining a through silicon via and an isolation trench;
FIG. 11 is a schematic structural diagram of an etched silicon via, an isolation trench, and a back-biased via in an embodiment;
fig. 12 is a schematic structural diagram of a chip structure according to the present invention.
Detailed Description
The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic views illustrating only the basic structure of the present invention in a schematic manner, and thus show only the constitution related to the present invention.
As shown in fig. 4, a FD-SOI backside deep trench isolation process based on a bonding process includes the following steps:
s1: manufacturing a first chip 101 on a first wafer 100, manufacturing M first bonding pads 103 on a metal connection layer 102 on the uppermost layer of the first chip 101, wherein M is a positive integer, and manufacturing a contact Pad104 on a tungsten via layer of the first chip 101;
a schematic structural diagram of the first wafer 100 after the first chip 101, the first bonding Pad103 and the contact Pad104 are manufactured can be referred to fig. 5, where the second chip 101, the first bonding Pad103 and the contact Pad in fig. 5 are only schematic, and specific structures thereof can be determined according to actual requirements;
s2: manufacturing a second chip 201 on the second wafer 200, and manufacturing M second bonding pads 203 on the metal wiring layer 202 on the uppermost layer of the second chip 201;
as a schematic structural diagram of the second chip 201 and the second bonding Pad203 fabricated on the second wafer 200, referring to fig. 6, the second chip 201 in fig. 6 includes four FDSOI transistors, and when actually fabricated, specific circuits of the second chip 201 and a position of the second bonding Pad203 in the metal wiring layer 202 on the uppermost layer of the second chip 201 may be determined according to an actual design;
additionally, the first wafer 100 and the second wafer 200 may be FDSOI wafers, Epi wafers, or Lowcop wafers;
s3: aligning and bonding the first chip 101 and the second chip 201, so that the M first bonding pads 103 on the first chip 101 are electrically connected with the M second bonding pads 203 on the second chip 201 one by one;
a schematic structural diagram of the bonded first chip 101 and second chip 201 is shown in fig. 7, where positions of the second bonding Pad203 and the first bonding Pad103 in fig. 7 are arranged vertically and correspondingly, that is, after the first chip 101 and the second chip 201 are bonded, one first bonding Pad103 and one second bonding Pad are attached to each other;
s4: firstly, thinning the substrate of the second chip 201 on the second wafer 200, and then performing ion implantation on the substrate of the second chip 201 to form an ion layer 204, wherein the ion layer 204 is arranged corresponding to the FDSOI transistor on the second chip;
fig. 8 can be referred to in a schematic structural diagram of the substrate of the second chip 201 after thinning and ion implantation, where an arrow direction in fig. 8 is an ion implantation direction, an arrow range is an ion implantation interval, and the ion implantation interval in fig. 8 is only schematic, and an actually implanted ion interval may be determined according to design requirements;
s5: referring to fig. 9, 10 and 11, in this step, an oxide layer 312 is first formed on the substrate of the second chip 201, then a photoresist is coated on the oxide layer 312 to form a photoresist layer 300, and then a position of a back bias via 301, a position of a through silicon via 303 and a position of an isolation trench 302 are defined on the photoresist layer 300 through an exposure and development process, in fig. 8, the defined position of the back bias via is a blank portion in the photoresist layer 300, the defined position of the through silicon via 303 in fig. 9 is a leftmost blank region in the photoresist layer 300, and the defined position of the isolation trench 302 in fig. 9 is five blank regions on the right side in the photoresist layer 300;
s6: etching the defined back bias through hole 301 to the substrate of the second chip 201, etching the defined silicon through hole 303 to the contact Pad104, and etching the isolation trench 302 until the isolation trench 302 penetrates through the top silicon of the second chip;
fig. 11 shows a schematic structure of the first chip 101 and the second chip 102 after etching back bias vias 301, through-silicon vias 302 and isolation trenches 302;
s7: filling an insulating medium in the isolation trench 302 to form an insulating layer 309;
alternatively, the isolation trench may be filled with silicon dioxide by an ALD process;
s8: filling metal in the silicon through hole 303 and the back bias through hole 301;
s9: referring to fig. 12, in the present step, a second oxide layer 306 is formed on the oxide layer 312, and then a first metal connection line 308 and a second metal connection line 307 are respectively formed in the second oxide layer 306, wherein the first metal connection line 308 is electrically connected to the metal 310 in the silicon via 303, and the second metal connection line 307 is electrically connected to the metal in the back bias via 301.
As a further technical solution, referring to fig. 12, in this embodiment, the second chip 201 in fig. 12 only takes four FDSOI transistors as an example, the second metal connection line 307 includes an upper metal Pad311 and a lower two metal pads 311, the metal in the back bias vias 301 of the two FDSOI transistors on the left side is electrically connected to the metal Pad311 on the left side below the second metal connection line 307, the metal in the back bias vias 301 of the two FDSOI transistors on the right side is electrically connected to the metal Pad311 on the right side below the second metal connection line 307, the two metal pads 311 below the second metal connection line 307 is electrically connected to the metal Pad311 on the second metal connection line 307, so that in actual use, the metal in the back bias vias 301 of all FDSOI transistors in a certain range can be connected to the metal Pad311 on the second metal connection line 307, for example, the metal in the back bias vias 301 of Z N-type FDSOI transistors can be electrically connected to one metal Pad311 on the second metal connection line 307, or the metal in the back bias holes 301 of the Y P-type FDSOI transistors is electrically connected with one metal Pad311 on the second metal connection line 307, and Y and Z are positive integers. In addition, the second metal connection lines 307 in fig. 9 are only schematically illustrated, and four or more metal pads 311 may be disposed according to the position of the FDSOI transistor in the actual second chip 201, and all the metal pads 311 may be disposed in multiple layers.
In practical use, the FDSOI transistor can be adjusted when a control voltage is input to the metal in the back bias via 301 through the second metal connection line 307.
As a further technical solution, in this embodiment, the M first bonding pads 103 are uniformly distributed on the metal wiring layer 102 on the uppermost layer of the first chip 101, and the M second bonding pads 203 are uniformly distributed on the metal wiring layer 202 on the uppermost layer of the second chip 201. Wherein the uniform distribution includes that when the M first bonding pads 103 are distributed in a single row, the distance between every two adjacent first bonding pads 103 is the same; when the M first bonding pads 103 are distributed in multiple rows, the pitch of every two adjacent rows of first bonding pads 103 is the same, and the pitch between every two adjacent first bonding pads 103 in all the rows is the same; when the M first bonding pads 103 are distributed in a circular shape, the distance between every two adjacent first bonding pads 103 is the same.
In addition, in actual use, the M first bonding pads 103 may also be unevenly distributed, and the distribution of the first bonding pads 103 may be determined according to actual requirements.
As a further technical solution, in this embodiment, after the first chip 101 and the second chip 201 are bonded, the through silicon via 303 extends to the top of the first chip 101, and the circuit in the first chip 101 performs signal interaction with the peripheral circuit through the contact Pad104 and the metal 310 in the through silicon via 303. In addition, in practical use, the contact Pad104 may be disposed on the periphery of the first chip 101, or the contact Pad104 on the tungsten via layer is located on the periphery of the first chip 101, which may be determined according to practical requirements.
As a further technical solution, as shown in fig. 11, since the second chip 201 has only four FDSOI transistors, in this embodiment, five isolation trenches 302 are formed on the second wafer 200, each of the five isolation trenches 302 is in an inverted trapezoid shape, and one FDSOI transistor is disposed between every two adjacent isolation trenches 302.
In addition, in actual use, corresponding isolation trenches 302 may be formed in the second wafer 200 according to the component composition and distribution positions of the circuit of the second chip 201, so as to implement isolation of the components on the second chip 201, and the isolation trenches may also be designed in a rectangular shape.
As shown in fig. 12, in the present embodiment, in step S1, when the first chip 101 is fabricated on the first wafer 100, a shallow isolation trench 313 is fabricated on the first wafer to implement isolation between components of the first chip 101.
In conclusion, the invention has the following beneficial effects:
firstly, in the chip structure of the invention, the first chip 101 and the second chip 201 are connected in a bonding mode, rather than being connected through a metal circuit after being tiled on a bottom plate, so that the area required by integrating the first chip 101 and the second chip 201 is reduced;
secondly, after the first wafer 100 and the second wafer 200 are bonded, since the back bias control terminal of the FDSOI transistor in the second chip 101 is led out upward from the substrate of the second chip 201, specifically referring to fig. 2, the source, the drain and the gate of the FDSOI transistor do not compete for the metal area, the area of the FDSOI transistor is reduced, and the area of the entire second chip 201 can be reduced;
finally, the positions of the back bias voltage through hole 301, the isolation groove 302 and the silicon through hole 303 can be simultaneously defined by one photomask, so that the manufacturing process steps are saved, the number of photomasks adopted in the practical use of the invention is reduced, and the cost is further saved.
In light of the foregoing, it is to be understood that various changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.
Claims (8)
1. A FD-SOI back deep channel isolation process based on bonding process is characterized in that: the method comprises the following steps:
s1: manufacturing a first chip on a first wafer, manufacturing M first bonding pads on a metal connecting line layer on the uppermost layer of the first chip, wherein M is a positive integer, and manufacturing contact pads on a tungsten through hole layer of the first chip;
s2: manufacturing a second chip on the second wafer, and manufacturing M second bonding pads on a metal connecting line layer on the uppermost layer of the second chip;
s3: aligning and bonding the first chip and the second chip, and electrically connecting M first bonding pads on the first chip with M second bonding pads on the second chip one by one;
s4: firstly, thinning a substrate of a second chip on a second wafer, and then injecting ions on the substrate of the second chip to form an ion layer, wherein the ion layer is arranged corresponding to an FDSOI transistor on the second chip;
s5: firstly, generating an oxide layer on a substrate of a second chip, then coating photoresist on the oxide layer, and then defining the position of a back bias through hole, the position of a silicon through hole and the position of an isolation groove on the photoresist through exposure and development processes;
s6: etching the defined back bias through hole to the substrate of the second chip, etching the defined silicon through hole to the contact Pad, and etching the isolation groove until the isolation groove passes through the top silicon of the second chip;
s7: filling an insulating medium in the isolation trench;
s8: and filling metal in the silicon through hole and the back bias through hole.
2. The FD-SOI backside deep trench isolation process based on bonding process of claim 1, wherein: in step S1, the M first bonding pads are uniformly distributed on the metal wiring layer of the uppermost layer of the first chip, and in step S2, the M second bonding pads are uniformly distributed on the metal wiring layer of the uppermost layer of the second chip.
3. The FD-SOI backside deep trench isolation process based on bonding process of claim 1, wherein: and step S9, in step S9, a second oxide layer is formed on the oxide layer, and then a first metal connection line and a second metal connection line are formed in the second oxide layer, wherein the first metal connection line is electrically connected to the metal in the silicon via, and the second metal connection line is electrically connected to the metal in the back bias via.
4. The FD-SOI backside deep trench isolation process based on bonding process of claim 3, wherein: the first metal connecting line and the second metal connecting line respectively comprise at least one metal Pad, the metal of the silicon through hole is electrically connected with the metal Pad on the first metal connecting line, and the metal in the back bias through hole is electrically connected with the metal Pad on the second metal connecting line.
5. The FD-SOI backside deep trench isolation process based on bonding process of claim 4, wherein: the metal in the back-biased vias of the plurality of FDSOI transistors in the second chip is electrically connected to one metal Pad.
6. The FD-SOI backside deep trench isolation process based on bonding process of claim 1, wherein: in step S1, a shallow isolation trench is formed in the isolation region of the first chip on the first wafer, and the depth of the isolation trench is greater than that of the shallow isolation trench.
7. The FD-SOI backside deep trench isolation process based on bonding process of claim 1, wherein: in step S7, the isolation trench is filled with silicon dioxide by an ALD process.
8. The FD-SOI backside deep trench isolation process based on bonding process of claim 1, wherein: the isolation trench is in an inverted trapezoidal shape.
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| JP2001284596A (en) * | 2000-03-31 | 2001-10-12 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
| CN109841561A (en) * | 2019-01-07 | 2019-06-04 | 中国科学院微电子研究所 | A kind of SOI device structure and preparation method thereof |
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