CN113272900A

CN113272900A - Memory circuit package with adjustable active channel count

Info

Publication number: CN113272900A
Application number: CN201980085585.2A
Authority: CN
Inventors: D·J·哈伯德
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2018-12-07
Filing date: 2019-11-15
Publication date: 2021-08-17
Also published as: WO2020117451A1; EP3891740A4; US20200183622A1; EP3891740A1

Abstract

Various embodiments described herein provide a memory circuit package that includes a plurality of memory dies, a plurality of external memory channel interfaces, and a multiplexer circuit. The multiplexer circuit may selectively couple at least one memory die to a first external memory interface (of the plurality of external memory channel interfaces) or a second external memory channel interface (of the plurality of external memory channel interfaces) based on a control input, thereby facilitating adjustment of an active memory channel count of the memory circuit package.

Description

Memory circuit package with adjustable active channel count

Priority application

This application claims priority to U.S. application serial No. 16/213,720, filed on 7/12/2018, which is incorporated herein by reference.

Technical Field

Embodiments of the present disclosure relate generally to a memory and, more particularly, to an adjustable count memory circuit package with active memory channels.

Background

The memory subsystem may be a storage system, such as a Solid State Drive (SSD), and may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, a host system may utilize a memory subsystem to store data at and retrieve data from memory components.

Drawings

The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure.

FIG. 1 is a block diagram illustrating an example computing environment including a memory subsystem in accordance with some embodiments of the present disclosure.

FIG. 2 is a block diagram of an example memory circuit package with adjustable counting of active memory channels according to some embodiments of the present disclosure.

Fig. 3 and 4 are diagrams of example memory circuit packages with adjustable active memory channel counts, according to some embodiments of the present disclosure.

Fig. 5 is a flow diagram of an example method for adjusting an active memory channel count of a memory circuit package, according to some embodiments of the present disclosure.

FIG. 6 provides an interaction diagram illustrating interactions between components of a computing environment in the context of performing an example embodiment of a method for adjusting an active memory channel count of a memory circuit package.

Fig. 7 is a block diagram illustrating a diagrammatic representation of a machine in the form of a computer system within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, may be executed according to some embodiments of the present disclosure.

Detailed Description

Aspects of the present disclosure relate to a memory circuit package with an adjustable count of active memory channels that may be used by a memory subsystem or a portion of a memory subsystem. The memory subsystem is also referred to hereinafter as a "memory device". An example of a memory subsystem is a storage system, such as an SSD. In some embodiments, the memory subsystem is a hybrid memory/storage subsystem. In general, a host system may utilize a memory subsystem that includes one or more memory components. The host system may provide data to be stored at the memory subsystem (e.g., via a write request) and may request data to be retrieved from the memory subsystem (e.g., via a read request).

The memory subsystem may contain a number of memory components that may store data from the host system. The memory subsystem may further include a memory subsystem controller that may communicate with each of the memory components to perform operations such as reading data, writing data, or erasing data at the memory components in response to requests received from the host system. Any one or more of the memory components of the memory subsystem may include a media controller to manage memory cells of the memory components, communicate with the memory subsystem controller, and execute memory requests (e.g., reads or writes) received from the memory subsystem controller.

Conventional memory circuit packages, such as Dual Die Package (DDP)/four die package (QDP)/eight die package (8 DP)/sixteen die package (16DP) NAND (NAND) type flash memory circuit packages (hereinafter NAND memory packages), have been designed with a fixed number of active (operational) memory channels (e.g., 2 or 4 NAND memory channels). For example, a conventional nand memory package may include a fixed number of active nand channels, such as one channel, two channels, or four channels. Thus, to meet the demand for different memory channel configurations, memory manufacturers separately manufacture several different Stock Keeping Unit (SKU) memory circuit packages that combine different nand memory package types (e.g., DDP, QDP, 8DP, 16DP) with different fixed memory channel configurations (e.g., one channel, two channel, four channel). Each unique memory circuit package SKU can result in a separate resource being used to manufacture the unique memory circuit package SKU (e.g., a resource used to generate/maintain a separate memory circuit design for the SKU, a resource used to perform a separate qualification on the SKU, a resource used to manage the supply chain for the SKU, etc.). In addition, with a fixed configuration of active memory channels, conventional memory circuit packages fail to provide flexibility in switching between different active memory channel modes, which may be used in certain memory applications/solutions.

Various embodiments described herein provide a memory circuit package, such as a nand memory package, with an adjustable count of active memory channels (also referred to herein as an adjustable active memory channel count), which may allow the memory circuit package to provide a flexible number of active and inactive memory channels (e.g., nand memory channels). As used herein, a "memory circuit package" may include one or more memory dies (e.g., nand dies) encapsulated within the memory circuit package and accessible (e.g., for data reads and data writes) by one or more memory channels of the memory circuit package, which may be accessed by an external memory channel interface. The memory circuit package may be implemented as a surface-mounted Integrated Circuit (IC) package (e.g., a circuit carrier) having an external pin layout (e.g., according to an industry standard) and capable of being mounted on a circuit substrate (e.g., a Printed Circuit Board (PCB)). An example of a circuit package type may include, but is not limited to, a Ball Grid Array (BGA) package, such as a low-profile ball grid array (LBGA) package. As used herein, a "memory die" may comprise a block of semiconductive material that implements a memory Integrated Circuit (IC). Examples of memory dies may include, but are not limited to, nand memory dies (hereinafter nand dies). Additionally, as used herein, an "external memory channel interface" may include one or more external pins that facilitate data communication with a memory die of a memory circuit package through a memory channel of the memory circuit package.

According to an embodiment, the count of active memory channels provided by the memory circuit package may be controlled (e.g., dynamically controlled) by one or more external pins of the memory circuit package (e.g., disposed on an external surface of the memory circuit package) or by one or more commands transmitted to the memory circuit package via an external hardware interface (e.g., disposed on an external surface of the memory circuit package) to command or control the memory die of the memory circuit package. According to embodiments, switching between different active memory channel counts may be controlled by a controller of a memory subsystem (where the memory subsystem includes the memory circuit packages described herein), or by a controller of a memory component, where the memory component includes the memory circuit packages (which may or may not be part of the memory subsystem).

Additionally, for some embodiments, the memory circuit package includes one or more multiplexer circuits or the like to control one or more electrical connections between one or more memory dies (e.g., nand dies) of the memory circuit package and one or more external memory channel hardware interfaces of the memory circuit package (e.g., disposed on an external surface of the memory circuit package). These multiplexer circuits of the memory circuit package may be controlled by external pins of the memory circuit package or by a controller controlled through the external hardware interface. For some embodiments, the memory die of the memory circuit package that is accessible by the active memory channel prior to the adjusting of the active memory channel count is the same as the memory die that is accessible by the active memory channel after the adjusting of the active memory channel count. Thus, the same memory die of the memory circuit package may be accessed regardless of the current count of active (operational) memory channels.

By using the various embodiments described herein, a memory circuit package (e.g., a nand memory package) may have the flexibility to switch between different active memory channel counts (e.g., between two and four channels or between one and two channels) while maintaining access to the same memory die (e.g., nand die) of the memory circuit package. Different configurations of active memory channel counts may be referred to as different memory channel patterns, such as a one-channel (1Ch) pattern, a two-channel (2Ch) pattern, and a four-channel (4Ch) pattern. For example, according to one embodiment, a QDP nand memory package may be designed to operate in a two-channel or four-channel configuration (e.g., determine the configuration based on the settings of one or more external pins). Such QDP and nand memory packages can be produced based on a single circuit design, involving only a single qualification process, and can be used for larger circuit designs (e.g., Printed Circuit Boards (PCBs)) that are specifically designed to use (e.g., utilize) the ability of the QDP and nand memory packages to adjust between a two-channel mode or a four-channel mode. For some embodiments, the memory circuit package includes one or more integrated input/output expanders (IOEs) that may be coupled to the external memory channel interface through one or more multiplexer circuits to facilitate switching between different active memory channel counts/modes. For example, according to one embodiment, a 16DP nand memory package may include one or more IOEs configured such that the 16DP nand memory package may switch between a one channel mode and a two channel mode. For some embodiments, the IOE of a memory circuit package may split the load across multiple memory dies while redriving electrical signals through the IOE.

Memory manufacturers can provide memory circuit packages having different memory channel configurations with fewer memory circuit package SKUs by manufacturing the memory circuit packages of the various embodiments described herein as compared to manufacturing conventional memory circuit packages. With fewer memory circuit package SKUs, a memory manufacturer may use fewer resources in producing various memory circuit packages having different memory channel configurations (e.g., fewer numbers of memory circuit designs that need to be created/maintained, fewer numbers of individual qualifications that need to be performed, simpler supply chain management, etc.).

Additionally, the memory circuit packages of some embodiments may enable (or otherwise facilitate) a reduction in power consumption of a system (e.g., a memory subsystem) using the memory circuit packages described herein. In particular, for some embodiments, the memory subsystem includes the memory circuit package described herein, and when the memory subsystem enters a lower power or low performance mode (e.g., from a normal or high power/performance mode), a controller of the memory subsystem may adjust (or cause adjustment of) an active (operational) memory channel count of the memory circuit package (e.g., from four active memory channels to two active memory channels), thereby causing the controller to use fewer memory channels to access the memory die of the memory circuit package than before (adjustment). As described herein, for some embodiments, the memory die of the memory circuit package that is accessible by the active memory channel prior to the adjustment of the active memory channel count is the same as the memory die that is accessible by the active memory channel after the adjustment. As the memory channel count decreases, the controller may disable one or more portions of the controller (e.g., power islands, such as memory channel portions, parity engine portions, etc.) that are not currently being used by the controller due to the decrease in active memory channels of the memory circuit package. Disabling one or more of the portions of the controller may cause the controller to use less power, which in turn may cause a memory subsystem that includes the controller to use less power. In addition, reducing the active memory channel count may cause the memory circuit package to use less power.

For example, according to some embodiments, a memory subsystem (e.g., SSD) may include a controller supporting up to eight active memory channels and two QDP nand memory packages (each of which may be dynamically switched (e.g., by setting one or more external pins) between a two-channel mode and a four-channel mode). In the normal/high performance mode, each of the two QDP nand memory packages may be set to operate in a four-channel mode, resulting in all eight memory channels of the controller being connected to the two QDP nand memory packages (thereby making all eight memory channels active). Alternatively, in the low performance mode, each of the two QDP nand memory packages may be set to operate in a two-channel mode, resulting in only four memory channels of the controller being connected to the two QDP nand memory packages (thereby making all four memory channels active). According to various embodiments, whether the two QDP nand memory packages are set to operate in a two-channel mode or a four-channel mode, all nand dies of the two QDP nand memory packages remain accessible to the controller. As described herein, switching between the two-channel mode and the four-channel mode may be dynamically controlled (e.g., by one or more external pins). In the case where less than all eight memory channels are connected/used, the controller may disable portions of the controller (e.g., power islands, such as portions of memory channels, parity engine portions, etc.) associated with unconnected/unused memory channels, thereby reducing power consumption of at least the controller.

As described herein, some examples of systems that include or use a memory circuit package with an adjustable count of active memory channels are disclosed herein.

Fig. 1 shows an example computing environment 100 including a memory subsystem 110 in accordance with some examples of the present disclosure. Memory subsystem 110 may contain media, such as memory components 112A through 112N. The memory components 112A-112N may be volatile memory devices, non-volatile memory devices, or a combination of the like. In some embodiments, memory subsystem 110 is a storage system. One example of a storage system is an SSD. In some embodiments, memory subsystem 110 is a hybrid memory/storage system. In general, the computing environment 100 may contain a host system 120 that uses a memory subsystem 110. For example, the host system 120 may write data to the memory subsystem 110 and read data from the memory subsystem 110.

The host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing devices that include memory and processing devices. The host system 120 may contain or be coupled to the memory subsystem 110 such that the host system 120 may read data from or write data to the memory subsystem 110. The host system 120 may be coupled to the memory subsystem 110 through a physical host interface. As used herein, "coupled to" generally refers to a connection between components that may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, and the like. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, peripheral component interconnect express (PCIe) interfaces, Universal Serial Bus (USB) interfaces, fibre channel interfaces, serial attached scsi (sas) interfaces, and the like. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled with the host system 120 over a PCIe interface, the host system 120 may further utilize an NVM express (NVMe) interface to access the memory components 112A-112N. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120.

The memory components 112A-112N may include any combination of different types of non-volatile memory components and/or volatile memory components. One example of a non-volatile memory component includes a NAND (NAND) type flash memory. Each of memory components 112A-112N may include one or more arrays of memory cells, such as Single Level Cells (SLC) or multi-level cells (MLC) (e.g., TLC or QLC). In some embodiments, a particular memory component 112 may include both SLC and MLC portions of a memory cell. Each of the memory cells may store one or more bits of data (e.g., a block of data) for use by the host system 120. A given set of memory cells of a memory component (e.g., 112A) may be provided by a memory circuit package (e.g., nand memory package) described herein, such as memory circuit package 124 having an adjustable count of active memory channels (active memory channel count) of memory component 112A. Although non-volatile memory components such as NAND flash memory are described, the memory components 112A through 112N may be based on any other type of memory such as volatile memory. In some embodiments, memory components 112A-112N may be, but are not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Phase Change Memory (PCM), Magnetoresistive Random Access Memory (MRAM), NOR (NOR) flash memory, Electrically Erasable Programmable Read Only Memory (EEPROM), and cross-point arrays of non-volatile memory cells. A cross-point array of non-volatile memory cells may perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memories may perform in-place write operations in which non-volatile memory cells may be programmed without pre-erasing the non-volatile memory cells. Further, the memory cells of the memory components 112A-112N may be grouped into memory pages or data blocks, which may refer to the cells of the memory components 112 used to store data.

Memory subsystem controller 115 may communicate with memory components 112A-112N to perform operations such as reading data, writing data, or erasing data at memory components 112A-112N, among other such operations. Memory subsystem controller 115 may include hardware, such as one or more integrated circuits and/or discrete components, cache memory, or a combination thereof. Memory subsystem controller 115 may be a microcontroller, special purpose logic circuitry (e.g., a Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), etc.), or another suitable processor. Memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120. In some embodiments, local memory 119 may include memory registers that store memory pointers, acquired data, and the like. The local memory 119 may also include a Read Only Memory (ROM) for storing microcode. Although the example memory subsystem 110 in fig. 1 has been shown to contain a memory subsystem controller 115, in another embodiment of the present disclosure, the memory subsystem 110 may not contain a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or a processor or controller separate from the memory subsystem 110).

In general, memory subsystem controller 115 may receive commands or operations from host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to memory components 112A through 112N. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and Error Correction Code (ECC) operations, encryption operations, cache operations, and address translation between logical and physical block addresses associated with the memory components 112A-112N. Memory subsystem controller 115 may further include host interface circuitry to communicate with host system 120 over a physical host interface. The host interface circuitry may convert commands received from the host system 120 into command instructions for accessing the memory components 112A-112N and convert responses associated with the memory components 112A-112N into information for the host system 120.

Memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive addresses from memory subsystem controller 115 and decode the addresses to access memory components 112A-112N.

Any of the memory components 112A through 112N may include a media controller (e.g., media controller 113A and media controller 113N) to manage memory units of the memory component 112, communicate with the memory subsystem controller 115, and execute memory requests (e.g., reads or writes) received from the memory subsystem controller 115.

According to various embodiments described herein, the memory component 112A includes a memory circuit package 124 having an adjustable memory channel count. According to some embodiments, memory circuit package 124 includes a plurality of memory dies, a plurality of external memory channel interfaces, and a multiplexer circuit. According to an embodiment, one or more of the memory dies of the memory circuit package 124 include a DDP, QDP, 8DP, or 16DP nand memory die. In addition, a given memory die may provide one or more memory cells (e.g., SLC, TLC, or QLC) of memory component 112A. For some embodiments, the plurality of memory dies of the memory circuit package 124 includes a first group of memory dies and a second group of memory dies. For some embodiments, the plurality of external memory channel interfaces of the memory circuit package 124 includes a first external memory channel interface and a second external memory channel interface. In accordance with some embodiments, a first external memory channel interface is coupled to the first group of memory dies and a multiplexer circuit is coupled to the second group of memory dies and selectively couples the second group of memory dies to one of the first external memory channel interface and the second external memory channel interface based on a control input. Thus, for some embodiments in which the multiplexer circuitry couples the second set of memory dies to the first external memory channel interface, both the first set of memory dies and the second set of memory dies may be accessible through a single memory channel of the memory circuit package 124 via the first external memory channel interface. On the other hand, for some embodiments in which the multiplexer circuitry couples the second group of memory dies to a second external memory channel interface, the first group of memory dies may be accessed through a first memory channel of the memory circuit package 124 via the first external memory channel interface and the second group of memory dies may be accessed through a second memory channel of the memory circuit package 124 via the second external memory channel interface.

Within the memory circuit package 124, a given set of memory dies may include two or more multiple memory dies, where each multiple memory die is coupled to an input/output expander (IOE) of the memory circuit package 124, and the IOE is coupled to a multiplexer circuit of the memory circuit package 124. In this manner, the IOE may couple the two or more multiple memory dies to the multiplexer circuit. For example, the first set of memory dies may include a first plurality of memory dies, a second plurality of memory dies, and IOEs that couple a first external memory channel interface of the memory circuit package 124 to both the first plurality of memory dies and the second plurality of memory dies. Likewise, the second set of memory dies may include a third plurality of memory dies, another plurality of memory dies, and a second IOE coupling a multiplexer circuit to both the third plurality of memory dies and a fourth plurality of memory dies.

The control inputs of the multiplexer circuitry may be provided by a set of external pins (e.g., disposed on an external surface of the memory circuit package 124), which may be driven by a controller (e.g., the media controller 113A or the memory subsystem controller 115). For example, the set of external pins may include a single pin, and the control input may include a single bit that determines whether the second set of memory dies is coupled to the first external memory channel interface or the second external memory channel interface. According to an embodiment, the multiplexer circuitry of the memory circuit package 124 may include a plurality of multiplexers controlled based on a control input.

Memory subsystem controller 115 includes an active memory channel count adjuster 122 that enables memory subsystem controller 115 to control memory circuit packages 124 to adjust their memory channel counts (e.g., adjust between two active memory channels and four active memory channels) as described herein. For example, the active memory channel count adjuster 122 may cause or cause the memory subsystem controller 115 to generate a control input for the multiplexer circuit of the memory circuit package 124, which the memory circuit package 124 may receive over one or more external pins (e.g., a single mode pin). Based on the active memory channel count adjuster 122, the memory subsystem controller 115 may generate control inputs for a first external memory channel interface that causes the multiplexer circuitry to couple the second group of memory dies to the memory circuit package 124, or may generate control inputs to cause the multiplexer circuitry to couple the second group of memory dies to a second external memory channel interface of the memory circuit package 124. The active memory channel number adjuster 122 may cause the memory subsystem controller 115 to generate a control input in response to and based on a request to adjust an active memory channel count of the memory circuit package 124. The request to adjust the active memory channel count of the memory circuit package 124 may be part of a larger request to adjust the active memory channel count of multiple memory circuit packages of the memory component 112A. Additionally, the memory subsystem controller 115 may generate control inputs to the memory circuit package 124 through the media controller 113A of the memory component 112A. The request to adjust the active memory channel count may be associated with (e.g., generated in response to) a mode (e.g., power or performance mode) change of memory subsystem 110, which in turn may be based on a request received by memory subsystem controller 115 (e.g., from host system 120). For example, in response to a request to change to a low power consumption mode (e.g., a low performance mode) of the memory subsystem 110, and the generated control input may cause the multiplexer circuit to couple the second group of memory dies to the first external memory channel interface (thereby deactivating the memory channel associated with the second external memory channel interface). In another example, in response to a request to change to a non-low power consumption mode (e.g., a normal or high performance mode) of the memory subsystem 110, and the generated control input may cause the multiplexer circuit to couple the second group of memory dies to the second external memory channel interface (thereby activating the memory channel associated with the second external memory channel interface).

According to an embodiment, the active memory channel count adjuster 122 may comprise logic (e.g., a set of machine instructions, such as firmware) or one or more components that cause the memory subsystem 110 (e.g., memory subsystem controller 115) to perform the operations described herein with respect to the memory circuit package 124. The active memory channel count adjuster 122 may comprise a tangible unit capable of performing the operations described herein. For alternative embodiments, the media controller 113A includes some or all of the active memory channel count adjuster 122, and the media controller 113A operates to control the memory circuit package 124, as described with respect to the memory subsystem controller 115. Additional details regarding the operation of the memory circuit package 124 are described below.

FIG. 2 is a block diagram of an example memory circuit package 200 with adjustable counting of active memory channels according to some embodiments of the present disclosure. As shown, the memory circuit package 200 includes a plurality of memory dies 210, a multiplexer circuit 220, and a plurality of external memory channel interfaces 230. According to some embodiments, the plurality of memory dies 210 includes a first group of memory dies and a second group of memory dies, and the plurality of external memory channel interfaces 230 includes a first external memory channel interface and a second external memory channel interface, wherein the first external memory channel interface is coupled to the first group of memory dies. Multiplexer circuit 220 is coupled to the second group of memory dies and selectively couples the second group of memory dies to one of the first external memory channel interface and the second external memory channel interface based on a control input (e.g., received by memory circuit package 200 through one or more external pins). A processing device operatively coupled to the memory circuit package 200 may receive a request to adjust an active memory channel count of the memory circuit package 200 and, in response to the request, generate a control input based on the request. For example, as described herein, the control input may be generated by a media controller (e.g., 113A) containing the memory components 112 of the memory circuit package 200 or a controller (e.g., 115) containing the memory subsystem 110 of the memory circuit package 200. Additionally, where the mode change by the system (e.g., memory subsystem 110) includes a change to a low power consumption mode, the generated control input may cause multiplexer circuit 220 to couple the second group of memory dies to the first external memory channel interface (thereby deactivating the memory channel associated with the second external memory channel interface). In the event that the mode change by the system (e.g., memory subsystem 110) includes a change to a non-low power consumption mode (e.g., a normal or high performance mode), the generated control input may cause multiplexer circuit 220 to couple the second group of memory dies to the second external memory channel interface (thereby activating the memory channel associated with the second external memory channel interface).

For some embodiments, the plurality of memory dies 210 includes one or more IOEs such that separate plurality of memory dies are coupled to a given external memory channel interface. For some embodiments, the plurality of memory dies 210 includes three or more separate groups of memory dies, where each group of memory dies 210 includes at least one memory die 210. Further, for some embodiments, the plurality of external memory channel interfaces 230 includes three or more external memory channel interfaces.

Fig. 3 is a diagram of an example memory circuit package 300 with adjustable memory channel count, according to some embodiments of the present disclosure. Specifically, memory circuit package 300 includes a plurality of external memory channel interfaces 310,

multiplexers

320, 325, external pins 340 that provide control inputs to

multiplexers

320, 325, and a plurality of memory dies 330, including memory die 330A, memory die 330B, memory die 330C, and memory die 330D. One or more of the memory dies 330A, 330B, 330C, 330D may include a nand die, and one or more of the nand dies may include a nand cell (e.g., SLC, TLC, or QLC).

The plurality of external memory channel interfaces 310 includes memory channel 0, memory channel 1, memory channel 2, and memory channel 3, each of which may become active or inactive based on a current memory channel count of the memory circuit package 300 as determined by a control input provided through the external pins 340. During operation of the memory circuit package 300, the control inputs may be used to dynamically adjust the active memory channel count (and thus the memory channel configuration) of the memory circuit package 300. According to an embodiment, the external pins 340 may allow a media controller (e.g., 113A) or a memory subsystem controller (e.g., 115) to control the memory channel count of the memory circuit package 300. According to some embodiments, regardless of the currently active memory channel count of the memory circuit package 300, all of the memory dies 330A, 330B, 330C, 330D may be accessed (e.g., for data reads or data writes) through the currently active memory channel.

300A refers to the memory circuit package 300 when all external memory channel interfaces 310 (memory channel 0, memory channel 1, memory channel 3, and memory channel 3) are active, while 300B refers to the memory circuit package 300 when only two of the external memory channel interfaces 310, memory channel 0 and memory channel 1, are active.

As shown with respect to 300A, to operate in the four-channel mode, a control input received by the memory circuit package 300 over the external pin 340 causes the multiplexer 320 to couple the memory die 330C to the external memory channel interface associated with memory channel 2 and causes the multiplexer 325 to couple the memory die 330D to the external memory channel interface associated with memory channel 3. Memory die 330A remains coupled to the external memory channel interface associated with memory channel 0 and memory die 330B remains coupled to the external memory channel interface associated with memory channel 1.

As shown with respect to 300B, to operate in the two-channel mode, control inputs received by memory circuit package 300 over external pins 340 cause multiplexer 320 to couple memory die 330C to the external memory channel interface associated with memory channel 0 (shared with memory die 330A), and cause multiplexer 325 to couple memory die 330D to the external memory channel interface associated with memory channel 1 (shared with memory die 330B). Memory die 330A remains coupled to the external memory channel interface associated with memory channel 0 and memory die 330B remains coupled to the external memory channel interface associated with memory channel 1.

Fig. 4 is a diagram of an example memory circuit package 400 with adjustable memory channel count according to some embodiments of the present disclosure. Specifically, the memory circuit package 400 includes a plurality of external memory channel interfaces 410, a multiplexer 420, an external pin 440 providing a control input to the multiplexer 420, a plurality of input/output expanders (IOEs) 450, 455, and a plurality of memory dies 430, including a sub-plurality of memory dies 430A, a sub-plurality of memory dies 430B, a sub-plurality of memory dies 430C, and a sub-plurality of memory dies 430D. As illustrated, each of the sub-pluralities 430A, 430B, 430C, 430D includes four dies (e.g., a quad nand die), wherein each of the sub-pluralities 430A, 430B is coupled to an IOE 450 and each of the sub-pluralities 430C, 430D is coupled to an IOE 455.

Similar to the memory circuit package 300 of FIG. 3, the plurality of external memory channel interfaces 410 includes memory channel 0 and memory channel 1, each of which may become active or inactive based on a current memory channel count of the memory circuit package 400 as determined by a control input provided through the external pins 440. During operation of the memory circuit package 400, the control inputs may be used to dynamically adjust the active memory channel count (and thus the memory channel configuration) of the memory circuit package 400. According to an embodiment, the external pins 440 may allow a media controller (e.g., 113A) or a memory subsystem controller (e.g., 115) to control the memory channel count of the memory circuit package 400. According to some embodiments, regardless of the currently active memory channel count of the memory circuit package 400, all of the sub-plurality of memory dies 430A, 430B, 430C, 430D are accessible (e.g., for data read or data write) through the currently active memory channel.

As shown with respect to 400A, to operate in the two-channel mode, a control input received by the memory circuit package 400 through the external pin 440 causes the multiplexer 420 to couple the IOE 455 (which is coupled to the sub-plurality of memory dies 430C and the sub-plurality of memory dies 430D) to the external memory channel interface associated with memory channel 1. The sub-plurality of memory dies 430A and the sub-plurality of memory dies 430B remain coupled to the external memory channel interface associated with memory channel 0 through the IOE 450.

As shown with respect to 400B, to operate in a channel mode, a control input received by the memory circuit package 400 through the external pin 440 causes the multiplexer 420 to couple the IOE 455 (which is coupled to the sub-plurality of memory dies 430C and the sub-plurality of memory dies 430D) to the external memory channel interface associated with memory channel 0. The sub-plurality of memory dies 430A and the sub-plurality of memory dies 430B remain coupled to the external memory channel interface associated with memory channel 0 through the IOE 450.

Fig. 5 is a flow diagram of an example method 500 for adjusting an active memory channel count of a memory circuit package, according to some embodiments of the present disclosure. Method 500 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, method 500 is performed by host system 120 of fig. 1. In these embodiments, the method 500 may be performed, at least in part, by the active memory channel count adjuster 122. Alternatively, method 500 is performed by memory subsystem 110 of fig. 1 (e.g., a processor of memory subsystem controller 115). Although the processes are shown in a particular sequence or order, the order of the processes may be modified unless otherwise indicated. Thus, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

Referring now to method 500 of fig. 5, at operation 505, a memory subsystem (e.g., memory subsystem controller 115) or a processing device of a memory component (e.g., memory component 112A) receives a request to adjust an active memory channel count of the memory component (e.g., 112A). At operation 510, in response to the request, the processing device generates a control input for the memory circuit package (e.g., 124) based on the request.

As described herein, a memory circuit package may include: a plurality of memory dies (e.g., 430) including a first group of memory dies and a second group of memory dies; a plurality of external memory channel interfaces (e.g., 410) including a first external memory channel interface and a second external memory channel interface, wherein the first external memory channel interface is coupled to the first set of memory dies; and a multiplexer circuit (e.g., 220) coupled to the second set of memory dies and selectively coupling the second set of memory dies to one of the first external memory channel interface and the second external memory channel interface based on a control input. For some embodiments in which the request is to decrease an active memory channel count, generating the control input based on the request includes generating the control input to cause the multiplexer circuitry to couple the second set of memory dies to the first external memory channel interface. In doing so, the memory circuit package deactivates a memory channel associated with the second external memory channel interface of the memory circuit package, thereby reducing a memory channel count of the memory circuit package. Additionally, for some embodiments in which the request is to increase an active memory channel count, generating the control input based on the request includes generating the control input to cause the multiplexer circuit to couple the second group of memory dies to a second external memory channel interface. In doing so, the memory circuit package activates a memory channel associated with the second external memory channel interface of the memory circuit package, thereby increasing the memory channel count of the memory circuit package. Finally, at operation 515, the processing device provides (e.g., transmits) the control input (generated at operation 510) to the memory circuit package, responding as described herein.

FIG. 6 provides an interaction diagram illustrating interactions between components of the computing environment 100 in the context of performing an example embodiment of a method for adjusting an active memory channel count of a memory circuit package. The operations of the methods may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method is performed by a memory subsystem controller (e.g., 115), a media controller (e.g., 113A), or a combination of both. Although the operations are shown in a particular sequence or order, the order of the processes may be modified unless otherwise indicated. Thus, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment.

In the context of the example illustrated in fig. 6, the memory subsystem controller may include the memory subsystem controller 115, the media controller may include the media controller 113A, and the one or more memory circuit packages may include at least the memory circuit package 124 of the memory component 112A, and may further include other memory circuit packages of the memory component 112A.

As shown in fig. 6, at operation 605, the memory subsystem controller 115 receives a request to change a power or performance mode of the memory subsystem 110 (e.g., from the host system 120). In response, at operation 610, the memory subsystem controller 115 generates a request to adjust a count of active memory channel counts for one or more memory components 112A-112N of the memory subsystem 110. As described herein, a request generated by memory subsystem 110 to adjust the active memory channel count may include a request to decrease the active memory channel count in response to a request to change memory subsystem 110 to a low power/performance mode. On the other hand, in response to a request to change memory subsystem 110 to a normal or high power/performance mode, the request generated by memory subsystem 110 to adjust the active memory channel count may include a request to increase the active memory channel count.

At operation 620, the media controller 113A of the memory component 112A receives a request from the memory subsystem controller 115 to adjust the active memory channel count. In response, at operation 625, the media controller 113A generates control inputs for at least the memory circuit package 124 (if not other similar memory circuit packages for the memory component 112A) based on the request to adjust the active memory channel count. As described herein, the request to adjust the active memory channel count may include a request to increase or decrease the active memory channel count of the memory circuit package 124.

At operation 630, the memory circuit package 124 receives a control input generated by the media controller 113A. Based on the generated control input, the memory circuit package 124 adjusts the count of its active memory channels. Specifically, at operation 635, based on the generated control input, the multiplexer circuit of the memory circuit package 124 couples the (second) group of memory dies of the memory circuit package 124 to either the first external memory channel interface or the second external memory channel interface. For some embodiments, a first group of memory dies of the memory circuit package 124 is coupled to a first external memory channel interface, and a second group of memory dies of the memory circuit package 124 is coupled to either the first external memory channel interface or a second external memory channel interface based on the generated control inputs. Thus, at operation 635, the second group of memory dies is coupled to the first external memory channel interface to decrease the count of active memory channels of the memory circuit package 124 based on the generated control input and the second group of memory dies is coupled to the second external memory channel interface to increase the count of active memory channels of the memory circuit package 124 based on the generated control input.

Fig. 7 illustrates an example machine in the form of a computer system 700 within which a set of instructions may be executed to cause the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 700 may correspond to a host system (e.g., the host system 120 of fig. 1) that includes, is coupled to, or utilizes a memory subsystem (e.g., the memory subsystem 110 of fig. 1) or may be used to perform the operations of a controller (e.g., to execute an operating system to perform operations corresponding to the active memory channel count adjuster 122 of fig. 1). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a Local Area Network (LAN), an intranet, an extranet, and/or the internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The machine may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, network switch, network bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system 700 includes a processing device 702, a main memory 704 (e.g., Read Only Memory (ROM), flash memory, Dynamic Random Access Memory (DRAM) (such as synchronous DRAM (sdram) or Rambus DRAM (rdram), etc.), a static memory 706 (e.g., flash memory, Static Random Access Memory (SRAM), etc.), and a data storage device 718 that communicate with each other over a bus 730.

The processing device 702 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More specifically, the processing device 702 may be a Complex Instruction Set Computing (CISC) microprocessor, Reduced Instruction Set Computing (RISC) microprocessor, Very Long Instruction Word (VLIW) microprocessor, processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device 702 may also be one or more special-purpose processing devices such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), network processor, or the like. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 may further include a network interface device 708 that communicates over a network 720.

The data storage 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 726 or software embodying any one or more of the methodologies or functions described herein. The instructions 726 may also reside, completely or at least partially, within the main memory 704 and/or within the processing device 702 during execution thereof by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage media 724, data storage 718, and/or main memory 704 may correspond to memory subsystem 110 of fig. 1.

In one embodiment, the instructions 726 include instructions for implementing functions corresponding to adjusting an active memory channel count of a memory circuit package as described herein (e.g., the active memory channel count adjuster 122 of FIG. 1). While the machine-readable storage medium 724 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks; read Only Memory (ROM); random Access Memory (RAM); erasable programmable read-only memory (EPROM); an EEPROM; magnetic or optical cards; or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as set forth in the description above. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

The present disclosure may be provided in the form of a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine-readable (e.g., computer-readable) storage medium such as Read Only Memory (ROM), Random Access Memory (RAM), magnetic disk storage media, optical storage media, flash memory components, and so forth.

In the foregoing specification, embodiments of the disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications can be made thereto without departing from the embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Examples of the invention

Example 1 is a system, comprising: a memory component comprising a memory circuit package, the memory circuit package comprising: a plurality of memory dies including a first set of memory dies and a second set of memory dies; a plurality of external memory channel interfaces including a first external memory channel interface and a second external memory channel interface, the first external memory channel interface coupled to the first set of memory dies; and multiplexer circuitry coupled to the second set of memory dies and selectively coupling the second set of memory dies to one of the first external memory channel interface and the second external memory channel interface based on a control input; and a processing device operatively coupled to the memory component, the processing device configured to perform operations comprising: receiving a request to adjust an active memory channel count of the memory component; and in response to the request, generating the control input based on the request.

In example 2, the subject matter of example 1 optionally includes wherein the plurality of memory dies further includes a third set of memory dies and a fourth set of memory dies, wherein the plurality of external memory channel interfaces further includes a third external memory channel interface and a fourth external memory channel interface, wherein the third external memory channel interface is coupled to the third set of memory dies, and wherein the multiplexer circuit is further coupled to the fourth set of memory dies and selectively couples the fourth set of memory dies to one of the third external memory channel interface and the fourth external memory channel interface based on the control input.

In example 3, the subject matter of example 1 or example 2 optionally includes wherein the multiplexer circuit comprises a plurality of multiplexers controlled based on the control input.

In example 4, the subject matter of any of examples 1-3 optionally includes wherein the generating the control input based on the request comprises generating the control input to cause the multiplexer circuitry to couple the second set of memory dies to the first external memory channel interface.

In example 5, the subject matter of any of examples 1-4 optionally includes wherein the generating the control input based on the request comprises generating the control input to cause the multiplexer circuitry to couple the second set of memory dies to the second external memory channel interface.

In example 6, the subject matter of any of examples 1-5 optionally includes wherein the first set of memory dies comprises: a first plurality of memory dies; a second plurality of memory dies; and an input/output expander coupling the first external memory channel interface to both the first plurality of memory dies and the second plurality of memory dies.

In example 7, the subject matter of any of examples 1-6 optionally includes wherein the second set of memory dies comprises: a third plurality of memory dies; a fourth plurality of memory dies; and a second input/output expander coupling the multiplexer circuit to both the third plurality of memory dies and the fourth plurality of memory dies.

In example 8, the subject matter of any of examples 1-7 optionally includes wherein the request is associated with a mode change by the system.

In example 9, the subject matter of any of examples 1-8 optionally includes wherein the mode change comprises a change to a low power consumption mode by the system, and generating the control input based on the request comprises generating the control input to cause the multiplexer circuitry to couple the second set of memory dies to the first external memory channel interface.

In example 10, the subject matter of any of examples 1-9 optionally includes wherein the mode change comprises a change to a non-low power consumption mode by the system, and wherein generating the control inputs based on the request comprises generating the control inputs to cause the multiplexer circuitry to couple the second set of memory dies to the second external memory channel interface.

Example 11 is a method, comprising: a plurality of memory dies including a first set of memory dies and a second set of memory dies; a plurality of external memory channel interfaces including a first external memory channel interface and a second external memory channel interface, the first external memory channel interface coupled to the first set of memory dies; and a multiplexer circuit coupled to the second set of memory dies and selectively coupling the second set of memory dies to one of the first external memory channel interface and the second external memory channel interface based on a control input.

In example 12, the subject matter of example 11 optionally includes wherein the plurality of memory dies further includes a third set of memory dies and a fourth set of memory dies, wherein the plurality of external memory channel interfaces further includes a third external memory channel interface and a fourth external memory channel interface, wherein the third external memory channel interface is coupled to the third set of memory dies, and wherein the multiplexer circuit is further coupled to the fourth set of memory dies and selectively couples the fourth set of memory dies to one of the third external memory channel interface and the fourth external memory channel interface based on the control input.

In example 13, the subject matter of example 11 or example 12 optionally includes wherein the multiplexer circuit comprises a plurality of multiplexers controlled based on the control input.

In example 14, the subject matter of any of examples 11-13 optionally includes wherein the first set of memory dies comprises: a first plurality of memory dies; a second plurality of memory dies; and an input/output expander coupling the first external memory channel interface to both the first plurality of memory dies and the second plurality of memory dies.

In example 15, the subject matter of any of examples 11-14 optionally includes wherein the second set of memory dies comprises: a third plurality of memory dies; a fourth plurality of memory dies; and a second input/output expander coupling the multiplexer circuit to both the third plurality of memory dies and the fourth plurality of memory dies.

Example 16 is a method, comprising: receiving a request to adjust an active memory channel count of the memory component; generating, in response to the request, a control input based on the request; and providing the generated control input to a memory circuit package, the memory circuit package comprising: a plurality of memory dies including a first set of memory dies and a second set of memory dies; a plurality of external memory channel interfaces including a first external memory channel interface and a second external memory channel interface, the first external memory channel interface coupled to the first set of memory dies; and a multiplexer circuit coupled to the second set of memory dies and selectively coupling the second set of memory dies to one of the first external memory channel interface and the second external memory channel interface based on the control input.

In example 17, the subject matter of example 16 optionally includes wherein generating the control inputs based on the request comprises generating the control inputs to cause the multiplexer circuitry to couple the second set of memory dies to the first external memory channel interface.

In example 18, the subject matter of example 16 or example 17 optionally includes generating the control input based on the request includes generating the control input to cause the multiplexer circuitry to couple the second set of memory dies to the second external memory channel interface.

In example 19, the subject matter of any of examples 16-18 optionally includes wherein the request is associated with a mode change by the system, wherein the mode change comprises a change to a low power consumption mode by the system, and generating the control input based on the request comprises generating the control input to cause the multiplexer circuitry to couple the second set of memory dies to the first external memory channel interface.

In example 20, the subject matter of any of examples 16-19 optionally includes wherein the request is associated with a mode change by the system, wherein the mode change comprises a change to a non-low power mode by the system, and wherein generating the control inputs based on the request comprises generating the control inputs to cause the multiplexer circuitry to couple the second set of memory dies to the second external memory channel interface.

Claims

1. A system, comprising:

a memory component comprising a memory circuit package, the memory circuit package comprising:

a plurality of memory dies including a first set of memory dies and a second set of memory dies;

a plurality of external memory channel interfaces including a first external memory channel interface and a second external memory channel interface, the first external memory channel interface coupled to the first set of memory dies; and

a multiplexer circuit coupled to the second set of memory dies and selectively coupling the second set of memory dies to one of the first external memory channel interface and the second external memory channel interface based on a control input; and

a processing device operatively coupled to the memory component, the processing device configured to perform operations comprising:

receiving a request to adjust an active memory channel count of the memory component; and

in response to the request, generating the control input based on the request.

2. The system of claim 1, wherein the plurality of memory dies further comprises a third set of memory dies and a fourth set of memory dies, wherein the plurality of external memory channel interfaces further comprises a third external memory channel interface and a fourth external memory channel interface, wherein the third external memory channel interface is coupled to the third set of memory dies, and wherein the multiplexer circuit is further coupled to the fourth set of memory dies and selectively couples the fourth set of memory dies to one of the third external memory channel interface and the fourth external memory channel interface based on the control input.

3. The system of claim 2, wherein the multiplexer circuit comprises a plurality of multiplexers controlled based on the control input.

4. The system of claim 1, wherein the generating the control input based on the request comprises generating the control input to cause the multiplexer circuitry to couple the second set of memory dies to the first external memory channel interface.

5. The system of claim 1, wherein the generating the control inputs based on the request comprises generating the control inputs to cause the multiplexer circuitry to couple the second set of memory dies to the second external memory channel interface.

6. The system of claim 1, wherein the first set of memory dies comprises:

a first plurality of memory dies;

a second plurality of memory dies; and

an input/output expander coupling the first external memory channel interface to both the first plurality of memory dies and the second plurality of memory dies.

7. The system of claim 6, wherein the second set of memory dies comprises:

a third plurality of memory dies;

a fourth plurality of memory dies; and

a second input/output expander coupling the multiplexer circuit to both the third plurality of memory dies and the fourth plurality of memory dies.

8. The system of claim 1, wherein the request is associated with a mode change by the system.

9. The system of claim 8, wherein the mode change comprises a change to a low power consumption mode by the system, and wherein generating the control input based on the request comprises generating the control input to cause the multiplexer circuit to couple the second set of memory dies to the first external memory channel interface.

10. The system of claim 8, wherein the mode change comprises a change to a non-low power consumption mode by the system, and wherein the generating the control inputs based on the request comprises generating the control inputs to cause the multiplexer circuitry to couple the second set of memory dies to the second external memory channel interface.

11. A memory circuit package, comprising:

a multiplexer circuit coupled to the second set of memory dies and selectively coupling the second set of memory dies to one of the first external memory channel interface and the second external memory channel interface based on a control input.

12. The memory circuit package of claim 11, wherein the plurality of memory dies further comprises a third set of memory dies and a fourth set of memory dies, wherein the plurality of external memory channel interfaces further comprises a third external memory channel interface and a fourth external memory channel interface, wherein the third external memory channel interface is coupled to the third set of memory dies, and wherein the multiplexer circuit is further coupled to the fourth set of memory dies and selectively couples the fourth set of memory dies to one of the third external memory channel interface and the fourth external memory channel interface based on the control input.

13. The memory circuit package of claim 11, wherein the first set of memory dies comprises:

a first plurality of memory dies;

a second plurality of memory dies; and

14. The memory circuit package of claim 13, wherein the second set of memory dies comprises:

a third plurality of memory dies;

a fourth plurality of memory dies; and

15. A method, comprising:

receiving a request to adjust an active memory channel count of the memory component;

generating, in response to the request, a control input based on the request; and

providing the generated control input to a memory circuit package, the memory circuit package comprising:

a multiplexer circuit coupled to the second set of memory dies and selectively coupling the second set of memory dies to one of the first external memory channel interface and the second external memory channel interface based on the control input.