CN113271064B - Three-dimensional integrated low-phase noise voltage-controlled oscillator - Google Patents

Three-dimensional integrated low-phase noise voltage-controlled oscillator Download PDF

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CN113271064B
CN113271064B CN202110443900.3A CN202110443900A CN113271064B CN 113271064 B CN113271064 B CN 113271064B CN 202110443900 A CN202110443900 A CN 202110443900A CN 113271064 B CN113271064 B CN 113271064B
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tsv
wheatstone
output end
copper column
silicon substrate
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CN113271064A (en
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王凤娟
陈佳俊
文炳成
余宁梅
杨媛
朱樟明
尹湘坤
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Xian University of Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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Abstract

The invention discloses a three-dimensional integrated low-phase noise voltage-controlled oscillator, which comprises a power supply, wherein the power supply is connected with a source electrode and a substrate of M1 and M2, a grid electrode of M1 is connected with an output end of Lv1 and an input end of C2, a grid electrode of M2 is connected with an output end of Lv2 and an input end of C1, vbias is connected with input ends of Lv1 and Lv2, a drain electrode of M1 is connected with input ends of L1 and R1, an output end of L1 and Cv1, an input end of Lv3 and Vout1, a drain electrode of M2 is connected with an input end of L2, an output end of L2 is connected with an input end of R2, an output end of R2 and Cv2, an input end of Lv4, vout2, vctr1 and input ends of Cv1 and Cv2, and a ground end is connected with output ends of Lv3 and Lv 4. The invention has the advantages of small chip area, low phase noise, and the like.

Description

Three-dimensional integrated low-phase noise voltage-controlled oscillator
Technical Field
The invention belongs to the technical field of three-dimensional integrated circuits, and relates to a three-dimensional integrated low-phase noise voltage-controlled oscillator.
Background
Voltage Controlled Oscillators (VCO) are important in radio frequency circuits, particularly in phase locked loop circuits, clock recovery circuits, frequency synthesizer circuits, etc., whose oscillation frequency can be adjusted by controlling the voltage. The phase noise directly affects the stability of the output frequency, and the inductance and capacitance frequency modulation oscillators are the only reliable realization methods, but the inductance and capacitance occupy larger chip area.
With the development of microelectronic technology, the size of microelectronic devices continues to decrease according to moore's law, and the integration level of integrated circuits is also increasing. The current voltage-controlled oscillator is difficult to meet the requirements of high integration level and excellent performance in the future.
Disclosure of Invention
The invention aims to provide a three-dimensional integrated low-phase noise voltage-controlled oscillator, which solves the problem of high phase noise in a voltage-controlled oscillator circuit in the prior art.
The three-dimensional integrated low-phase noise voltage-controlled oscillator comprises a power supply VDD, wherein the power supply VDD is connected with a source and a substrate of a TSV vertical switch M1 and a source and a substrate of a TSV vertical switch M2, a grid electrode of the TSV vertical switch M1 is connected with an output end of a Wheatstone inductive bridge Lv1 and an input end of a TSV capacitor tube C2, a grid electrode of the TSV vertical switch M2 is connected with an output end of the Wheatstone inductive bridge Lv2 and an input end of the TSV capacitor tube C1, a reference voltage Vbias is connected with an input end of the Wheatstone inductive bridge Lv1 and an input end of the Wheatstone inductive bridge Lv2, a drain electrode of the TSV vertical switch M1 is connected with an input end of the TSV inductive bridge L1, an output end of the Wheatstone inductive bridge Lv2 is connected with an output end of the Wheatstone capacitive bridge Cv2, an output end of the Wheatstone capacitive bridge Cv2 is connected with an output end of the Wheatstone capacitive bridge Cv1, an output end of the Wheatstone capacitive bridge Cv2 is connected with an output end of the Wheatstone capacitive bridge Cv2, and an output end of the Wheatstone capacitive bridge Cv2 is connected with an output end of the Wheatstone capacitive bridge Cv 2.
The invention is also characterized in that:
the TSV vertical switch M1 comprises an N-type silicon substrate (4), wherein a vertical TSV copper column (1) is arranged in the N-type silicon substrate (4), a dielectric layer (2) is arranged on the outer side of the TSV copper column (1), p+ doping regions (7) are arranged on the outer sides of the dielectric layers (2) at the upper end and the lower end of the N-type silicon substrate (4), a rewiring layer (3) is arranged on the outer side face of the p+ doping region (7), silicon dioxide layers (6) are arranged on the upper end face and the lower end face of the TSV vertical switch M1 outside the rewiring layer (3), a source electrode S and a drain electrode D serving as MOS are respectively led out from the upper and lower rewiring layers (3), and a grid electrode G serving as MOS is led out from the top end of the TSV copper column (1).
The TSV inductors L1, L2, L3, L4, L5 and L6 are all composed of 2N TSV inductor copper columns.
The TSV capacitor tube C1 comprises a P-type silicon substrate (5), a half-through-hole TSV copper column (1) is arranged on the P-type silicon substrate (5), a dielectric layer (2) is arranged on the outer side of the half-through-hole TSV copper column (1), a metal layer (8) is arranged on the outer side of the dielectric layer (2), a rewiring layer (3) is arranged on the outer side face of the metal layer (8) and the P-type silicon substrate (5), the metal layer (8) is led out through the rewiring layer (3) on the surface of the P-type silicon substrate (5) to serve as an output end of the TSV capacitor tube C1, silicon dioxide layers (6) are arranged on the upper end face and the lower end face of the TSV capacitor tube C1 outside the rewiring layer (3), and the top end of the half-through-hole TSV copper column (1) is led out to serve as an input end of the TSV capacitor tube C1.
The TSV varactor Cv1 comprises a P-type silicon substrate (5), wherein the P-type silicon substrate (5) is provided with a vertical TSV copper column (1), a grid electrode G serving as an MOS is led out from the top end of the TSV copper column (1), a dielectric layer (2) is arranged on the outer side of the TSV copper column (1), p+ doped regions (7) are arranged on the outer sides of the dielectric layers (2) at the upper end and the lower end of the P-type silicon substrate (5), a rewiring layer (3) is arranged on the outer side of the p+ doped regions (7), a source electrode S and a drain electrode D serving as the MOS are led out from the upper and the lower rewiring layers (3) respectively, the source electrode S and the drain electrode D are connected to serve as output ends of the TSV varactor Cv1, silicon dioxide layers (6) are arranged on the upper end face and the lower end faces of the TSV varactor C1 outside the rewiring layer (3), and the grid electrode G of the MOS serves as the input end of the TSV varactor.
The wheatstone inductive bridges Lv1, lv2, lv3, lv4 are each composed of 4n+2 TSV inductive copper pillars and 1 TSV vertical switch.
The beneficial effects of the invention are as follows: according to the invention, an Lc bias circuit is added into a circuit to serve as an impedance transformation network, and the phase noise of a voltage-controlled oscillator is improved by conveying higher frequency to the grid electrode of an MOS cross-coupling pair; and adding a resistor and an inductor at the drain electrode of the MOS to strengthen the-Gm; the inductors (L1 and L2), the Wheatstone inductive bridge (Lv 1, lv2, lv3 and Lv 4), the MOS tubes (M1 and M2), the capacitor tubes (C1 and C2) and the varistors (Cv 1 and Cv 2) all adopt TSV three-dimensional structures, so that the area and cost of a chip are reduced, the integration level is improved, the TSV inductor has a better quality factor at a lower frequency (such as below 20 GHz), the TSV varistors have higher performance in the same area compared with the planar varistors, the performance of the TSV varistors can be adjusted by changing the height and diameter of the TSVs, and the depth and width of a source drain region are changed to adjust the tuning range of the TSV varistors; the wheatstone inductive bridge has a larger adjustable range, a smaller area and a higher quality factor,
compared with the traditional voltage-controlled oscillator, the invention has the advantages of small chip area, low phase noise, low power consumption under low voltage, larger amplitude of an output curve and the like.
Drawings
FIG. 1 is a circuit diagram of a three-dimensional integrated low phase noise voltage controlled oscillator of the present invention;
FIG. 2 is a schematic diagram of a TSV vertical switch in a three-dimensional integrated low phase noise voltage controlled oscillator according to the present invention;
FIG. 3 is a top view of a TSV inductor in a three-dimensional integrated low phase noise voltage controlled oscillator of the present invention;
FIG. 4 is a schematic diagram of the structure of the TSV capacitor in the three-dimensional integrated low-phase noise voltage controlled oscillator according to the present invention;
fig. 5 is a schematic diagram of the structure of a TSV varactor in a three-dimensional integrated low-phase noise voltage controlled oscillator according to the present invention;
fig. 6 is a schematic diagram of the structure of a wheatstone inductive bridge in a three-dimensional integrated low phase noise voltage controlled oscillator of the present invention.
In the figure, a 1-TSV copper column, a 2-dielectric layer, a 3-rewiring layer, a 4-N type silicon substrate, a 5.P type silicon substrate, a 6-silicon dioxide layer, a 7.p + doped region and an 8-metal layer.
Detailed Description
The invention will be described in detail below with reference to the drawings and the detailed description.
The invention relates to a three-dimensional integrated low-phase noise voltage-controlled oscillator, which is shown in fig. 1, and comprises two TSV vertical switches M1 and M2 of P-type MOS, two inductors L1 and L2, four Wheatstone inductive bridges Lv1, lv2, lv3 and Lv4, two TSV capacitance tubes C1 and C2, two TSV varactors Cv1 and Cv2, two resistors R1 and R2, a power supply VDD, a ground end GND, a varactor control power supply Vctr1, a reference power supply Vbias and circuit output ports Vout1 and Vout2; the power supply VDD is connected with the source S1 and the substrate B1 of the TSV vertical switch M1 and the source S2 and the substrate B2 of the TSV vertical switch M2, the grid of the TSV vertical switch M1 is connected with the output end OUT1 of the Wheatstone inductive bridge Lv1 and the input end Cin2 of the TSV capacitive tube C2, the grid of the TSV vertical switch M2 is connected with the output end OUT2 of the Wheatstone inductive bridge Lv2 and the input end Cin1 of the TSV capacitive tube C1, the reference voltage Vbias is connected with the input end IN1 of the Wheatstone inductive bridge Lv1 and the input end IN2 of the Wheatstone inductive bridge Lv2, the drain of the TSV vertical switch M1 is connected with the input end Lin1 of the TSV inductive bridge L1, the output end Lout1 of the TSV inductive bridge L1 is connected with the input end Rin1 of the resistor R1, the output end Rout1 of the resistor R1 is connected with the output end Cout1 of the TSV capacitor C1, the output end Cvout1 of the TSV varactor Cv1, the input end IN3 of the Wheatstone inductive bridge Lv3 and the circuit output port Vout1, the drain electrode of the TSV vertical switch M2 is connected with the input end Lin2 of the TSV inductor L2, the output end Lout2 of the TSV inductor L2 is connected with the input end Rin2 of the resistor R2, the output end Rout2 of the resistor R2 is connected with the output end Cout2 of the TSV capacitor C2, the output end Cvout2 of the TSV varactor Cv2, the input end TSV 4 of the Wheatstone inductive bridge Lv4 and the circuit output signal Vout2, the varactor control voltage Vctr1 is connected with the input end Cvin1 of the varactor Cv2, the input end Cvin2 of the TSV varactor Cv 3 and the output end OUT4 of the Wheatstone inductive bridge Lv 4;
as shown in fig. 2, the TSV vertical switch M1 includes an N-type silicon substrate 4, a vertical TSV copper pillar 1 is disposed in the N-type silicon substrate 4, a dielectric layer 2 is disposed outside the TSV copper pillar 1, p+ doped regions 7,p + doped regions 7 are disposed outside the dielectric layer 2 at the upper and lower ends of the N-type silicon substrate 4, a redistribution layer 3 is disposed on the outer side surface of the p+ doped regions 7,p + doped regions 7, silicon dioxide layers 6 are disposed on the upper and lower end surfaces of the TSV vertical switch M1 except for the redistribution layer 3, the upper and lower redistribution layers 3 respectively lead out a source S and a drain D as MOS, and the top end of the TSV copper pillar 1 leads out a gate G as MOS; the TSV vertical switch M2 has the same structure as the TSV vertical switch M1; the TSV vertical switches (M3, M4, M5, M6) in the wheatstone inductive bridge are identical in structure to the TSV vertical switch M1.
As shown in fig. 3, the TSV inductors L1, L2, L3, L4, L5, and L6 are each composed of 2N TSV inductor copper pillars; the size of the TSV inductor can be controlled by changing N, where n=3, that is, 6 TSV inductor copper columns are taken as an example, the TSV inductor input end Lin is connected with the a1 end of the TSV inductor copper column I1, the b1 end of the TSV inductor copper column I1 is connected with the b2 end of the TSV inductor copper column I2, the a2 end of the TSV inductor copper column I2 is connected with the a3 end of the TSV inductor copper column I3, the b3 end of the TSV inductor copper column I3 is connected with the b4 end of the TSV inductor copper column I4, the a4 end of the TSV inductor copper column I4 is connected with the a5 end of the TSV inductor copper column I5, the b5 end of the TSV inductor copper column I5 is connected with the b6 end of the TSV inductor copper column I6, and the a6 end of the TSV inductor copper column I6 is connected with the TSV inductor output end Lout;
as shown in fig. 4, the TSV capacitor C1 includes a P-type silicon substrate 5, a semi-through-hole TSV copper pillar 1 is disposed on the P-type silicon substrate 5, a dielectric layer 2 is disposed outside the semi-through-hole TSV copper pillar 1, a metal layer 8 is disposed outside the dielectric layer 2, a rewiring layer 3 is disposed on the outer side surfaces of the metal layer 8 and the P-type silicon substrate 5, the metal layer 8 is led out through the rewiring layer 3 on the surface of the P-type silicon substrate 5 to serve as an output end Cout1 of the TSV capacitor C1, silicon dioxide layers 6 are disposed on the upper and lower end surfaces of the TSV capacitor C1 outside the rewiring layer 3, and the top end of the semi-through-hole TSV copper pillar 1 is led out to serve as an input end of the TSV capacitor C1; c2 and C1 have the same structure;
as shown in fig. 5, the TSV varactor Cv1 includes a P-type silicon substrate 5, the P-type silicon substrate 5 is provided with a vertical TSV copper pillar 1, a gate G serving as a MOS is led out from the top end of the TSV copper pillar 1, a dielectric layer 2 is provided outside the TSV copper pillar 1, p+ doped regions 7,p + doped regions 7 are provided outside the dielectric layer 2 at the upper and lower ends of the P-type silicon substrate 5, a redistribution layer 3 is provided on the outer side surfaces of the p+ doped regions 7, the upper and lower redistribution layers 3 respectively led out as a source S and a drain D of the MOS, the source S and the drain D are connected to serve as an output end of the TSV varactor Cv1, silicon dioxide layers 6 are provided on the upper and lower end surfaces of the TSV varactor C1 except the redistribution layer 3, and the gate G of the MOS serves as an input end of the TSV varactor;
as shown in fig. 6, the wheatstone inductive bridges Lv1, lv2, lv3, lv4 are each composed of (4n+2) TSV inductive copper pillars and 1 TSV vertical switch; the size of the TSV inductor can be controlled by changing N, here taking n=4, i.e. 18 TSV inductor copper pillars as an example. The input end IN of the Wheatstone inductance bridge is connected with the a17 end of the TSV inductance copper column D17 and the a1 end of the TSV inductance copper column D1, the b1 end of the TSV inductance copper column D1 is connected with the b2 end of the TSV inductance copper column D2, the a2 end of the TSV inductance copper column D2 is connected with the a3 end of the TSV inductance copper column D3, the b3 end of the TSV inductance copper column D3 is connected with the b4 end of the TSV inductance copper column D4, the a4 end of the TSV inductance copper column D4 is connected with the a5 end of the TSV inductance copper column D5 and the source S of the TSV vertical switch M3, the b5 end of the TSV inductance copper column D5 is connected with the b6 end of the TSV inductance copper column D6, the a6 end of the TSV inductance copper column D7 is connected with the a7 end of the TSV inductance copper column D8, the a8 end of the TSV inductance copper column D8 is connected with the a18 end of the TSV inductance copper column D18, the b18 end of the TSV inductance copper column D18 is connected with the b9 end of the TSV inductance copper column D9 and the output end OUT of the Wheatstone inductance bridge, the a9 end of the TSV inductance copper column D9 is connected with the a10 end of the TSV inductance copper column D10, the b10 end of the TSV inductance copper column D10 is connected with the b11 end of the TSV inductance copper column D11, the a11 end of the TSV inductance copper column D11 is connected with the a12 end of the TSV inductance copper column D12, the b12 end of the TSV inductance copper column D12 is connected with the b13 end of the TSV inductance copper column D13 and the drain electrode D of the TSV vertical switch M3, the a13 end of the TSV inductance copper column D13 is connected with the a14 end of the TSV inductance copper column D14, the b14 end of the TSV inductance copper column D15 is connected with the a16 end of the TSV inductance copper column D15, and the b16 end of the TSV inductance copper column D16 is connected with the b17 end of the TSV inductance copper column D17;
the total inductance of the Wheatstone inductive bridge in the three-dimensional integrated low-phase noise voltage-controlled oscillator is divided into the following two types:
(1) When the inductance control power supply is smaller than the threshold voltage of the TSV vertical switch, the TSV vertical switch is turned off, and the total inductance value Ltot1 of the Wheatstone inductive bridge is:
L tot1 ＝[(L 0 -ΔL)+(L 0 +ΔL)]||[(L 0 +ΔL)+(L 0 -ΔL)]＝L 0
i.e. the equivalent inductance value from the input end in1 to the output end out1 of the Wheatstone inductive bridge is L 0 。
In the above (L) 0 -DELTA.L) is equivalent to the inductance of the series connection of TSV inductors D1, D2, D3, D4 and the inductance of the series connection of TSV inductors D9, D10, D11, D12, (L) 0 + [ delta ] L) is equivalent to TSV inductors D5, D6, D7The series inductance of D8 and D18 and the series inductance of TSV inductances D13, D14, D15, D16 and D17.
(2) When the inductance control power supply is larger than the threshold voltage of the TSV vertical switch, the TSV vertical switch is conducted, and the total inductance value Ltot2 of the Wheatstone inductive bridge is as follows:
Figure BDA0003036042490000081
the Wheatstone inductive bridge (Lv 1/Lv2/Lv3/Lv 4) adopted by the voltage-controlled oscillator adjusts the total inductance value of an inductive circuit through the on/off of the TSV vertical switch (M3/M4/M5/M6), and the frequency adjustment of the voltage-controlled oscillator is realized by matching with the TSV varactors Cv1 and Cv2, wherein the inductance control power supplies are (V1/V2/V3/V4) respectively.
Compared with the traditional voltage-controlled oscillator, the three-dimensional integrated low-phase noise voltage-controlled oscillator has the advantages of small chip area, low phase noise, low power consumption under low voltage, larger amplitude of an output curve and the like.

Claims (6)

1. The three-dimensional integrated low-phase noise voltage-controlled oscillator is characterized by comprising a power supply VDD, wherein the power supply VDD is connected with a source electrode and a substrate of a TSV vertical switch M1 and a source electrode and a substrate of a TSV vertical switch M2, a grid electrode of the TSV vertical switch M1 is connected with an output end of a Wheatstone inductive bridge Lv1 and an input end of a TSV capacitive tube C2, a grid electrode of the TSV vertical switch M2 is connected with an output end of the Wheatstone inductive bridge Lv2 and an input end of the TSV capacitive tube C1, a reference voltage Vbias is connected with an input end of the Wheatstone inductive bridge Lv1 and an input end of the Wheatstone inductive bridge Lv2, a drain electrode of the TSV vertical switch M1 is connected with an input end of the TSV inductive bridge Lv1, an output end of the TSV inductive bridge L1 is connected with an input end of a resistor R1, an output end of the resistor R1 is connected with an output end of the TSV capacitive tube C1, an output end of the Wheatstone inductive bridge Lv3 is connected with an output end of the Wheatstone capacitive tube C1, an output end of the Wheatstone inductive bridge Lv2 is connected with an output end of the Wheatstone inductive bridge Lv2, and an output end of the Wheatstone inductive bridge Lv2 is connected with an output end of the Wheatstone capacitive tube C2.
2. The three-dimensional integrated low-phase noise voltage-controlled oscillator according to claim 1, wherein the TSV vertical switch M1 comprises an N-type silicon substrate (4), a vertical TSV copper column (1) is arranged in the N-type silicon substrate (4), a dielectric layer (2) is arranged on the outer side of the TSV copper column (1), p+ doped regions (7) are arranged on the outer sides of the dielectric layers (2) at the upper end and the lower end of the N-type silicon substrate (4), a rewiring layer (3) is arranged on the outer side of the p+ doped regions (7), silicon dioxide layers (6) are arranged on the upper end face and the lower end face of the TSV vertical switch M1 outside the rewiring layer (3), a source S and a drain D serving as MOS are respectively led out from the upper and lower rewiring layers (3), and a grid G serving as MOS is led out from the top end of the TSV copper column (1).
3. The three-dimensional integrated low-phase noise voltage-controlled oscillator according to claim 1, wherein the TSV inductors L1, L2, L3, L4, L5, L6 are each composed of 2N TSV inductor copper pillars.
4. The three-dimensional integrated low-phase noise voltage-controlled oscillator according to claim 1, wherein the TSV capacitor tube C1 comprises a P-type silicon substrate (5), a half-through hole TSV copper column (1) is arranged on the P-type silicon substrate (5), a dielectric layer (2) is arranged on the outer side of the half-through hole TSV copper column (1), a metal layer (8) is arranged on the outer side of the dielectric layer (2), a rewiring layer (3) is arranged on the outer side of the metal layer (8) and the outer side of the P-type silicon substrate (5), the TSV is led out by the metal layer (8) through the rewiring layer (3) on the surface of the P-type silicon substrate (5) to serve as an output end of the TSV capacitor tube C1, silicon dioxide layers (6) are arranged on the upper end face and the lower end face of the TSV capacitor tube C1 outside the rewiring layer (3), and the top end of the half-through hole TSV copper column (1) is led out to serve as an input end of the TSV capacitor tube C1.
5. The three-dimensional integrated low-phase noise voltage-controlled oscillator according to claim 1, wherein the TSV varactor Cv1 comprises a P-type silicon substrate (5), the P-type silicon substrate (5) is provided with a vertical TSV copper column (1), a grid electrode G serving as a MOS is led out from the top end of the TSV copper column (1), a dielectric layer (2) is arranged on the outer side of the TSV copper column (1), p+ doped regions (7) are respectively arranged on the outer sides of the dielectric layers (2) at the upper end and the lower end of the P-type silicon substrate (5), a rewiring layer (3) is arranged on the outer side of the p+ doped regions (7), the upper and lower rewiring layers (3) are respectively led out to serve as a source electrode S and a drain electrode D of the MOS, the source electrode S and the drain electrode D are connected to serve as output ends of the TSV varactor Cv1, silicon dioxide layers (6) are respectively arranged on the upper end face and the lower end faces of the TSV varactor C1 except the rewiring layer (3), and the grid electrode G serves as input ends of the TSV varactor.
6. The three-dimensional integrated low-phase noise voltage-controlled oscillator according to claim 1, wherein the wheatstone inductive bridges Lv1, lv2, lv3, lv4 are each composed of 4n+2 TSV inductive copper pillars and 1 TSV vertical switch.
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基于TSV技术的3D电感的设计与实现;薛宇;张洪泽;刘鹏飞;朱健;;电子元件与材料(第06期);全文 *
硅基微电感的研究;李点美;王璐;杨志;温殿忠;;黑龙江大学自然科学学报(第03期);全文 *

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