CN113259679A - Image processing system for realizing image compression based on domestic DSP chip - Google Patents
Image processing system for realizing image compression based on domestic DSP chip Download PDFInfo
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Abstract
The invention discloses an image processing system for realizing image compression based on a domestic DSP chip, which comprises a video processing component and an information processing component, wherein image data input by an external camera is decoded by the video processing component and converted into RGB video data, and the video processing component sends the RGB video data to the information processing component; characterized in that the information processing assembly comprises: the FPGA adopts JFM7K325T, the domestic DSP chip adopts FT-M6678 chip, and the core processor adopts T7-AXP 858; a domestic DSP chip and a T7-AXP858 chip are used for replacing an original imported DSP chip, the domestic DSP chip is responsible for corresponding character processing, and the T7-AXP858 chip is used for H.264 image compression and simultaneously supports an offline preview function. The data transmission and processing speed is fast, the stability is good, the domestic DSP chip is matched with the external DDR3 and the DDR3 which are specially responsible for storing data, the capacity of the processing system is large, and the universality is good.
Description
Technical Field
The invention relates to the field of image processing, in particular to an image processing system for realizing image compression based on a domestic DSP chip.
Background
With the development of electronic information technology, higher requirements are put on image data processing, and now the data processing technology enters a big data era, and the reliability and the rapidity of the data processing are less targets to be pursued. The information processing board with stronger image processing data capability in the current market has large power consumption and poor reliability.
The information processing component in the existing image processing system is mainly composed of an FPGA and 1 imported DSP chip, wherein the character processing function and the H.264 compression processing function of the image processing system are realized by the imported DSP chip, the use function is limited, and the character processing function and the H.264 compression processing function in the image processing system can be realized only by relying on the imported DSP chip.
Disclosure of Invention
The technical problem to be solved by the invention is that the existing image processing system has limited use function, and the character processing function and the H.264 compression processing function can be realized only by relying on an imported DSP chip, the scheme provides an image processing system for realizing image compression based on a domestic DSP chip, and the domestic DSP chip and a T7-AXP858 chip are used for replacing the original imported DSP chip; the connection relation between the domestic DSP chip, the domestic DSP chip and the T7-AXP858 chip and the image processing system and the composition framework of the image processing system based on the domestic DSP chip and the T7-AXP858 chip provide a new equivalent route for the existing image processing system, the domestic DSP chip is responsible for corresponding character processing, the T7-AXP858 chip is used for H.264 image compression, and simultaneously supports an off-line preview function, and under the condition of no imported chip, the character processing function and the H.264 compression processing function can still be realized.
The invention is realized by the following technical scheme:
the image processing system for realizing image compression based on the domestic DSP chip comprises a video processing component and an information processing component, wherein image data input by an external camera is decoded by the video processing component and converted into RGB video data, and the video processing component sends the RGB video data to the information processing component; characterized in that the information processing assembly comprises: the FPGA adopts JFM7K325T, the domestic DSP chip adopts a domestic FT-M6678 chip, and the core processor adopts T7-AXP 858;
the information processing component decodes and converts the RGB video data into YUV video data after receiving the RGB video data, and divides the YUV video data into two paths: the first path of YUV video data is sent to a domestic DSP chip through a high-speed bus to be analyzed and calculated to generate a character superposition instruction, and the domestic DSP chip returns the character superposition instruction to the FPGA through a low-speed bus; the FPGA carries out character superposition processing on the second channel of YUV video data according to the character superposition instruction;
the information processing component divides the YUV video data after the character superposition processing into three paths: the first path is output in a Cameralink format, the second path is output in a VGA format, and the third path is sent to a core processor for H.264 image compression by adopting a BT1120 format, and simultaneously, offline preview is supported.
The FPGA adopts JFM7K325T of the Fudan micro company, the domestic DSP chip adopts an FT-M6678 chip of the Galaxy Feiteng company, and the core processor adopts a Zhuhai Quanzhi science and technology six-core vehicle-scale intelligent high-definition SOC processor T7-AXP 858.
The working principle of the scheme is as follows: an information processing component in the existing image processing system is mainly composed of an FPGA and 1 imported DSP chip, wherein the character processing function and the H.264 compression processing function of the image processing system are realized by the imported DSP chip, and the functions are limited when the information processing component is used on equipment. The image processing system provided by the scheme realizes image compression based on the domestic DSP chip, the structure is improved based on the existing image processing system, the domestic DSP chip and a T7-AXP858 chip are used for replacing the original imported DSP chip, the connection relation between the domestic DSP chip, the T7-AXP858 chip and the image processing system and the composition framework of the image processing system based on the domestic DSP chip and the T7-AXP858 chip provide a new equivalent route for the existing image processing system, the domestic DSP chip is responsible for corresponding character processing, the T7-AXP858 chip is used for H.264 image compression and simultaneously supports an offline preview function without depending on the imported DSP chip, the function substitution is strong, a high-speed channel and a low-speed channel are arranged for data communication between the domestic DSP chip and the FPA according to the requirement of data transmission, the data transmission and processing speed are high, the domestic FT-M6678 chip is provided with a plurality of functional interfaces, the function expansion is convenient, and the stability is good.
T7-AXP858 is a brand-new generation six-core vehicle-scale intelligent high-definition SOC processor constructed by Cortex-A7 of ARM company. The built-in MCU can greatly improve the application level of the SOC on the vehicle-mounted product. The method supports intelligent operating systems such as android4.4/6.0/7.1, Linux3.10 and the like of the current mainstream; audio playback supports all mainstream music formats such as MP3, WMA, OGG, FLAC, APE, AAC, ATRA, etc.
Support full high definition video decoding, H.2654K @15fps, H.2644K @12fps, H.263, VC-1, MPEG1/2/4, DIVX/3/4/5/6, XVID, WMV7/8, VP9/D1/30fps, VP8, VP6 and the like. Supporting full high definition coding, H.2641080p @60fps, H.2651080p @60 fps; in the scheme, T7-AXP858 is configured into YUV422SP input format, and the output format is H.264.
The further optimization scheme is that the high-speed bus is an SRIO high-speed bus connected between a domestic DSP chip and the FPGA, the communication speed of the SRIO high-speed bus adopts a 3.125Gbps4x mode, and the transaction type of the SRIO high-speed bus uses NWRITE and Doorbell; NWRITE indicates writing data to the specified address and Doorbell indicates a Doorbell interrupt.
The low-speed bus is an EMIF bus connected between a domestic DSP chip and the FPGA, is connected with the FPGA by using a chip select of the EMIF and is configured into a 16-bit data mode and 24 address lines.
The further optimization scheme is that the low-speed bus is an EMIF bus connected between a domestic DSP chip and the FPGA, the FPGA is connected by using a plurality of chip selections of the EMIF, and the EMIF bus is configured into a 16-bit data mode and 24 address lines.
The further optimization scheme is that the information processing assembly further comprises a network switching module and a PHY module, the domestic DSP chip realizes network communication through the network switching module and the PHY module, and the core processor realizes network communication through the network switching module or the PHY module.
The further optimization scheme is that the PHY module comprises a JEM88E1111HV chip A and a JEM88E1111HV chip B, and the network switching module comprises an SF2507 chip;
the gigabit network port of the domestic DSP chip is connected with a JEM88E1111HV chip A through an SGMII, the JEM88E1111HV chip A is connected with an SF2507 chip, and the SF2507 chip is connected to an external network interface through a transformer;
the core processor outputs two gigabit networks: one path of gigabit network is connected to the SF2507 chip through RGMII, the other path of gigabit network is connected to the JEM88E1111HV chip B through SGMII, and the JEM88E1111HV chip B is connected to an external network interface through a transformer; the network of the core processor only uses one path for communication and debugging, and the other path is used as a reserved design.
The further optimization scheme is that the character superposition instruction comprises: the character superposition method comprises character superposition content and a character superposition position, wherein the character superposition content comprises one or more of a tracking target size gate, a cross line and time.
The further optimization scheme is that the system further comprises a DSP memory expansion module, wherein the DSP memory expansion module comprises a DDR3 externally connected with a domestic DSP chip, and the DDR3 is responsible for storing data.
The FPGA is connected with a domestic DSP chip through a GPIO, and the FPGA is connected with a core processor through the GPIO; and after data transmission between the FPGA and the domestic DSP chip or between the FPGA and the core processor is finished, sending interrupt information through the GPIO.
The further optimization scheme is that all I2C interfaces of the domestic DSP chip are connected to the FPGA through an I2C bus, and the I2C bus is provided with a pull-up resistor of 4.7K.
The information processing assembly further comprises a Cameralink output module and a VGA output module, wherein the Cameralink output module comprises a GM8285C chip, and the GM8285C chip compiles parallel data into high-speed serial data; the VGA output module comprises a GMG7123 chip, YUV video data after character superposition processing is converted into RGB digital signals through the VGA output module and then is input into the GMG7123 chip, and the GMG7123 chip outputs analog signals after the input RGB digital signals are subjected to digital-to-analog conversion.
The information processing component is provided with a VGA output and is used for debugging the image processing board. The VGA output adopts a GMG7123 chip of Chengdu electronic technology GmbH, which is provided with a 3-channel high-speed DAC chip, inputs 30-bit RGB digital signals and outputs analog signals after digital-to-analog conversion; can be applied to: digital video system (1600 × 1200@100 Hz); a high resolution color image; digital radio frequency modulation; processing an image; instrument and video signal reconstruction, etc.
The information processing assembly is provided with a Cameralink output circuit, adopts a GM82 8285C chip of Chengdu nations to compile parallel data into high-speed serial data so as to realize the rapid and reliable transmission of signals, can convert 28-bit parallel data into 4 pairs of serial LVDS differential signals, and simultaneously outputs 1 path of LVDS differential clock signals in parallel; the input clock frequency is: 25 MHz-135 MHz; the I/O voltage supports 1.8V/3.3V, the core voltage is a 28-bit programmable data strobe Channel-Link transmitter of 1.8V/3.3V, the 1080p (60 Hz) video display is supported, and the method is suitable for transmitting data in VGA, XGA, SXGA and UXGA formats from the controller to the display device; the required 1080p (50 Hz) is met.
Compared with the prior art, the invention has the following advantages and beneficial effects:
1. the image processing system for realizing image compression based on the domestic DSP chip provided by the invention is improved on the existing image processing system, and the domestic DSP chip and a T7-AXP858 chip are used for replacing the original imported DSP chip; the connection relation between the domestic DSP chip, the domestic DSP chip and the T7-AXP858 chip and the image processing system and the composition framework of the image processing system based on the domestic DSP chip and the T7-AXP858 chip provide a new equivalent route for the existing image processing system, the domestic DSP chip is responsible for corresponding character processing, the T7-AXP858 chip is used for H.264 image compression and simultaneously supports an offline preview function, the H.264 image compression and the character processing are independently completed by the two chips, the data transmission and processing speed is high, and the stability is good.
2. According to the image processing system for realizing image compression based on the domestic DSP chip, the domestic DSP chip is matched with the external DDR3 and the DDR3 are specially responsible for storing data, the capacity of the processing system is large, the universality is good, the domestic FT-M6678 chip is provided with a plurality of functional interfaces, the function expansion is convenient, and the stability is good.
3. The image processing system for realizing image compression based on the domestic DSP chip provides a new equivalent route for realizing image processing of image compression, can still realize character processing and H.264 compression processing based on the domestic DSP chip under the condition of no import DSP chip, and reduces the dependency on the import DSP chip.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a schematic diagram of data processing of an image processing system for implementing image compression based on a domestic DSP chip according to the present invention;
FIG. 2 is a schematic diagram of a video processing module according to the present invention;
FIG. 3 is a schematic diagram of an image processing system for implementing image compression based on a domestic DSP chip according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that: it is not necessary to employ these specific details to practice the present invention. In other instances, well-known structures, circuits, materials, or methods have not been described in detail so as not to obscure the present invention.
Throughout the specification, reference to "one embodiment," "an embodiment," "one example," or "an example" means: the particular features, structures, or characteristics described in connection with the embodiment or example are included in at least one embodiment of the invention. Thus, the appearances of the phrases "one embodiment," "an embodiment," "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. Further, those of ordinary skill in the art will appreciate that the illustrations provided herein are for illustrative purposes and are not necessarily drawn to scale. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In the description of the present invention, it is to be understood that the terms "front", "rear", "left", "right", "upper", "lower", "vertical", "horizontal", "high", "low", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and therefore, are not to be construed as limiting the scope of the present invention.
Example 1
As shown in fig. 1 and 3, the image processing system for implementing image compression based on a domestic DSP chip includes a video processing component and an information processing component, wherein image data input by an external camera is decoded by the video processing component and converted into RGB video data, and the video processing component sends the RGB video data to the information processing component; characterized in that the information processing assembly comprises: the FPGA adopts JFM7K325T, the domestic DSP chip adopts a domestic FT-M6678 chip, and the core processor adopts T7-AXP 858;
the information processing component decodes and converts the RGB video data into YUV video data after receiving the RGB video data, and divides the YUV video data into two paths: the first path of YUV video data is sent to a domestic DSP chip through a high-speed bus to be analyzed and calculated to generate a character superposition instruction, and the domestic DSP chip returns the character superposition instruction to the FPGA through a low-speed bus; the FPGA carries out character superposition processing on the second channel of YUV video data according to the character superposition instruction;
the information processing component divides the YUV video data after the character superposition processing into three paths: the first path is output in a Cameralink format, the second path is output in a VGA format, and the third path is sent to a core processor for H.264 image compression by adopting a BT1120 format, and simultaneously, offline preview is supported.
The FPGA adopts JFM7K325T of the Fudan micro company, the domestic DSP chip adopts an FT-M6678 chip of the Galaxy Feiteng company, and the core processor adopts a Zhuhai Quanzhi science and technology six-core vehicle-scale intelligent high-definition SOC processor T7-AXP 858.
The high-speed bus is an SRIO high-speed bus connected between a domestic DSP chip and the FPGA, the communication speed of the SRIO high-speed bus adopts a 3.125Gbps4x mode, and the transaction type of the SRIO high-speed bus uses NWRITE and Doorbell;
the low-speed bus is an EMIF bus connected between a domestic DSP chip and the FPGA, is connected with the FPGA by using a chip select of the EMIF and is configured into a 16-bit data mode and 24 address lines.
The information processing assembly further comprises a network switching module and a PHY module, the domestic DSP chip realizes network communication through the network switching module and the PHY module, and the core processor realizes network communication through the network switching module or the PHY module.
The PHY module comprises a JEM88E1111HV chip A and a JEM88E1111HV chip B, and the network switching module comprises an SF2507 chip;
the gigabit network port of the domestic DSP chip is connected with a JEM88E1111HV chip A through SGMII, the JEM88E1111HV chip A is connected with an SF2507 chip, and the SF2507 chip is connected to an external network interface XJ6 through a transformer; the XJ6 adopts the model as follows: ZD-1310-2111 connector
The core processor outputs two gigabit networks: one path of gigabit network is connected to SF2507 chip through RGMII, another path of gigabit network is connected to JEM88E1111HV chip B through SGMII, JEM88E1111HV chip B is connected to external network interface XJ6 through transformer. The XJ6 adopts the model as follows: ZD-1310-2111.
The character superimposition instruction includes: the character superposition method comprises character superposition content and a character superposition position, wherein the character superposition content comprises one or more of a tracking target size gate, a cross line and time.
The DSP memory expansion module comprises a domestic DSP chip and DDR3 externally connected with the domestic DSP chip, and the DDR3 is responsible for storing data.
The FPGA and the domestic DSP chip are connected through a GPIO, and the FPGA and the core processor are connected through the GPIO; and when the data transmission between the FPGA and the domestic DSP chip is finished or the data transmission between the FPGA and the core processor is finished, the GPIO is used for transmitting the interrupt information.
All I2C interfaces of the domestic DSP chip are connected to the FPGA via an I2C bus, and the I2C bus is configured with a pull-up resistor of 4.7K.
The information processing assembly also comprises a Cameralink output module and a VGA output module, wherein the Cameralink output module comprises a GM8285C chip, and the GM8285C chip compiles parallel data into high-speed serial data; the VGA output module comprises a GMG7123 chip, YUV video data after character superposition processing is converted into RGB digital signals through the VGA output module and then is input into the GMG7123 chip, and the GMG7123 chip outputs analog signals after the input RGB digital signals are subjected to digital-to-analog conversion.
Example 2
As shown in fig. 2, the video processing component in this embodiment includes: cameralink input, RAM and FIBER,
the external camera transmits the data to the video processing component, samples the image data using the Cameralink input clock, resolves RX [25] for the VS signal, RX [24] for the HS signal, RX [26] for the DS signal and 24bit RGB video data. The 24-bit RGB data passes through the RAM splicing bit 32bit, the transmitters are called, the optical FIBER sending module generates a reading signal, the data is read from the RAM, and the 32-bit video data is sent to the information processing component through the optical FIBER FIBER.
The video processing component mainly comprises 1 FPGA of Anlu science and technology company, 1 GM8284 chip of vibrating core science and technology company, two SIT3490 chips and an optical module (HULC-6G 10-31 IL-10L), wherein the FPGA of the Anlu science and technology company adopts a PH1A100SFG676 chip to mainly realize the processing of image information and convert the processed information into optical signals for transmission through an optical module externally hung by SEDERS; the basic block diagram of the video processing components is shown in fig. 3. The video processing component has two serial port data streams: a, one path of RS485 communicates with an information processing board, and the baud rate is 115200 bps; b, one RS422 receives 5ms synchronous signals from the information processing component.
The PH1A100SFG676 chip has a flexible logic structure, a double LUT5 structure, an equivalent LUT4 logic scale of 127872, a maximum user IO number of 400, and supports DDRx1 and DDRx2 modes; 212 DSP units are arranged in the device and can support a two-input adder, a three-input adder, a multiplier and an arithmetic logic unit; the high-speed serial transceiver with up to 8 channels supports the speed of 1.2Gbps to 6.25Gbps, integrates a PCI Express hard core, supports GEN1/2/3, supports x1 and x2 modes, and supports various protocols such as CPRI, SGMII, JESD204B, SRIO, XAUI, RXAAUI, 1000BASE-KX, 10GBASE-KX4, CEI and the like.
The Cameralink input adopts a DS90CR286MTD chip of TI, the chip can convert a 4-channel low-voltage differential signal (LVDS) into 28-bit TTL data, and a clock channel and a data channel are input in parallel; the Cameralink chip clock is maximum 66MHz, and is in 7:1 mode, the maximum single-channel data rate is 66MHz 7=462Mbps, and the total data rate is 1.848Gbps (231 MByte). The technical requirements are met: the input resolution was 1920x1080@30, with a maximum data rate of 74.25MHz × 24=1.782Gbps according to the calculated clock ≈ 74.25 MHz.
In the design, a Cameralink input signal is deserialized by a DS90CR286MTD chip to generate 28-bit parallel data (including data signals D0-D23, HS, VS, DE and CLK), an image signal format is RGB and 8bit wide, the RGB is processed by an FPGA and then is output to an information processing board through an optical fiber,
the information processing component receives the optical fiber data, decodes the 32-bit optical fiber data into 24-bit RGB data (the actual transmission requires a bandwidth of 1920 × 1080 × 50 × 32/8=414.7MB, and the actual bandwidth of the optical fiber is 6.25G/8=800 MB.), and converts the 24-bit RGB data into 24-bit YUV 4:4:4 data to prepare for subsequent image compression and character superposition. The 24-bit YUV 4:4:4 data is converted into 16-bit YUV 4:2:2 data, so that the data bandwidth can be reduced, and preparation is made for caching subsequent image compression and character superposition.
Sending the 16bit YUV data after image format conversion to a domestic DSP chip through x4 SRIO for calculation processing to obtain a character superposition instruction, wherein the resolution is 1920 × 1080 × 16bit @50fps, and the clock is 125 MHZ; the domestic DSP chip sends character information (character superposition instruction) to be superposed to the FPGA through the EMIF bus, the FPGA carries out character superposition such as wave gate, cross line, time and the like on the other path of 16-bit YUV data after image format conversion according to the character superposition instruction, and the output resolution is 1920x1080 x 16-bit @50 fps.
The FPGA completes character superposition according to the character superposition instruction, an image after character superposition passes through DDR (double data rate) cache, and an arbitration module of the FPGA outputs three processed data paths by reading the DDR:
the image after the character superposition is coded by Camlink, and the 16-bit YUV conversion bit 28-bit camera link format image data is output to a system end for display:
a: one path is output in a Cameralink format through a Cameralink output module and is displayed to a system end, and the resolution is 1920 × 1080 × 24bit @50 fps;
b: one path is output to T7-AXP858 for H.264 image compression by adopting a BT1120 format, and an offline preview function is supported;
c: one path is output in a VGA format through a VGA output module and used for user test, and the resolution is 1280, 1024, 24bit @50 fps; output pixel clock frequency: and 90 MHz.
The information processing component mainly adopts 1 piece of high-performance FPGA (JFM 7K 325T) of the double-denier micro company and 1 piece of high-performance domestic DSP (FT-M6678) chip of the Galaxy Feiteng company, and 1 core processor is used for image compression. The FPGA adopts JFM7K325T, mainly realizes the receiving and signal processing of image signals and sends the image signals to a domestic DSP chip through SRIO. The external extension of a domestic DSP chip is 1 group of 8GB DDR3, and the basic composition block diagram of an information processing component is shown in FIG. 3. The information processing assembly is provided with one path of optical fiber, the optical fiber is connected by adopting a connector with the model of 'RPB 4F 11Q', and the model of the optical module is as follows: HULC-6G10-31IL-10L, HULC-6G10-31IL-10L have the speed of 6.25Gbps, the wavelength of 1310nm, the transmissible distance of 10km, the internal integration of a blocking capacitor and the differential impedance of 100 omega. The actual transmission required bandwidth is about 2.7G, and the actual bandwidth of the optical fiber is 6.25G, so that the requirements are met.
The information processing component is provided with 2 paths of RS422 serial ports and is used for realizing external communication; the RS422 communication interface adopts a SIT3490E driving chip of Corey company to realize RS422 communication, and an ESD protection device is additionally arranged outside. And the RS422 communication interface is connected to the FPGA end through a SIT3490E driver chip. The SIT3490E is powered by 3.3V to 5.5V, is a full-duplex telling transceiver for RS422 communication, comprises a driver and an initiator, has the advantages of failure safety, overvoltage protection, overcurrent protection and +/-15 KV electrostatic protection, and can realize error-free data transmission of 14 Mbps.
The information processing component is also provided with 1 RS485 serial port for external communication; the RS485 communication interface adopts a SIT3485E driving chip with special core power to realize RS485 communication, and an ESD protection device is additionally arranged outside the RS485 communication interface. The SIT3485E is powered by 3.0V to 3.6V, is a half-duplex telling transceiver for RS422 communication, comprises a driver and a receiver, has failure safety, over-voltage protection, over-current protection and +/-15 KV electrostatic protection, and can realize error-free data transmission of 12 Mbps.
In the embodiment, the theoretical bandwidth of the DDR3 is 2666MB/S, and considering that the read-write efficiency of the DDR3 is 30-40%, the actual effective bandwidth can reach 799.8 MB/S-1066.4 MB/S.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. The image processing system for realizing image compression based on the domestic DSP chip comprises a video processing component and an information processing component and is characterized in that image data input by an external camera is decoded by the video processing component and converted into RGB video data, and the RGB video data are sent to the information processing component by the video processing component; the information processing assembly includes: the system comprises an FPGA, a domestic DSP chip and a core processor;
the information processing component decodes and converts the RGB video data into YUV video data after receiving the RGB video data, and divides the YUV video data into two paths: the first path of YUV video data is sent to a domestic DSP chip through a high-speed bus to be analyzed and calculated to generate a character superposition instruction, and the domestic DSP chip returns the character superposition instruction to the FPGA through a low-speed bus; the FPGA carries out character superposition processing on the second channel of YUV video data according to the character superposition instruction;
the information processing component divides the YUV video data after the character superposition processing into three paths: the first path is output in a Cameralink format, the second path is output in a VGA format, and the third path is sent to a core processor for H.264 image compression and simultaneously supports offline preview.
2. The image processing system for realizing image compression based on the domestic DSP chip according to claim 1,
the FPGA adopts an JFM7K325T chip of the Fudan micro company, a domestic DSP chip adopts an FT-M6678 chip of the Galaxy Feiteng company, and a core processor adopts a six-core vehicle-scale intelligent high-definition SOC processor T7-AXP858 of the Zhuhai Quanzhi technology.
3. The image processing system for realizing image compression based on the domestic DSP chip according to claim 2, wherein the high-speed bus is an SRIO high-speed bus connected between the domestic DSP chip and the FPGA, the communication rate of the SRIO high-speed bus adopts a 3.125Gbps mode, and the transaction type of the SRIO high-speed bus uses NWRITE and Doorbell;
the low-speed bus is an EMIF bus connected between a domestic DSP chip and the FPGA, is connected with the FPGA by using a chip select of the EMIF and is configured into a 16-bit data mode and 24 address lines.
4. The image processing system for realizing image compression based on the domestic DSP chip as claimed in claim 2, wherein the information processing component further comprises a network switching module and a PHY module, the domestic DSP chip realizes network communication through the network switching module and the PHY module, and the core processor realizes network communication through the network switching module or the PHY module.
5. The image processing system for realizing image compression based on the domestic DSP chip as claimed in claim 4, wherein said PHY module comprises JEM88E1111HV chip A and JEM88E1111HV chip B, and the network switching module comprises SF2507 chip;
the gigabit network port of the domestic DSP chip is connected with a JEM88E1111HV chip A through an SGMII, the JEM88E1111HV chip A is connected with an SF2507 chip, and the SF2507 chip is connected to an external network interface through a transformer;
the core processor outputs two gigabit networks: one path of gigabit network is connected to SF2507 chip through RGMII, another path of gigabit network is connected to JEM88E1111HV chip B through SGMII, JEM88E1111HV chip B is connected to external network interface through transformer.
6. The image processing system for realizing image compression based on the domestic DSP chip as claimed in claim 1, wherein said character superposition instruction comprises: the character superposition method comprises character superposition content and a character superposition position, wherein the character superposition content comprises one or more of a tracking target size gate, a cross line and time.
7. The image processing system for realizing image compression based on the domestic DSP chip as claimed in claim 1, further comprising a DSP memory expansion module, wherein said DSP memory expansion module comprises a DDR3 externally connected to the domestic DSP chip, and DDR3 is responsible for storing data.
8. The image processing system for realizing image compression based on the domestic DSP chip as claimed in claim 2, wherein the FPGA is connected with the domestic DSP chip via GPIO, and the FPGA is connected with the core processor via GPIO; and when the data transmission between the FPGA and the domestic DSP chip is finished or the data transmission between the FPGA and the core processor is finished, the GPIO is used for transmitting the interrupt information.
9. The image processing system for realizing image compression based on the domestic DSP chip as claimed in claim 2, wherein all I2C interfaces of the domestic DSP chip are connected to the FPGA via an I2C bus, and the I2C bus is configured with a pull-up resistor of 4.7K.
10. The image processing system for realizing image compression based on the domestic DSP chip as set forth in claim 1, wherein said information processing component further comprises a Cameralink output module and a VGA output module, said Cameralink output module comprises a GM8285C chip, and a GM8285C chip compiles parallel data into high-speed serial data; the VGA output module comprises a GMG7123 chip, YUV video data after character superposition processing is converted into RGB digital signals through the VGA output module and then is input into the GMG7123 chip, and the GMG7123 chip outputs analog signals after the input RGB digital signals are subjected to digital-to-analog conversion.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113709399A (en) * | 2021-08-31 | 2021-11-26 | 中国电子科技集团公司第五十八研究所 | Visual target tracking system based on DSP + FPGA |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08146930A (en) * | 1994-11-18 | 1996-06-07 | Fujitsu General Ltd | Character superimposing circuit for word processor |
| US20060232604A1 (en) * | 2005-04-15 | 2006-10-19 | Sony Corporation | Reproduction apparatus, display method thereof, display program thereof, display apparatus, and display method |
| CN102209205A (en) * | 2011-06-14 | 2011-10-05 | 中国科学院长春光学精密机械与物理研究所 | Video overlapping display device for television tracker |
| CN102708375A (en) * | 2012-04-18 | 2012-10-03 | 北方工业大学 | High-definition integrated license plate snapshot recognition equipment and method |
| CN206908724U (en) * | 2017-06-26 | 2018-01-19 | 湖南源科创新科技有限公司 | Device for graph image character adding |
| CN108319918A (en) * | 2018-02-05 | 2018-07-24 | 中国科学院长春光学精密机械与物理研究所 | A kind of Embedded Trace device and the method for tracking target applied to Embedded Trace device |
| CN112256627A (en) * | 2020-10-21 | 2021-01-22 | 四川望望科技有限公司 | High-definition high-frame-frequency real-time image processing platform and method for photoelectric tracking system |
-
2021
- 2021-06-30 CN CN202110733197.XA patent/CN113259679A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08146930A (en) * | 1994-11-18 | 1996-06-07 | Fujitsu General Ltd | Character superimposing circuit for word processor |
| US20060232604A1 (en) * | 2005-04-15 | 2006-10-19 | Sony Corporation | Reproduction apparatus, display method thereof, display program thereof, display apparatus, and display method |
| CN102209205A (en) * | 2011-06-14 | 2011-10-05 | 中国科学院长春光学精密机械与物理研究所 | Video overlapping display device for television tracker |
| CN102708375A (en) * | 2012-04-18 | 2012-10-03 | 北方工业大学 | High-definition integrated license plate snapshot recognition equipment and method |
| CN206908724U (en) * | 2017-06-26 | 2018-01-19 | 湖南源科创新科技有限公司 | Device for graph image character adding |
| CN108319918A (en) * | 2018-02-05 | 2018-07-24 | 中国科学院长春光学精密机械与物理研究所 | A kind of Embedded Trace device and the method for tracking target applied to Embedded Trace device |
| CN112256627A (en) * | 2020-10-21 | 2021-01-22 | 四川望望科技有限公司 | High-definition high-frame-frequency real-time image processing platform and method for photoelectric tracking system |
Non-Patent Citations (1)
| Title |
|---|
| 章奇: "基于DSP+FPGA构架视频处理***及其实现", 《中国优秀硕士论文全文数据库（电子期刊）》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113709399A (en) * | 2021-08-31 | 2021-11-26 | 中国电子科技集团公司第五十八研究所 | Visual target tracking system based on DSP + FPGA |
| CN113709399B (en) * | 2021-08-31 | 2024-03-08 | 中国电子科技集团公司第五十八研究所 | Visual target tracking system based on DSP+FPGA |
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