CN113259035A - Clock synchronization method - Google Patents
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- CN113259035A CN113259035A CN202010223493.0A CN202010223493A CN113259035A CN 113259035 A CN113259035 A CN 113259035A CN 202010223493 A CN202010223493 A CN 202010223493A CN 113259035 A CN113259035 A CN 113259035A
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- 230000001360 synchronised effect Effects 0.000 claims description 5
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- H—ELECTRICITY
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- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
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- H—ELECTRICITY
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Abstract
The invention discloses a clock synchronization method, which relates to the field of computer embedding.A GPS module sends clock information data to a Micro Control Unit (MCU) through a serial port, the MCU receives the clock information data from the GPS module through interrupt mode serial port communication, when the serial port data of the GPS module is output, the other port line generates a jump of high and low level to trigger the MCU external interrupt, a timer is started in the MCU external interrupt to analyze a standard positioning time unit, so that the GPS time from a satellite is obtained, the time is the basic time of clock synchronization, the timer calculates the time error difft caused by serial communication and data analysis and corrects the time, and the sum of the GPS time and the time error difft calculated by the timer; the invention combines the software and hardware technical means to correct the errors caused by time consumption of communication receiving, data analysis and operation, and ensures the high precision of time sequence synchronization.
Description
Technical Field
The invention relates to the field of computer embedding, in particular to the field of clock synchronization.
Background
Patent CN106817184B discloses a clock synchronization system, which includes: the built-in GPS receiver is used for locking a GPS satellite after receiving a GPS signal output by an external GPS antenna and outputting a 1PPS clock signal and a TX differential signal after locking the GPS satellite; the test circuit board is respectively connected with the built-in GPS receiver, the main port and the plurality of slave ports and is used for respectively outputting the 1PPS clock signal and the TX differential signal output by the built-in GPS receiver to the main port and the plurality of slave ports; the master port and the plurality of slave ports are respectively used for outputting the received 1PPS clock signal and the TX differential signal to equipment which is connected with the master port and the plurality of slave ports and needs clock synchronization so as to realize clock synchronization of the equipment; and the power interface is respectively connected with the built-in GPS receiver and the test circuit board and is used for respectively supplying power to the built-in GPS receiver and the test circuit board after being connected with an external power supply. The invention has low cost and short synchronization time.
Patent CN109039513A clock synchronization method, device, equipment and storage medium, disclosing a clock synchronization method, device, equipment and storage medium. The method comprises the following steps: acquiring a GPS clock signal through a local satellite positioning system GPS device; and carrying out time calibration on a local clock according to the GPS clock signal. According to the embodiment of the invention, the local clocks of the network nodes of the block chain are calibrated according to the GPS, so that the local clocks of the network nodes of the block chain can be accurately synchronized, and the stability of block output operation is improved.
Patent CN109814370A discloses a clock synchronization system, a clock synchronization method, a clock synchronization device, a clock synchronization apparatus, and a storage medium. The method comprises the following steps: acquiring a GPS clock signal through a local satellite positioning system GPS device; and carrying out time calibration on a local clock according to the GPS clock signal. According to the embodiment of the invention, the local clocks of the network nodes of the block chain are calibrated according to the GPS, so that the local clocks of the network nodes of the block chain can be accurately synchronized, and the stability of block output operation is improved.
The method does not consider that the time-consuming error in the communication receiving process affects the time sequence synchronization precision and the time-consuming error in the data analysis process, and affects the time sequence synchronization precision.
Disclosure of Invention
The embodiment of the invention provides a clock synchronization method. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
According to a first aspect of the embodiments of the present invention, a clock synchronization method is provided, which specifically includes the following steps:
s1: the GPS module sends clock information data to the MCU through a serial port, and the MCU receives the clock information data of the GPS module through interrupt mode serial port communication;
s2: when the serial port data output of the GPS module starts, one port line of the GPS module generates one jump of high and low levels, triggers the MCU external interrupt, and starts a timer in the MCU external interrupt;
s3: analyzing the clock information data of the GPS module to obtain a standard positioning time unit, thereby obtaining the GPS time from the satellite, namely the synchronous basic time;
s4: the timer calculates a time error difft caused by serial communication and data analysis;
s5: the time of the clock is corrected by the sum of the GPS time and the time error difft calculated by the timer, that is,
the correction time is GPS time + difft.
Preferably, the GPS module outputs GPS information that conforms to the RMC specification, wherein the standard positioning time cell format is time minutes, seconds, and second, with a resolution of milliseconds.
Preferably, the priority of the MCU external interrupt is higher than the priority of the MCU interrupt mode serial port communication, and the priority of the MCU external interrupt is the highest priority.
Preferably, the MCU external interrupts the clear timer value and resets the timer.
Preferably, the precision of the timer is 0.01ms, i.e. it is accumulated every 0.01ms, and the timer accumulation sum is diff.
Preferably, the data parsing includes a verification operation, which includes the following steps:
s31: checking whether the frame head and the frame tail are in compliance;
s32: checking whether the checksum is correct;
s33: checking whether the value of the positioning status unit is available.
Preferably, the time error caused by the data analysis is communication receiving time and data analysis time.
Preferably, the time error diff is the product of the timer accumulation sum diff and the timer precision, i.e.,
difft＝diff×0.01ms。
preferably, the correction time is GPS time + offset, and specifically includes a calculation time consumption, that is,
the correction time is GPS time + difft + computation time consumption.
Preferably, the correction time is GPS time + difft, and the calculation of the formula becomes language using embedded assembly code.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
the GPS module is adopted to acquire time, and the errors caused by time consumption of communication receiving, data analysis and operation are corrected by combining software and hardware technical means, so that the high precision of time sequence synchronization is ensured. Meanwhile, a clock chip is designed, and time is acquired from the clock chip under the condition that the GPS signal does not exist or is weak, so that time sequence synchronization is realized, and full coverage of an application scene is guaranteed. High precision and full coverage of application scenes, balance the performance of the system and the application scenes, and are beneficial to popularization and application of products. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a logic flow diagram illustrating a clock synchronization method in accordance with an exemplary embodiment;
FIG. 2 is a diagram illustrating serial communications and external interrupt circuitry in accordance with an exemplary embodiment;
fig. 3 is a diagram illustrating a standby clock circuit according to an example embodiment.
Detailed Description
The following description and the drawings sufficiently illustrate specific embodiments of the invention to enable those skilled in the art to practice them. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. The scope of embodiments of the invention encompasses the full ambit of the claims, as well as all available equivalents of the claims. Embodiments may be referred to herein, individually or collectively, by the term "invention" merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed. Herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed. The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the structures, products and the like disclosed by the embodiments, the description is relatively simple because the structures, the products and the like correspond to the parts disclosed by the embodiments, and the relevant parts can be just described by referring to the method part.
It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.
It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.
The invention is further described with reference to the following figures and examples:
as shown in fig. 1, a clock synchronization method specifically includes the following steps:
s1: the GPS module sends clock information data to the MCU through a serial port, and the MCU receives the clock information data of the GPS module through interrupt mode serial port communication;
s2: when the serial port data output of the GPS module starts, one port line of the GPS module jumps at a high level and a low level, triggers the MCU external interrupt, and starts a timer in the MCU external interrupt
S3: analyzing the clock information data of the GPS module to obtain a standard positioning time unit, thereby obtaining the GPS time from the satellite, namely the synchronous basic time;
s4: the timer calculates a time error difft caused by serial communication and data analysis;
s5: the time of the clock is corrected by the sum of the GPS time and the time error difft calculated by the timer, that is,
the correction time is GPS time + difft.
According to the above scheme, further, the GPS module adopts a Gstar series GPS module, and the GPS module outputs GPS information that meets the RMC specification, where the standard positioning time unit format is time division, minute, second, and millisecond, and the resolution is millisecond, and the RMC outputs an example:
$GPRMC,161229.487,A,3723.2475,N,12158.3416,W,0.13,309.62,120598,,*10<CR><LF>，
the specific protocol is as follows in the RMC specification:
according to the scheme, as shown in fig. 2, an ARM core chip STM32F103VC is selected, a port line PB10 receives external interrupts of the GPS module, and a port line PB11 is a serial port receiving port and receives data of the GPS module; the ARM core supports 4 levels of interrupts, interrupt processing priorities of different levels are different, a high-level interrupt can interrupt processing flows of a low-level interrupt and a main loop, after the high-level interrupt processing is finished, the low-level interrupt or the main loop continues the processing flows from a breakpoint, the priority of the MCU external interrupt is higher than that of the MCU interrupt mode serial port communication, and the priority of the MCU external interrupt is the highest priority.
According to the scheme, further, after the port line PB10 of the MCU STM32F103VC receives the external interrupt, the timer value is cleared, and the timer is reset.
According to the above scheme, further, the precision of the timer is 0.01ms, namely, the timer is accumulated once every 0.01ms, and the accumulated sum of the timer is diff.
According to the above scheme, further, the data analysis includes a verification operation, which includes the following steps:
s31: checking whether the frame head and the frame tail are in compliance;
s32: checking whether the checksum is correct;
s33: checking whether the value of the positioning status unit is available.
According to the above scheme, further, the time error caused by the data analysis is consumed by communication reception and data analysis.
According to the above solution, further, the time error diff is a product of the timer accumulated sum diff and the timer precision, that is,
difft＝diff×0.01ms。
according to the above scheme, further, the correction time is GPS time + difft, and the MCU needs to perform a multiplication and an addition, and two instructions may consume operation time, which results in the correction time being GPS time + difft + operation time.
According to the above scheme, further, the correction time is the GPS time + offset formula, and the calculation of this formula in this embodiment uses embedded assembly code, and the register is directly operated to implement the above multiplication and addition operations. The purpose is as follows: on one hand, the code execution time is reduced, the calculation efficiency is guaranteed, and on the other hand, the theoretical time consumption of the correlation operation is convenient to calculate and is used for correcting the time error.
According to the scheme, further, the timing synchronization solution based on the GPS depends on satellites, and in some application fields (such as mountains, mountains and mountains, and indoors), satellites cannot be searched or the number of searched satellites is too small, so that signals cannot be received or the confidence of the received signals is low and unavailable, and the realization of the timing synchronization function is influenced; in this case, the design uses a clock chip DS1307 to implement timing synchronization to ensure full coverage of the application scenario, as shown in fig. 3, the technical principle is as follows: the clock chip DS1307 is periodically accessed through the I2C bus, and the ARM chip can acquire date and time information; and meanwhile, a lithium battery circuit is designed to ensure that the clock chip DS1307 can normally work under the condition of power loss. Under the condition of giving initial date and time and not losing power, the clock chip can guarantee continuous work for up to several years. By using the clock chip as a time base, timing synchronization accurate to the order of seconds can be achieved.
The invention relates to a clock synchronization method, which adopts a GPS module to acquire time, combines software and hardware technical means to correct errors caused by time consumption of communication receiving, data analysis and operation, and ensures high precision of time sequence synchronization. Meanwhile, a clock chip is designed, and time is acquired from the clock chip under the condition that the GPS signal does not exist or is weak, so that time sequence synchronization is realized, and full coverage of an application scene is guaranteed. High precision and full coverage of application scenes, balance the performance of the system and the application scenes, and are beneficial to popularization and application of products.
It is to be understood that the present invention is not limited to the procedures and structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the invention is limited only by the appended claims.
Claims (10)
1. A clock synchronization method is characterized by comprising the following steps:
s1: the GPS module sends clock information data to the MCU through a serial port, and the MCU receives the clock information data of the GPS module through interrupt mode serial port communication;
s2: when the serial port data output of the GPS module starts, one port line of the GPS module generates one jump of high and low levels, triggers the MCU external interrupt, and starts a timer in the MCU external interrupt;
s3: analyzing the clock information data of the GPS module to obtain a standard positioning time unit, thereby obtaining the GPS time from the satellite, namely the synchronous basic time;
s4: the timer calculates a time error difft caused by serial communication and data analysis;
s5: the time of the clock is corrected by the sum of the GPS time and the time error difft calculated by the timer, that is,
the correction time is GPS time + difft.
2. The method of claim 1, wherein the GPS module outputs GPS information in compliance with RMC specifications, wherein the standard positioning time unit format is in minute seconds second with a resolution of milliseconds.
3. The clock synchronization method according to claim 1, wherein the priority of the MCU external interrupt is higher than the priority of the MCU interrupt mode serial port communication, and the priority of the MCU external interrupt is the highest priority.
4. The clock synchronization method according to claim 3, wherein the MCU external interrupt clears the timer value and resets the timer.
5. The clock synchronization method according to claim 4, wherein the precision of the timer is 0.01ms, i.e. the timer is accumulated every 0.01ms, and the timer accumulation sum is diff.
6. The clock synchronization method according to claim 1, wherein the data parsing comprises a verification operation, and the method comprises the following steps:
s31: checking whether the frame head and the frame tail are in compliance;
s32: checking whether the checksum is correct;
s33: checking whether the value of the positioning status unit is available.
7. The clock synchronization method according to claim 1, wherein the time error caused by the data analysis is a communication reception time and a data analysis time.
8. The clock synchronization method according to claim 7, wherein the time error diff is a product of the timer accumulation sum diff and the timer precision, that is,
difft＝diff×0.01ms。
9. the clock synchronization method according to claim 8, wherein the correction time is GPS time + difft, and further comprises computation time consumption, that is,
the correction time is GPS time + difft + computation time consumption.
10. The clock synchronization method according to claim 9, wherein the correction time is GPS time + difft, and the calculation of the formula is language embedded assembly code.
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