CN113258881A - Asymmetric Doherty power amplifier based on high-power back-off - Google Patents
Asymmetric Doherty power amplifier based on high-power back-off Download PDFInfo
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Abstract
The invention discloses an asymmetric Doherty power amplifier based on high-power back-off, which comprises a power divider, a carrier power amplifier phase compensation line, a carrier power amplifier module, a peak power amplifier module, a back matching network and load impedance, wherein the output end of the back matching network is connected with the load impedance by using a step impedance transformation line structure, the peak power amplifier module inhibits second harmonic waves, the peak power amplifier compensation line of the traditional back matching type Doherty power amplifier is omitted, the saturated power and the high efficiency of the peak power amplifier module are realized, the problem of larger power consumption of the power amplifier is further solved, and the output end of the back matching network is connected with the load impedance by using the step impedance transformation line structure, so that the Doherty power amplifier has a simple structure and is easy to design.
Description
Technical Field
The invention relates to the field of microwave power amplifiers, in particular to an asymmetric Doherty power amplifier based on high-power back-off.
Background
With the rapid development of modern wireless communication technology, the peak-to-average ratio of the modulated signal is higher and higher, and in such a background, the Doherty power amplifier draws wide attention and research because it can effectively improve the efficiency of the back-off operation.
Due to the bandwidth limitation caused by the quarter wavelength line of the traditional Doherty power amplifier, the designed Doherty power amplifier can only work in a narrow bandwidth range, which does not meet the development requirement of the broadband of the current wireless communication technology. In recent years, a rear matching type Doherty power amplifier is proposed, which not only omits a traditional quarter-wavelength line, but also provides a more diversified design for the dual-impedance matching design of a carrier power amplifier, and provides more design possibilities for improving the efficiency at a power back-off point.
The design of the current mainstream rear-matching type Doherty power amplifier mainly comprises a symmetrical Doherty power amplifier and an asymmetrical Doherty power amplifier, the asymmetrical design concept provides a larger choice for expanding the power back-off interval of the Doherty power amplifier, the current mainstream asymmetrical high-power back-off Doherty power amplifier in the market is designed by utilizing two transistors with larger power ratio difference, so that a larger power back-off interval is obtained, the mode increases the design cost and the waste of power undoubtedly, and therefore, the design of the Doherty power amplifier with low cost, low power ratio and large power back-off range becomes an important research hotspot.
Disclosure of Invention
The invention provides an asymmetric Doherty power amplifier based on high-power back-off, which aims to overcome the problem that the power amplifier consumes larger power.
In order to achieve the purpose, the technical scheme of the invention is as follows:
an asymmetric Doherty power amplifier based on high power back-off, comprising: the power divider, a carrier power amplifier phase compensation line, a carrier power amplifier module, a peak power amplifier module, a back matching network and load impedance;
the output end of the power divider is connected with the input end of the carrier power amplifier phase compensation line and the input end of the peak power amplifier module, the output end of the carrier power amplifier phase compensation line is connected with the input end of the carrier power amplifier module, the output end of the carrier power amplifier module and the output end of the peak power amplifier module are connected with the input end of the rear matching network, and the output end of the rear matching network is connected with the load impedance by using a stepped impedance transformation line structure;
the carrier power amplifier module comprises a carrier input matching network, a carrier amplifier and a carrier output matching network, wherein the input end of the carrier input matching network is connected with the output end of the carrier power amplifier phase compensation line, the output end of the carrier input matching network is connected with the grid electrode of the carrier amplifier, and the carrier output matching network is connected with the drain electrode of the carrier amplifier;
the peak power amplifier module comprises a peak input matching network, a peak amplifier and a peak output matching network, wherein the input end of the peak input matching network is connected with the output end of the power divider, the output end of the peak input matching network is connected with the grid electrode of the peak amplifier, and the input end of the peak output matching network is connected with the drain electrode of the peak amplifier.
Further, the power divider includes a first port, a second port, a third port, a first ohmic line TL1, a first microstrip line TL2, a second microstrip line TL3, a first capacitor C1, a second capacitor C2, a first inductor L1, a second inductor L2, and a first resistor R1, where the first port is connected to one end of the first ohmic line TL1, the other end of the first ohmic line TL1 is connected to one end of the first microstrip line TL2 and one end of the second microstrip line TL3, the other end of the first microstrip line TL2 is connected to one end of the first resistor R1, one end of the first capacitor C1, and one end of the first inductor L1, the other end of the second microstrip line TL3 is connected to the other end of the first resistor R1 and one end of the second inductor L2, the other end of the first inductor L1 is connected to the second port, and the other end of the second microstrip line L2 is connected to the second capacitor C2 and the third port.
Further, the carrier input matching network and the peak input matching network are connected in parallel with the capacitor by utilizing a microstrip line; the third capacitor C3 is connected with the first inductor L1 in series and then connected with one end of a first ohmic line TL1 and one end of a first microstrip line TL2, the other end of the first microstrip line TL2 is connected with one end of a second microstrip line TL3 and one end of a third microstrip line TL4, the other end of the second microstrip line TL3 is connected with the first capacitor C1, the other end of the third microstrip line TL4 is connected with one end of a fourth microstrip line TL5 and one end of a fifth microstrip line TL6, and the other end of the fourth microstrip line TL5 is connected with the second capacitor C2.
Further, the carrier output matching network is in a stepped impedance transformation line structure.
Further, the output matching network is a quasi-elliptic filtering structure.
Furthermore, the carrier power amplifier phase compensation line is a 50 ohm microstrip line.
Has the advantages that: according to the Doherty power amplifier, the peak power amplifier module is used for inhibiting the second harmonic wave, a peak power amplifier compensation line of the traditional rear matching type Doherty power amplifier is omitted, the saturated power and the high efficiency of the peak power amplifier module are realized, and the problem of high power consumption of the power amplifier is further solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a block diagram of the overall structure of the present invention;
FIG. 2 is a schematic diagram of the relationship between the carrier power amplifier and the peak power amplifier for dual impedance matching according to the present invention;
FIG. 3(a) shows the power ratio of the present invention is 1: 1.5 about X;
FIG. 3(b) shows the power ratio of the present invention is 1: 1.5 vs. ZL;
FIG. 4 is a block diagram of the power divider of the present invention;
FIG. 5(a) is a graph of output port matching results at saturated output power of the present invention;
FIG. 5(b) is a diagram of the output port matching result under power back-off of the present invention;
FIG. 6 is a diagram of a peak amplifier quasi-elliptical filter output matching structure and impedance relationship in accordance with the present invention;
FIG. 7 is a solution space for impedance matching of the peak amplifier of the present invention at power back-off;
FIG. 8 is a graph of drain efficiency versus gain and output power provided by the present invention;
fig. 9 is a diagram of the input matching structure of the present invention using microstrip lines and capacitor parallel capacitors.
The power divider comprises a power divider, a carrier power amplifier phase compensation line, a carrier power amplifier module, a peak power amplifier module, a rear matching network, a load impedance, a carrier input matching network, a carrier amplifier, a carrier output matching network, a peak input matching network, a carrier amplifier, a carrier output matching network, a carrier input matching network, a carrier amplifier, a carrier output matching network, a carrier input matching network, a carrier output matching network and a carrier output matching network, wherein the carrier power amplifier is 1, the carrier power amplifier is 2, the carrier power amplifier is 3.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment provides an asymmetric Doherty power amplifier based on high-power back-off, as shown in fig. 1 to 9, including: the power divider comprises a power divider 1, a carrier power amplifier phase compensation line 2, a carrier power amplifier module 3, a peak power amplifier module 4, a rear matching network 5 and load impedance 6;
the output end of the power divider 1 is connected with the input end of the carrier power amplifier phase compensation line 2 and the input end of the peak power amplifier module 4, the output end of the carrier power amplifier phase compensation line 2 is connected with the input end of the carrier power amplifier module 3, the output end of the carrier power amplifier module 3 and the output end of the peak power amplifier module 4 are connected with the input end of the rear matching network 5, and the output end of the rear matching network 5 is connected with the load impedance 6 by using a stepped impedance transformation line structure;
the carrier power amplifier module 3 comprises a carrier input matching network 3-1, a carrier amplifier 3-2 and a carrier output matching network 3-3, wherein the input end of the carrier input matching network 3-1 is connected with the output end of the carrier power amplifier phase compensation line 2, the output end of the carrier input matching network 3-1 is connected with the grid electrode of the carrier amplifier 3-2, and the carrier output matching network 3-3 is connected with the drain stage of the carrier amplifier 3-2;
the peak power amplifier module 4 comprises a peak input matching network 4-1, a peak amplifier 4-2 and a peak output matching network 4-3, wherein the input end of the peak input matching network 4-1 is connected with the output end of the power divider 1, the output end of the peak input matching network 4-1 is connected with the grid electrode of the peak amplifier 4-2, and the input end of the peak output matching network 4-3 is connected with the drain stage of the peak amplifier 4-2.
In a specific embodiment, the power divider includes a first port, a second port, a third port, a first ohmic line TL1, a first microstrip line TL2, a second microstrip line TL3, a first capacitor C1, a second capacitor C2, a first inductor L1, a second inductor L2, and a first resistor R1, where the first port is connected to one end of the first ohmic line TL1, the other end of the first ohmic line TL1 is connected to one end of the first microstrip line TL2 and one end of the second microstrip line TL3, the other end of the first microstrip line TL2 is connected to one end of the first resistor R1, one end of the first capacitor C1, and one end of the first inductor L1, the other end of the second microstrip line 3 is connected to the other end of the first resistor R1 and one end of the second inductor L2, the other end of the first inductor L1 is connected to the second port, and the other end of the second microstrip line L2 is connected to the second capacitor C2 and the third port.
In a specific embodiment, the carrier input matching network and the peak input matching network are connected in parallel by a microstrip line and a capacitor; the third capacitor C3 is connected with the first inductor L1 in series and then connected with one end of a first ohmic line TL1 and one end of a first microstrip line TL2, the other end of the first microstrip line TL2 is connected with one end of a second microstrip line TL3 and one end of a third microstrip line TL4, the other end of the second microstrip line TL3 is connected with the first capacitor C1, the other end of the third microstrip line TL4 is connected with one end of a fourth microstrip line TL5 and one end of a fifth microstrip line TL6, and the other end of the fourth microstrip line TL5 is connected with the second capacitor C2.
In a specific embodiment, the carrier output matching network is a ladder impedance transformation line structure.
In a particular embodiment, the output matching network 4-3 is a quasi-elliptical filtering structure.
In a specific embodiment, the carrier power amplifier phase compensation line 2 is a 50 ohm microstrip line.
In a specific embodiment, the carrier of the high-power back-off asymmetric Doherty power amplifier selects a CGH4000P transistor, a drain adopts 28V direct current for power supply, the saturation output power is 6-8W, a peak amplifier 4-1 adopts a CGH40010F transistor, a drain adopts 28V direct current for power supply, and the saturation output power is 10-13W. The invention takes an asymmetric Doherty power amplifier with 9.5dB power back-off as an example, and the power ratio alpha is 1.5.
In practical application, when the peak power amplifier module of the conventional rear-matching Doherty power amplifier inputs power in a small signal, the output impedance is infinite, and the impedance relationship between the carrier power amplifier module and the peak power amplifier module at the combining point is as follows:
wherein P isc,satIs the saturated output power, P, of the carrier power amplifier modulep,satIs the saturated output power, P, of the peak power amplifier modulec,oboThe carrier power amplifier module is used for outputting power in a backspacing mode, ZL is a combination point impedance, alpha is the ratio of peak saturated output power to carrier saturated output power, or the ratio of the saturated output impedance of the carrier power amplifier module to the saturated output impedance of the peak power amplifier module at the combination point, beta is the ratio of the saturated output power of the carrier power amplifier to backspacing output power, OBO is power backspacing, and SAT is power saturation.
In an actual broadband power amplifier, only when the output impedance of the peak power amplifier module at the working center frequency point is infinite and deviates from infinity at other frequency points, the impedance which is not infinite affects the performance of the carrier power amplifier in a low-power region, and further affects the performance of the broadband Doherty power amplifier, so that the low-power working state of the peak power amplifier module needs to be analyzed. The peak power amplifier module 4 of the invention is biased in class C, before the work begins, the load impedance solution space falls on the edge of the Smith circular diagram, after the work begins, the impedance space moves to the middle of the circular diagram, therefore, the impedance of the peak power amplifier module 4 before the work begins is pure virtual impedance, which is marked as jX, and | gamma can be obtained according to the power back-off design formula (6)c1The reflection coefficient formula expression of the carrier power amplifier module 3 at the combining point is obtained by the formula of:
wherein Zc1,oboIs a combining point carrier back-off impedance, Zc1,satIs a combined point carrier saturated impedance, Zc1,satThe conjugate of the carrier saturation impedance of the combining point, ZL the impedance of the combining point at the rear matching position, and jX the impedance of the peak power amplifier at the combining point during the backspacing.
The power back-off is mainly determined by X, ZL and the power ratio alpha according to the formula (6) to the formula (8), and the back-off is larger when the power is larger.
Fig. 2 shows an impedance relationship of the dual impedance matching network, specifically, the impedance is represented by an impedance relationship of the carrier power amplifier module 3 in formula (9) and an impedance relationship of the peak power amplifier module 4 in formula (10):
from the above formula in conjunction with fig. 3(a) and fig. 3(b), the power back-off increases with the increase of ZL and the decrease of X, when X is selected to be 24, and ZL is selected to be 15, the power back-off of the conventional rear matching Doherty power amplifier is 9.5dB, the power back-off of the present invention is 8dB, compared with the power back-off increased by 1.5 dB.
In practical work, with reference to fig. 4, the power divider 1 of the present invention adopts a miniaturized unequal power divider design for distributing input power, where the power ratio is 1: 1.5. as shown in fig. 4, TL1 is a 50 ohm line, the length does not affect the power divider effect, TL2 and TL3 are 90 ° microstrip lines, the impedance Z2 is 87.5 ohms, the impedance Z3 is 50.3 ohms, the impedances of nodes Z4 and Z5 are 61.2 ohms and 40.8 ohms, respectively, in fig. 4, Term1 is a first port, Term2 is a second port, Term3 is a third port, and the first, second, and third ports are all 50 ohms. For miniaturized design, arm 2 and arm 3 are matched with LC matching circuits, arm 2 is matched to 50 ohms from Z4, arm 3 is matched to 50 ohms from Z5, and isolation resistance is 100 ohms, respectively.
The carrier power amplifier phase compensation line 2 adopts a 50 ohm microstrip line design, the electrical length of the carrier power amplifier phase compensation line is determined by the phase relation of two paths of the carrier power amplifier module 3 and the peak power amplifier module 4 at a combining point, and the electrical length is selected to be 30 degrees so as to ensure that output signals are combined in phase at the combining point.
The carrier power amplifier module 3 comprises a carrier input matching network 3-1, a carrier amplifier 3-2 and an output matching network 3-3 which are sequentially connected in series. The carrier amplifier 3-2 works in an AB working state, the transistor adopts CGH40006P as an example, the drain electrode of the transistor adopts a 28V direct current power supply for power supply, before the input and output matching circuit is designed, stability design is carried out, and after the transistor meets the full frequency stability of a working frequency band, source traction and load traction are carried out. The output matching network 3-3 of the carrier power amplifier module 3 adopts a double-impedance matching mode, obtains the optimal impedance of the carrier power amplifier module 3 in the backspacing and saturation through load traction, and enables the optimal impedance to be matched with 37.5 ohms in the saturation and to be matched with 10.8+ j x 6.7 ohms in the backspacing at a combining point, as shown in fig. 5(a) and 5(b), the matching conditions of the carrier power amplifier module 3 in the saturation state and the backspacing state are obtained by an optimization circuit built by an ADS electromagnetic simulation platform, S11 and S33 are both below-15 dB, and the two states achieve good matching.
The peak power amplifier module 4 comprises a peak input matching network 4-1, a peak power amplifier 4-2 and an output matching network 4-3 which are connected in series in sequence. The peak power amplifier module works in C-type bias, the CGH40010F is selected as a transistor, and the drain electrode of the transistor is supplied with 28V direct current. The peak output matching circuit 4-3 employs a quasi-elliptic filtering structure for second harmonic suppression, as shown in fig. 6. The output matching network 4-3 is required to satisfy a double-impedance matching state in a saturation state and a backspacing state, a point with the maximum output power is obtained by load traction in the saturation state, and an impedance solution area which does not start working in a C-type state is obtained by load traction in the backspacing state. As shown in fig. 7, the impedance solution space that the peak power amplifier module 4 needs to match when backing off is matched from Zp, out to Zp1, obo, and the saturation state satisfies Zp matching to Zp 1.
The rear matching structure 5 shown in the invention is composed of a stepped impedance transformation line, so that 15-ohm impedance transformation at the combination point to the load output impedance of 50-ohm is completed.
Fig. 8 is a graph of the relationship between the output power and the drain efficiency of the invention, and it can be seen from the graph that the saturation efficiency is 64% -72% and the efficiency at the 9.5dB power back-off is 55% -62% in the operating band of 500MHz-650MHz, which indicates that the Doherty power amplifier designed by the invention has better performance in the broadband performance, efficiency performance and back-off interval compared with the asymmetric post-matching Doherty power amplifier.
The working principle of the asymmetric Doherty power amplifier with high-power back-off of the invention is as follows:
when an input signal is small, the whole Doherty power amplifier is in a low-power working state, the whole Doherty power amplifier is only opened to work by the carrier power amplifier module 3, the working state is AB type, the peak power amplifier module 4 is in a C type bias working state and does not start to work, the output impedance of the Doherty power amplifier is positioned at the edge of a Smith chart, and the whole Doherty work reaches a peak point of first working efficiency; with the continuous increase of the input signal, the equivalent output impedance of the Doherty power amplifier entering the peak power amplifier module 4 in the medium power amplification state starts to move from the edge of the Smith chart to the inside of the chart, and the peak power amplifier module 4 gradually moves to the opening state; when the output currents of the carrier power amplifier module 3 and the peak power amplifier module 4 are equal in phase, the Doherty power amplifier is in a high-power working state, the two power amplifiers work together, and at the moment, the whole Doherty circuit reaches a second efficiency peak point.
The invention expands the power back-off interval of the traditional rear matching type Doherty power amplifier by starting from the back-off point impedance of the peak power amplifier module 4 to non-infinite impedance and utilizing the active load modulation principle of the Doherty power amplifier. That is, the carrier power amplifier module 3 adopts a stepped impedance transformation line structure to perform a double impedance matching design, so that the back impedance of the combining point is matched to the maximum efficiency point of the back load traction of the carrier power amplifier module 3, and the combined saturation impedance of the combining point is matched to the maximum power point of the saturation load traction of the carrier power amplifier module 3. For the peak power amplifier module 4, the output matching adopts a quasi-elliptic filtering structure to improve the saturation efficiency and saturation output power of the peak power amplifier module 4, the matching mode still adopts double impedance matching, when backing, the combining point peak power amplifier module 4 is a C-type working point of pure imaginary impedance matching to the peak power amplifier module 4, and when saturation, the real impedance matching of the combining point peak power amplifier module 4 is to the maximum output power point of the saturation load traction of the peak power amplifier module 4. And the two paths of combined circuits are connected through a rear matching network, so that the design of the whole Doherty power amplifier is realized.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (6)
1. An asymmetric Doherty power amplifier based on high power back-off, comprising: the power divider comprises a power divider (1), a carrier power amplifier phase compensation line (2), a carrier power amplifier module (3), a peak power amplifier module (4), a rear matching network (5) and load impedance (6);
the output end of the power divider (1) is connected with the input end of the carrier power amplifier phase compensation line (2) and the input end of the peak power amplifier module (4), the output end of the carrier power amplifier phase compensation line (2) is connected with the input end of the carrier power amplifier module (3), the output end of the carrier power amplifier module (3) and the output end of the peak power amplifier module (4) are connected with the input end of the rear matching network (5), and the output end of the rear matching network (5) is connected with the load impedance (6) by using a stepped impedance transformation line structure;
the carrier power amplifier module (3) comprises a carrier input matching network (3-1), a carrier amplifier (3-2) and a carrier output matching network (3-3), wherein the input end of the carrier input matching network (3-1) is connected with the output end of the carrier power amplifier phase compensation line (2), the output end of the carrier input matching network (3-1) is connected with the grid electrode of the carrier amplifier (3-2), and the carrier output matching network (3-3) is connected with the drain stage of the carrier amplifier (3-2);
the peak power amplifier module (4) comprises a peak input matching network (4-1), a peak amplifier (4-2) and a peak output matching network (4-3), wherein the input end of the peak input matching network (4-1) is connected with the output end of the power divider (1), the output end of the peak input matching network (4-1) is connected with the grid electrode of the peak amplifier (4-2), and the input end of the peak output matching network (4-3) is connected with the drain stage of the peak amplifier (4-2).
2. The asymmetric Doherty power amplifier based on high power back-off of claim 1, wherein: the power divider (1) comprises a first port, a second port, a third port, a first ohmic line TL1, a first microstrip line TL2, a second microstrip line TL3, a first capacitor C1, a second capacitor C2, a first inductor L1, a second inductor L2 and a first resistor R1, wherein the first port is connected with one end of the first ohmic line TL1, the other end of the first ohmic line TL1 is respectively connected with one end of the first microstrip line TL2 and one end of the second microstrip line TL3, the other end of the first microstrip line TL2 is respectively connected with one end of a first resistor R1, one end of a first capacitor C1 and one end of a first inductor L1, the other end of the second microstrip line TL3 is respectively connected with the other end of the first resistor R1 and one end of a second inductor L2, the other end of the first inductor L1 is connected with the second port, and the other end of the second inductor L2 is respectively connected with the second capacitor C2 and the third port.
3. The asymmetric Doherty power amplifier based on high power back-off of claim 2, wherein: the carrier input matching network (3-1) and the peak input matching network (4-1) are connected in parallel with the capacitor by utilizing a microstrip line;
the third capacitor C3 is connected with the first inductor L1 in series and then connected with one end of a first ohmic line TL1 and one end of a first microstrip line TL2, the other end of the first microstrip line TL2 is connected with one end of a second microstrip line TL3 and one end of a third microstrip line TL4, the other end of the second microstrip line TL3 is connected with the first capacitor C1, the other end of the third microstrip line TL4 is connected with one end of a fourth microstrip line TL5 and one end of a fifth microstrip line TL6, and the other end of the fourth microstrip line TL5 is connected with the second capacitor C2.
4. The asymmetric Doherty power amplifier based on high power back-off of claim 1, wherein: the carrier output matching network (3-3) is in a stepped impedance transformation line structure.
5. The asymmetric Doherty power amplifier based on high power back-off of claim 1, wherein: the output matching network (4-3) is of a quasi-elliptic filtering structure.
6. The asymmetric Doherty power amplifier based on high power back-off of claim 1, wherein: the carrier power amplifier phase compensation line (2) is a 50 ohm microstrip line.
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