CN113257192A - Pixel circuit and display device - Google Patents
Pixel circuit and display device Download PDFInfo
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- CN113257192A CN113257192A CN202110558796.2A CN202110558796A CN113257192A CN 113257192 A CN113257192 A CN 113257192A CN 202110558796 A CN202110558796 A CN 202110558796A CN 113257192 A CN113257192 A CN 113257192A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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Abstract
The embodiment of the invention discloses a pixel circuit and a display device, wherein the pixel circuit comprises a driving transistor, a data writing module, a compensation module, a first reset module, a storage module and a light-emitting module; and writing data voltage into the grid electrode of the driving transistor through the data writing module, realizing threshold voltage compensation of the driving transistor through the compensation module, and providing driving current for the light-emitting module by the driving transistor according to the grid electrode voltage of the driving transistor so as to drive the light-emitting module to emit light. Compared with the prior art, the compensation module at least comprises a double-gate transistor with a top gate and a bottom gate, and the top gate and the bottom gate simultaneously control the double-gate transistor to be turned off according to respective corresponding scanning signals in a light-emitting stage, so that the electric leakage condition of the driving transistor can be effectively reduced. In addition, the first reset module is connected with the second pole of the driving transistor, so that only one leakage path exists in the driving transistor, the stability of the grid potential of the driving transistor is greatly improved, and the display effect of the display panel is favorably improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a pixel circuit and a display device.
Background
An Organic Light Emitting Diode (OLED) display panel has the characteristics of low power consumption, low production cost, self-luminescence, and the like, and becomes a research hotspot in the current field.
A conventional display panel generally includes a pixel circuit, which includes a driving transistor and a light emitting diode, wherein the driving transistor generates a driving current for driving the light emitting diode to emit light. At present, in the working process of a pixel circuit, the grid of a driving transistor has the problem of unstable electric potential, and the display effect of a display device is influenced.
Disclosure of Invention
Embodiments of the present invention provide a pixel circuit and a display device, so as to improve stability of a gate voltage of a driving transistor, thereby optimizing a display effect of the display device.
In a first aspect, an embodiment of the present invention provides a pixel circuit, including: the device comprises a driving transistor, a data writing module, a compensation module, a first reset module, a storage module and a light emitting module;
the data writing module is connected between a data line and the first pole of the driving transistor and is used for writing a data voltage provided by the data line into the grid electrode of the driving transistor in a data writing stage;
the storage module is connected between the grid electrode of the driving transistor and a first power line and is used for storing the voltage of the grid electrode of the driving transistor;
the compensation module is connected between the grid electrode of the driving transistor and the second electrode of the driving transistor and used for grabbing the threshold voltage of the driving transistor to the grid electrode of the driving transistor and the storage module in the writing stage, the compensation module comprises at least one vertical double-grid transistor, the double-grid transistor comprises a top grid and a bottom grid, and the top grid and the bottom grid are respectively connected with a scanning signal line;
the driving transistor and the light emitting module are connected between the first power line and the second power line, and the driving transistor is used for providing a driving signal to the light emitting module according to the voltage stored by the storage module in a light emitting stage to drive the light emitting module to emit light;
the first reset module is connected between a first reset signal line and the second pole of the driving transistor, and is configured to write a first reset voltage provided by the first reset signal line to the gate of the driving transistor in the data writing phase.
Optionally, before the data writing phase, the top gate and/or the bottom gate receive a turn-on signal, and the first reset voltage is written to the gate of the driving transistor through the first reset module and the compensation module.
Optionally, in the data writing phase, the top gate and/or the bottom gate receive a turn-on signal, and the data voltage is written to the gate of the driving transistor through the data writing module and the compensation module.
Optionally, the compensation module comprises one of the double gate transistors;
the first pole of the double-grid transistor is connected with the second pole of the driving transistor, the second pole of the double-grid transistor is connected with the grid electrode of the driving transistor, the top grid of the double-grid transistor is connected with the first scanning signal line, and the bottom grid of the double-grid transistor is connected with the second scanning signal line.
Optionally, the compensation module comprises at least two of the double gate transistors;
the top gate of each double-gate transistor is connected with a first scanning signal line, the bottom gate of each double-gate transistor is connected with a second scanning signal line,
the first electrode of the first double-grid transistor is connected with the second electrode of the driving transistor, the first electrode of the latter double-grid transistor is connected with the second electrode of the former double-grid transistor, and the second electrode of the last double-grid transistor is connected with the grid electrode of the driving transistor.
Optionally, the first reset module includes a first transistor, the data write module includes a second transistor, the storage module includes a storage capacitor, and the light emitting module includes a light emitting diode;
a gate of the first transistor is connected to a first scan signal line, a first pole of the first transistor is connected to the first reset signal line, and a second pole of the first transistor is connected to the second pole of the driving transistor;
a first pole of the second transistor is connected with the data line, a second pole of the second transistor is connected with a first pole of the driving transistor, and a grid electrode of the second transistor is connected with a second scanning signal line; a first end of the storage capacitor is connected with the first power line, and a second end of the storage capacitor is connected with the grid electrode of the driving transistor;
and the first end of the light-emitting diode is connected with the second pole of the driving transistor, and the second end of the light-emitting diode is connected with the second power line.
Optionally, the first transistor is a single gate transistor.
Optionally, the pixel circuit further includes a light-emitting control module and a second reset module, the second reset module is configured to reset the first end of the light-emitting diode after the data writing phase and before the light-emitting phase, the light-emitting control module includes a third transistor and a fourth transistor, and the second reset module includes a fifth transistor;
a first electrode of the third transistor is connected to the first power supply line, a second electrode of the third transistor is connected to the first electrode of the driving transistor, a first electrode of the fourth transistor is connected to the second electrode of the driving transistor, a second electrode of the fourth transistor is connected to the first end of the light emitting diode, and a gate electrode of the third transistor and a gate electrode of the fourth transistor are both connected to a light emission control signal line;
a first pole of the fifth transistor is connected to the second reset signal line, a second pole of the fifth transistor is connected to the first end of the light emitting diode, and a gate of the fifth transistor is connected to a third scan signal line.
Optionally, the pixel circuit further includes a light emission control module and a second reset module, the second reset module is configured to reset the first end of the light emitting diode during or before the data writing phase, the light emission control module includes a third transistor and a fourth transistor, and the second reset module includes a fifth transistor;
a first electrode of the third transistor is connected to the first power supply line, a second electrode of the third transistor is connected to the first electrode of the driving transistor, a first electrode of the fourth transistor is connected to the second electrode of the driving transistor, a second electrode of the fourth transistor is connected to the first end of the light emitting diode, and a gate electrode of the third transistor and a gate electrode of the fourth transistor are both connected to a light emission control signal line;
a first pole of the fifth transistor is connected to the second reset signal line, a second pole of the fifth transistor is connected to the first end of the light emitting diode, and a gate of the fifth transistor is connected to the first scanning signal line or the second scanning signal line.
In a second aspect, embodiments of the present invention further provide a display device, where the display device includes the pixel circuit provided in any of the embodiments of the present invention.
According to the technical scheme provided by the embodiment of the invention, data voltage is written into the grid electrode of the driving transistor through the data writing module, the threshold voltage compensation of the driving transistor is realized through the compensation module, and the driving transistor provides driving current for the light-emitting module according to the grid electrode voltage of the driving transistor so as to drive the light-emitting module to emit light. The compensation module at least comprises a double-gate transistor with a top gate and a bottom gate, and the top gate and the bottom gate simultaneously control the double-gate transistor to be turned off according to respective corresponding scanning signals in a light-emitting stage, so that the electric leakage condition of the driving transistor can be effectively reduced. In addition, the first reset module is connected to the second pole of the driving transistor, so that the driving transistor only has a leakage path passing through the compensation module, thereby greatly improving the stability of the gate potential of the driving transistor and being beneficial to improving the display effect of the display panel.
Drawings
FIG. 1 is a schematic diagram of a pixel circuit in the prior art;
fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a dual gate transistor according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 7 is a driving timing diagram of a pixel circuit according to an embodiment of the invention;
fig. 8 is a schematic cross-sectional view illustrating a corresponding pixel circuit in a display panel according to an embodiment of the invention;
fig. 9 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 10 is a driving timing diagram of another pixel circuit according to an embodiment of the invention;
fig. 11 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 12 is a driving timing diagram of another pixel circuit according to an embodiment of the invention;
fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the background art, in the pixel circuit in the prior art, the gate of the driving transistor has a problem of unstable potential during operation. Because the OLED light emitting device is a current-type driving control device, the current flowing through the light emitting device is provided by the driving transistor, and the output current of the driving transistor is greatly influenced by the potential of the gate thereof, when some switching devices in the pixel circuit have off current to cause a leakage path to exist on the gate of the driving transistor, the potential of the gate of the driving transistor is easily unstable, which causes the display brightness of the light emitting device to change, thereby influencing the display effect. Fig. 1 is a schematic structural diagram of a pixel circuit in the prior art, and a 7T1C pixel circuit is taken as an example for explanation. In the reset phase, the reset voltage Vref is written to the gate of the first transistor Q1 and the anode of the light emitting element D1 through the fourth transistor Q4 and the seventh transistor Q7, respectively, to complete initialization of the light emitting element and the first transistor. In the data writing phase, the voltage Vdata on the data line is written to the gate of the first transistor Q1 through the second transistor Q2, the first transistor Q1, and the third transistor Q3, and the gate voltage thereof is stored by the capacitor C. When the data writing is finished, the first Scan signal Scan1 transits from low level to high level, the gate of the first transistor Q1 leaks current through the third transistor Q3 and the fourth transistor Q4, thereby affecting the stability of the gate potential of the first transistor Q1 and causing abnormal display. In the prior art, the third transistor Q3 and the fourth transistor Q4 are designed to be double-gate transistors (two transistors are connected in series, and the same signal is input to the gate) to reduce the leakage, but the leakage of the gate potential of the first transistor Q1 still exists due to the limitation of the device structure. Or the third transistor Q3 and the fourth transistor Q4 are designed as Indium Gallium Zinc Oxide (IGZO) transistors to reduce the leakage current, but the IGZO transistors occupy a large space and have high cost, which is not favorable for the design of a display panel with high resolution and high pixel density. Therefore, it is necessary to further reduce the gate leakage of the first transistor to improve the display effect.
Based on the above problems, embodiments of the present invention provide a pixel circuit to improve the stability of the gate voltage of the driving transistor, thereby optimizing the display effect of the display panel. Fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, fig. 3 is a schematic structural diagram of a dual-gate transistor according to an embodiment of the present invention, and referring to fig. 2 and fig. 3, the pixel circuit according to an embodiment of the present invention includes a driving transistor Tdrv, a data writing module 110, a compensation module 120, a first reset module 130, a storage module 140, and a light emitting module 150; the data writing module 110 is connected between the data line and the first pole of the driving transistor Tdrv, and is configured to write the data voltage Vdata provided by the data line into the driving transistor Tdrv in the data writing phase.
The memory module 140 is connected between the gate of the driving transistor Tdrv and the first power line, and stores a voltage of the gate of the driving transistor Tdrv.
The compensation module 120 is connected between the Gate of the driving transistor Tdrv and the second pole of the driving transistor Tdrv, and is configured to capture the threshold voltage of the driving transistor Tdrv to the Gate of the driving transistor Tdrv and the memory module 140 during a data writing phase, that is, a threshold compensation phase (threshold compensation occurs during the data writing phase, and thus the data writing phase is also used as the threshold compensation phase), where the compensation module 140 includes at least one vertical double-Gate transistor, and the double-Gate transistor includes a top Gate1 and a bottom Gate2, and the top Gate1 and the bottom Gate2 respectively input different scanning signals.
The driving transistor Tdrv and the light emitting module 150 are connected between the first power line and the second power line, and the driving transistor Tdrv is configured to provide a driving signal to the light emitting module 150 according to the voltage stored in the memory module 140, so as to drive the light emitting module 150 to emit light. The first reset module 130 is connected between the first reset signal line and the second pole of the driving transistor Tdrv, and is configured to write a first reset voltage to the gate of the driving transistor Tdrv before the data writing phase, that is, the first reset phase.
Specifically, the compensation module 120 grabs the threshold voltage of the driving transistor Tdrv to the gate of the driving transistor Tdrv in the threshold compensation phase and stores the threshold voltage in the storage module 140. In the data writing phase, that is, the threshold compensation phase, after the data voltage Vdata on the data line is written into the gate of the driving transistor Tdrv, the voltage of the gate of the driving transistor Tdrv is Vdata + Vth, that is, the voltage stored in the memory module is Vdata + Vth, where Vth is the threshold voltage of the driving transistor Tdrv. Therefore, the driving current flowing through the light emitting module 150 in the light emitting stage is not related to the threshold voltage Vth of the driving transistor in the data writing stage, and the problem of display unevenness caused by the drift of the threshold voltage Vth of the driving transistor Tdrv can be avoided. The double-Gate transistor is in a structure of vertical top Gate1+ bottom Gate 2. As shown in fig. 3, the top Gate1 and the bottom Gate2 of the dual Gate transistor share an active layer (the active layer includes a Source, a Drain and a polysilicon layer PSI), a first insulating layer GI1 is disposed between the active layer and the top Gate1, and a second insulating layer GI2 is disposed between the active layer and the bottom Gate 2. The double Gate transistor can be controlled to be turned on or off by applying an appropriate signal to either the top Gate1 or the bottom Gate 2.
Fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and specifically shows that the compensation module 120 includes a vertical double-gate transistor 121. In conjunction with the pixel circuit shown in fig. 4, the pixel circuit operates at a timing including at least a first reset phase, a data writing phase (i.e., a threshold compensation phase), and a light emitting phase. In the first reset phase, the first Scan signal Scan1 provided by the first Scan signal line controls the first reset module 130 and the top Gate1 of the dual-Gate transistor 121 to be turned on, and the first reset voltage Vref1 is written to the Gate of the driving transistor Tdrv to initialize the Gate potential of the driving transistor Tdrv. In the data writing phase, the data writing module 110 may be turned on in response to the second Scan signal Scan2 of the second Scan signal line, and at the same time, the bottom Gate2 of the dual-Gate transistor 121 is turned on, and after the data writing module 110 is turned on, the data voltage Vdata on the data line is written to the Gate of the driving transistor Tdrv and one end of the memory module 140, which is a process of charging the memory module 140, and after the charging is completed, the data voltage Vdata is stored in the memory module 140, and in the data writing phase, the threshold compensation process is performed at the same time. In the light emitting stage, neither the first Scan signal Scan1 nor the second Scan signal Scan2 can turn on the dual-Gate transistor, and compared with the transistor with the horizontal dual-Gate structure in the prior art, because the top Gate1 and the bottom Gate2 simultaneously control the dual-Gate transistor to turn off, the dual-Gate transistor with the structure of the top Gate1+ the bottom Gate2 has stronger Gate control capability, and thus the leakage current of the compensation module 120 is smaller. In addition, since the first reset module 130 is connected to the second pole of the driving transistor Tdrv, a leakage path of the gate of the driving transistor Tdrv is reduced (only leakage can be caused by the compensation module 120), so that the leakage of the driving transistor Tdrv can be greatly reduced, the gate potential of the driving transistor Tdrv can be kept stable, the influence of the change of the gate potential of the driving transistor Tdrv on the driving current can be reduced, and the light emitting module 150 can emit light stably.
Before the light emitting stage, the light emitting control module 160 may control the light emitting module 150 to be not conducted with the first power line, so as to prevent the light emitting module 150 from emitting light.
According to the technical scheme provided by the embodiment of the invention, data voltage is written into the grid electrode of the driving transistor through the data writing module, the threshold voltage compensation of the driving transistor is realized through the compensation module, and the driving transistor provides driving current for the light-emitting module according to the grid electrode voltage of the driving transistor so as to drive the light-emitting module to emit light. The compensation module at least comprises a vertical double-gate transistor with a top gate and a bottom gate, and the top gate and the bottom gate simultaneously control the double-gate transistor to be turned off according to respective corresponding scanning signals in a light-emitting stage, so that the electric leakage condition of the driving transistor can be effectively reduced. In addition, the first reset module is connected to the second pole of the driving transistor, so that the driving transistor only has a leakage path passing through the compensation module, thereby greatly improving the stability of the gate potential of the driving transistor and being beneficial to improving the display effect of the display panel.
In other embodiments, other Scan signals (not limited to the first Scan signal Scan1 and the second Scan signal Scan2) may be input to the top Gate1 and the bottom Gate2, and the bottom Gate2 may be turned on or the top Gate1 and the bottom Gate2 may be turned on at the same time in the first reset phase and the data write phase.
As an alternative to the embodiment of the present invention, the compensation module 120 may include only one double-gate transistor, such as the pixel circuit shown in fig. 4. With reference to fig. 2 and 4, the compensation module 120 includes a double gate transistor 121; a first Gate of the dual Gate transistor 121 is connected to a second Gate of the driving transistor Tdrv, a second Gate of the dual Gate transistor 121 is connected to a Gate of the driving transistor Tdrv, a top Gate1 of the dual Gate transistor 121 is connected to the first scanning signal line, and a bottom Gate2 of the dual Gate transistor is connected to the second scanning signal line.
In the first reset phase, the top Gate1 inputs a turn-on signal, and the first reset voltage Vref1 is written into the Gate of the driving transistor Tdrv through the first reset module 130 and the compensation module 120. In the threshold compensation phase, the bottom Gate2 inputs a turn-on signal, and the data voltage Vdata on the data line is written into the Gate of the driving transistor Tdrv through the data writing module 110 and the compensation module 120. By inputting different scanning signals to the top Gate1 and the bottom Gate2, the top Gate1 and the bottom Gate2 can be turned on in a time-sharing manner according to actual requirements, which is beneficial to reducing the power consumption of the double-Gate transistor 121.
When the compensation module 120 only includes a first double-gate transistor, the specific operation principle of the pixel circuit can be referred to the above description of the pixel circuit shown in fig. 2, and will not be described herein again.
Fig. 5 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and referring to fig. 5, a compensation module 120 according to an embodiment of the present invention includes at least two dual-gate transistors 121; the top Gate1 of each dual-Gate transistor 121 is connected to a first scanning signal line, the bottom Gate2 of each dual-Gate transistor 121 is connected to a second scanning signal line, the first Gate of the first dual-Gate transistor 121 is connected to the second Gate of the driving transistor Tdrv, the first Gate of the next dual-Gate transistor 121 is connected to the second Gate of the previous dual-Gate transistor 121, and the second Gate of the last dual-Gate transistor 121 is connected to the Gate of the driving transistor Tdrv.
Specifically, the compensation module 120 may further include a plurality of dual-Gate transistors 121, the dual-Gate transistors 121 are connected in series, and a top Gate1 of each dual-Gate transistor 121 is connected to the first scan signal line, and a bottom Gate2 of each dual-Gate transistor is connected to the second scan signal line. The advantage of this arrangement is that, in the light emitting stage, the first Scan signal Scan1 and the second Scan signal Scan2 control the multiple dual-gate transistors 121 to turn off at the same time, so that the leakage current of the compensation module 120 can be better reduced, the leakage current between the gate and the second pole of the driving transistor Tdrv can be better blocked, and the potential stability of the gate of the driving transistor Tdrv can be ensured.
The compensation module 120 includes a dual-gate transistor 121 for example. Fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and fig. 7 is a timing diagram of driving the pixel circuit according to an embodiment of the present invention, and with reference to fig. 3, fig. 6 and fig. 7, on the basis of the above technical solutions, the first reset module 130 includes a first transistor T1, the data write module 110 includes a second transistor T2, the storage module 140 includes a storage capacitor Cs, and the light emitting module 150 includes a light emitting diode OLED; a gate of the first transistor T1 is connected to a first scan signal line, a first pole of the first transistor T1 is connected to a first reset signal line, and a second pole of the first transistor T1 is connected to a second pole of the driving transistor Tdrv; a first pole of the second transistor T2 is connected to the data line, a second pole of the second transistor T2 is connected to the first pole of the driving transistor Tdrv, and a gate of the second transistor T2 is connected to the second scan signal line; a first end of the storage capacitor Cs is connected to the first power supply line, and a second end of the storage capacitor Cs is connected to the gate of the driving transistor Tdrv; a first terminal (i.e., an anode) of the light emitting diode OLED is connected to the second terminal of the driving transistor Tdrv, and a second terminal (i.e., a cathode) of the light emitting diode OLED is connected to the second power line.
Specifically, the first Scan signal line outputs a first Scan signal Scan1, the second Scan signal line outputs a second Scan signal Scan2, the first power line outputs a high power supply voltage ELVDD, and the second power line outputs a low power supply voltage ELVSS. In the present embodiment, the top Gate1 of the dual Gate transistor 121 and the Gate of the first transistor T1 are both connected to the first scan signal line, and the bottom Gate2 of the dual Gate transistor 121 and the Gate of the second transistor T2 are both connected to the second scan signal line. Therefore, in the first reset phase T11, the top Gate1 inputs a turn-on signal, that is, the first Scan signal Scan1 is a turn-on signal, the first transistor T1 and the top Gate1 of the dual-Gate transistor 121 are turned on, and the first reset voltage Vref1 is written into the Gate of the driving transistor Tdrv through the first transistor T1 and the dual-Gate transistor 121. In the threshold compensation stage T2, the first Scan signal Scan1 is an off signal, the second Scan signal Scan2 is an on signal, the second transistor T2 and the bottom Gate2 of the dual-Gate transistor 121 are turned on, and the data voltage Vdata is written to the Gate of the driving transistor Tdrv through the second transistor T2, the driving transistor Tdrv and the dual-Gate transistor 121. In the light emitting stage, the light emitting module 160 is controlled to be turned on to control the light emitting diode OLED to emit light. At this time, the first Scan signal Scan1 and the second Scan signal Scan2 are both off signals, and the dual-gate transistor 121 is controlled to be turned off, so that a leakage path between the gate and the second pole of the driving transistor Tdrv can be cut off more preferably.
In the present embodiment, the first transistor T1 is a single-gate transistor, and compared to a double-gate transistor in the prior art, the layout of the pixel circuit can be reduced in the present embodiment, which is favorable for improving the pixel density of the pixel circuit and the resolution of the display panel.
Fig. 8 is a schematic cross-sectional structure diagram of a corresponding pixel circuit in a display panel according to an embodiment of the present invention, and referring to fig. 6 and 8, on the basis of the above technical solutions, different layers of a top Gate1 and a bottom Gate2 are disposed.
In the present embodiment, the pixel circuits are arranged in the display panel in an array form, the buffer layer 22 is disposed on one side of the substrate 21, the buffer layer 22 can play a role of buffering and isolating water and oxygen, and the impurities on the substrate 21 are prevented from affecting the array substrate, wherein the material of the buffer layer 22 may be silicon oxide. A first metal layer, a first Gate insulating layer 23, an active layer 31, a second Gate insulating layer 24 and a second metal layer are sequentially formed on the buffer layer 22 on the side away from the substrate 21, wherein the first metal layer includes a first Gate 321, the second metal layer includes a second Gate 322 and a third Gate 323, the first Gate 321 may be a bottom Gate2, the second Gate 322 may be a top Gate1, and the third Gate 323 may be a Gate of another single-Gate transistor. The active layer 31 is a polysilicon layer, the active layer 31 may include a channel region, a source region, and a drain region, and the first and second gate insulating layers 23 and 24 are used for isolation between the first and second gate electrodes 321 and 322 and the active layer 31, respectively. A capacitor insulating layer 25 is further disposed on a side of the second gate 322 away from the substrate 21, a third metal layer is further included on a side of the capacitor insulating layer 25 away from the substrate 21, the third metal layer includes a plate of the storage capacitor, and the capacitor insulating layer 25 is used for electrically insulating the second gate 322 from the storage capacitor. The third metal layer further comprises an interlayer insulating layer 26 on the side away from the substrate 21, and the interlayer insulating layer 26 comprises a fourth metal layer on the side away from the substrate 21, wherein the fourth metal layer comprises a first pole 33 and a second pole 34 of the double-gate transistor, the first pole 33 is a source, the second pole 34 is a drain, and the first pole 33 and the second pole 34 are respectively connected with the active layer 31 through vias. The interlayer insulating layer 26 further includes an insulating layer 27 and a fifth metal layer on the substrate-remote side, the fifth metal layer including the first power supply line. The fifth metal layer further includes a planarization layer 28, a light emitting device layer including an anode 141, a light emitting layer 142 and a cathode 143, and a pixel defining layer 29 on a side away from the substrate 20, the pixel defining layer 29 defining a plurality of light emitting devices.
In this embodiment, the thin film transistor 1101 may be a double gate transistor 121, and the thin film transistor 1102 may be a driving transistor Tdrv. The dual-gate transistor 121 is controlled to be turned off by different signals at the same time, so that a leakage path between the gate and the second pole of the driving transistor Tdrv can be cut off better.
As another optional implementation manner of the embodiment of the present invention, referring to fig. 9, on the basis of the above technical solutions, in the pixel circuit provided in the embodiment of the present invention, with reference to fig. 9, the pixel circuit further includes a light emitting control module 160 and a second reset module 170, the second reset module 170 is configured to reset a first end of the light emitting diode after a data writing phase and before a light emitting phase, the light emitting control module 160 includes a third transistor T3 and a fourth transistor T4, and the second reset module 170 includes a fifth transistor T5;
a first pole of the third transistor T3 is connected to the first power line, a second pole of the third transistor T3 is connected to a first pole of the driving transistor Tdrv, a first pole of the fourth transistor T4 is connected to a second pole of the driving transistor Tdrv, a second pole of the fourth transistor T4 is connected to a first end of the light emitting diode OLED, and a gate of the third transistor T3 and a gate of the fourth transistor T4 are both connected to the light emission control signal line;
a first pole of the fifth transistor T5 is connected to the second reset signal line, a second pole of the fifth transistor T5 is connected to the first terminal of the light emitting diode OLED, and a gate of the fifth transistor T5 is connected to the third scan signal line.
Specifically, in the display panel, there are usually a large number of driving transistors Tdrv, and due to the limitation of the manufacturing process, the threshold voltage of each driving transistor Tdrv is different, which easily causes the difference of the driving current output by the driving transistors Tdrv. The dual gate transistor 121 is used to implement threshold voltage compensation of the driving transistor Tdrv to reduce the difference of driving currents, thereby improving the display effect of the display panel. The compensation module 120 adopts a dual-gate transistor 121 with a top-gate and bottom-gate structure, and the dual-gate transistor 121 is controlled to be turned off by the first Scan signal Scan1 and the second Scan signal Scan2 at the same time in the light emitting stage, so that the gate control capability of the dual-gate transistor 121 is stronger, the leakage current of the dual-gate transistor 121 is reduced, and the stability of the gate potential of the driving transistor Tdrv is maintained.
The first transistor T1 and the fifth transistor T5 are used to initialize the driving transistor Tdrv and the light emitting diode OLED, respectively. Here, the reset voltages inputted to the fifth transistor T5 and the first transistor T1 are different, and the scanning signals of the gates thereof are also different, and when the fifth transistor T5 and the first transistor T1 are turned on by the signals on the first scanning signal line and the second scanning signal line, respectively, the first reset voltage Vref1 and the second reset voltage Vref2 are written to the gate of the driving transistor Tdrv and the anode of the light emitting diode OLED, respectively, and the potentials thereof are initialized. The third transistor T3 and the fourth transistor T4 are used for controlling the light emitting diode OLED to emit light, and in the light emitting period, the third transistor T3 and the fourth transistor T4 are turned on in response to the light emitting control signal EM output by the light emitting control signal line, and the driving current generated by the driving transistor Tdrv is output to the anode of the light emitting diode OLED to drive the light emitting diode OLED to emit light. The voltage ELVSS output by the second power line connected to the cathode of the light emitting diode OLED is generally a negative value.
As an alternative implementation manner provided by the embodiment of the present invention, fig. 10 is a driving timing diagram of another pixel circuit provided by the embodiment of the present invention, where the driving timing may be applied to the pixel circuit shown in fig. 9, and the pixel circuit shown in fig. 9 is taken as an example, and the working principle of the pixel circuit provided by the embodiment of the present invention is specifically described with reference to fig. 10. In this embodiment, the transistors in the pixel circuit may be both p-type and n-type. The following embodiments of the present invention will be described with reference to the case where all transistors are p-type transistors.
The working process of the pixel circuit provided by the embodiment of the invention comprises a reset phase t1, a data writing phase t2 and a light-emitting phase t 3.
The reset phase t1 includes a first reset phase t11 and a second reset phase t 12. In the first reset phase T11, the emission control signal EM is at a high level, the third transistor T3 and the fourth transistor T4 are turned off, the second Scan signal Scan2 output from the second Scan signal line and the third Scan signal Scan3 output from the third Scan signal line are both at a high level, the second transistor T2 and the fifth transistor T5 are turned off, the first Scan signal Scan1 output from the first Scan signal line is at a low level, the first transistor T1 and the top Gate1 of the double Gate transistor 121 are turned on, the first reset voltage Vref1 is written to the Gate of the drive transistor Tdrv through the second transistor T2, the drive transistor Tdrv and the double Gate transistor 121, and the potential of the Gate of the drive transistor Tdrv is reset to the potential of the first reset voltage Vref 1.
In the data writing period T2, the emission control signal EM is at a high level, the third transistor T3 and the fourth transistor T4 are turned off, the first Scan signal Scan1 output from the first Scan signal line and the third Scan signal Scan3 output from the third Scan signal line are both at a high level, the first transistor T1 and the fifth transistor T5 are turned off, the second Scan signal Scan2 output from the second Scan signal line is at a low level, and the second transistor T2 and the bottom Gate2 of the dual Gate transistor 121 are turned on. The data voltage Vdata on the data line is written to the driving transistor Tdrv and the storage capacitor Cs through the second transistor T2, the driving transistor Tdrv, and the double gate transistor 121; meanwhile, threshold voltage compensation of the driving transistor Tdrv is achieved through the dual gate transistor 121 during the threshold compensation stage. At this time, the storage capacitor Cs holds the gate potential of the driving transistor Tdrv at Vdata | Vth |.
In the second reset period T12, the emission control signal EM is at a high level, the third transistor T3 and the fourth transistor T4 are turned off, the second Scan signal Scan2 output by the second Scan signal line and the first Scan signal Scan1 output by the first Scan signal line are both at a high level, the first transistor T1, the second transistor T2 and the double-gate transistor 121 are turned off, the third Scan signal Scan3 output by the third Scan signal line is at a low level, the fifth transistor T5 is turned on, the second reset voltage Vref2 is written to the anode of the light emitting diode OLED by the fifth transistor T5, and the potential of the anode of the light emitting diode OLED is reset to the potential of the second reset voltage Vref 2.
In the light emitting period T3, the light emitting control signal EM is at a low level, the third transistor T3 and the fourth transistor T4 are turned on, the second Scan signal Scan2 output by the second Scan signal line and the first Scan signal Scan1 output by the first Scan signal line are both at a high level, the first transistor T1, the second transistor T2 and the dual gate transistor 121 are turned off, the third Scan signal Scan3 output by the third Scan signal line is at a high level, the fifth transistor T5 is turned off, a loop between the light emitting diode OLED and the first power line and the second power line is turned on, the driving current generated by the driving transistor Tdrv flows into the anode of the light emitting diode OLED, and the light emitting diode OLED emits light. In the light emitting period t3, neither the first Scan signal Scan1 nor the second Scan signal Scan2 can turn on the dual-Gate transistor, and compared with the transistor with the horizontal dual-Gate structure in the prior art, because the top-Gate 1 and the bottom-Gate 2 simultaneously control the dual-Gate transistor to turn off, the Gate control capability of the dual-Gate transistor with the structure of the top-Gate 1+ the bottom-Gate 2 is stronger, and therefore the leakage current of the compensation module 120 is smaller. In addition, since the first reset module 130 is connected to the second pole of the driving transistor Tdrv, a leakage path of the gate of the driving transistor Tdrv is reduced (only leakage can be caused by the compensation module 120), so that the leakage of the driving transistor Tdrv can be greatly reduced, the gate potential of the driving transistor Tdrv can be kept stable, the influence of the change of the gate potential of the driving transistor Tdrv on the driving current can be reduced, and the light emitting module 150 can emit light stably.
As another alternative implementation manner of the embodiment of the present invention, fig. 11 is a schematic structural diagram of another pixel circuit provided in the embodiment of the present invention, fig. 12 is a timing diagram of driving the another pixel circuit provided in the embodiment of the present invention, and referring to fig. 11 and fig. 12 on the basis of the above technical solutions, the pixel circuit provided in the embodiment of the present invention further includes a light emission control module 160 and a second reset module 170, the second reset module 170 is used for resetting a first end of the light emitting diode in a data writing phase or before the data writing phase, the light emission control module 160 includes a third transistor T3 and a fourth transistor T4, and the second reset module 170 includes a fifth transistor T5; a first pole of the third transistor T3 is connected to the first power line, a second pole of the third transistor T3 is connected to a first pole of the driving transistor Tdrv, a first pole of the fourth transistor T4 is connected to a second pole of the driving transistor Tdrv, a second pole of the fourth transistor T4 is connected to a first end of the light emitting diode OLED, and a gate of the third transistor T3 and a gate of the fourth transistor T4 are both connected to the light emission control signal line; a first pole of the fifth transistor T5 is connected to the second reset signal line, a second pole of the fifth transistor T5 is connected to the first end of the light emitting diode OLED, and a gate of the fifth transistor T5 is connected to the first scan signal line or the second scan signal line.
Specifically, the gate of the fifth transistor T5 of the pixel circuit shown in fig. 11 is connected to the first scan signal line, that is, in the reset phase T1, the gate of the driving transistor Tdrv and the anode of the light emitting diode OLED are initialized at the same time, which is beneficial to saving the number of scan circuits and thus beneficial to realizing a narrow frame.
According to the technical scheme provided by the embodiment of the invention, data voltage is written into the grid electrode of the driving transistor through the data writing module, the threshold voltage compensation of the driving transistor is realized through the compensation module, and the driving transistor provides driving current for the light-emitting module according to the grid electrode voltage of the driving transistor so as to drive the light-emitting module to emit light. The compensation module at least comprises a double-gate transistor with a top gate and a bottom gate, and the top gate and the bottom gate simultaneously control the double-gate transistor to be turned off according to respective corresponding scanning signals in a light-emitting stage, so that the electric leakage condition of the driving transistor can be effectively reduced, and when the refresh rate of the display panel is low, the power consumption is favorably reduced. In addition, the first reset module is connected to the second pole of the driving transistor, so that the driving transistor only has a leakage path passing through the compensation module, thereby greatly improving the stability of the gate potential of the driving transistor and being beneficial to improving the display effect of the display panel.
The embodiment of the invention also provides a display device which comprises the pixel circuit provided by the embodiment of the invention. Fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present invention. Referring to fig. 13, a display device 200 according to an embodiment of the present invention includes: the display panel 100, the display panel 100 includes the pixel circuit provided by the embodiment of the invention. The display device 200 further includes a scan driving circuit 210, a display driving chip 220, and a plurality of data lines (D1, D2, D3 … …), a plurality of scan lines (S1, S2, S3 … …); the port of the scan driving circuit 210 is electrically connected to the scan line, and the port of the display driving chip 220 is electrically connected to the data line. Fig. 13 exemplarily shows a data voltage Vdata input terminal, a first Scan signal Scan1 input terminal, and a second Scan signal Scan2 input terminal of a pixel circuit corresponding to one pixel. The display device provided by the embodiment of the invention comprises the pixel circuit provided by any embodiment of the invention, so that the display device has the beneficial effects, and the description is omitted.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A pixel circuit, comprising: the device comprises a driving transistor, a data writing module, a compensation module, a first reset module, a storage module and a light emitting module;
the data writing module is connected between a data line and the first pole of the driving transistor and is used for writing a data voltage provided by the data line into the grid electrode of the driving transistor in a data writing stage;
the storage module is connected between the grid electrode of the driving transistor and a first power line and is used for storing the voltage of the grid electrode of the driving transistor;
the compensation module is connected between the grid electrode of the driving transistor and the second electrode of the driving transistor and used for grabbing the threshold voltage of the driving transistor to the grid electrode of the driving transistor and the storage module in the data writing stage, the compensation module comprises at least one vertical double-grid transistor, the double-grid transistor comprises a top grid and a bottom grid, and the top grid and the bottom grid are respectively connected with a scanning signal line;
the driving transistor and the light emitting module are connected between the first power line and the second power line, and the driving transistor is used for providing a driving signal to the light emitting module according to the voltage stored by the storage module in a light emitting stage to drive the light emitting module to emit light;
the first reset module is connected between a first reset signal line and the second pole of the driving transistor, and is configured to write a first reset voltage provided by the first reset signal line to the gate of the driving transistor in the data writing phase.
2. The pixel circuit according to claim 1, wherein before the data writing phase, the top gate and/or the bottom gate receive a turn-on signal, and the first reset voltage is written to the gate of the driving transistor through the first reset block and the compensation block.
3. The pixel circuit according to claim 1, wherein during the data writing phase, the top gate and/or the bottom gate receive a turn-on signal, and the data voltage is written to the gate of the driving transistor through the data writing module and the compensation module.
4. A pixel circuit according to claim 2 or 3, wherein the compensation module comprises one of the double gate transistors;
the first pole of the double-grid transistor is connected with the second pole of the driving transistor, the second pole of the double-grid transistor is connected with the grid electrode of the driving transistor, the top grid of the double-grid transistor is connected with the first scanning signal line, and the bottom grid of the double-grid transistor is connected with the second scanning signal line.
5. The pixel circuit according to claim 2 or 3, wherein the compensation module comprises at least two of the double gate transistors;
the top gate of each double-gate transistor is connected with a first scanning signal line, the bottom gate of each double-gate transistor is connected with a second scanning signal line,
the first electrode of the first double-grid transistor is connected with the second electrode of the driving transistor, the first electrode of the latter double-grid transistor is connected with the second electrode of the former double-grid transistor, and the second electrode of the last double-grid transistor is connected with the grid electrode of the driving transistor.
6. The pixel circuit according to claim 1, wherein the first reset block comprises a first transistor, the data write block comprises a second transistor, the storage block comprises a storage capacitor, and the light emitting block comprises a light emitting diode;
a gate of the first transistor is connected to a first scan signal line, a first pole of the first transistor is connected to the first reset signal line, and a second pole of the first transistor is connected to the second pole of the driving transistor;
a first pole of the second transistor is connected with the data line, a second pole of the second transistor is connected with a first pole of the driving transistor, and a grid electrode of the second transistor is connected with a second scanning signal line; a first end of the storage capacitor is connected with the first power line, and a second end of the storage capacitor is connected with the grid electrode of the driving transistor;
and the first end of the light-emitting diode is connected with the second pole of the driving transistor, and the second end of the light-emitting diode is connected with the second power line.
7. The pixel circuit according to claim 6, wherein the first transistor is a single-gate transistor.
8. The pixel circuit according to claim 6, further comprising a light emission control module and a second reset module, wherein the second reset module is configured to reset the first terminal of the light emitting diode after the data writing phase and before the light emission phase, the light emission control module comprises a third transistor and a fourth transistor, and the second reset module comprises a fifth transistor;
a first electrode of the third transistor is connected to the first power supply line, a second electrode of the third transistor is connected to the first electrode of the driving transistor, a first electrode of the fourth transistor is connected to the second electrode of the driving transistor, a second electrode of the fourth transistor is connected to the first end of the light emitting diode, and a gate electrode of the third transistor and a gate electrode of the fourth transistor are both connected to a light emission control signal line;
a first pole of the fifth transistor is connected to the second reset signal line, a second pole of the fifth transistor is connected to the first end of the light emitting diode, and a gate of the fifth transistor is connected to a third scan signal line.
9. The pixel circuit according to claim 6, further comprising a light emission control module and a second reset module, wherein the second reset module is configured to reset the first terminal of the light emitting diode during or before the data writing phase, the light emission control module comprises a third transistor and a fourth transistor, and the second reset module comprises a fifth transistor;
a first electrode of the third transistor is connected to the first power supply line, a second electrode of the third transistor is connected to the first electrode of the driving transistor, a first electrode of the fourth transistor is connected to the second electrode of the driving transistor, a second electrode of the fourth transistor is connected to the first end of the light emitting diode, and a gate electrode of the third transistor and a gate electrode of the fourth transistor are both connected to a light emission control signal line;
a first pole of the fifth transistor is connected to the second reset signal line, a second pole of the fifth transistor is connected to the first end of the light emitting diode, and a gate of the fifth transistor is connected to the first scanning signal line or the second scanning signal line.
10. A display device comprising the pixel circuit according to any one of claims 1 to 9.
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