CN113241041A

CN113241041A - Apparatus and method for driving display

Info

Publication number: CN113241041A
Application number: CN202110538254.9A
Authority: CN
Inventors: K·R·可劳恩斯; T·P·辛; K·R·阿蒙森; Z·J·辛伯斯基
Original assignee: E Ink Corp
Current assignee: E Ink Corp
Priority date: 2015-09-16
Filing date: 2016-09-16
Publication date: 2021-08-10
Anticipated expiration: 2036-09-16
Also published as: KR102308589B1; CN108028034B; EP3350798C0; EP3350798A1; KR102158965B1; TWI637377B; KR20200110475A; TW201719616A; CN113241041B; EP3350798A4; CN108028034A; JP2018529126A; KR20180030949A; JP6871241B2; HK1247729A1; EP3350798B1; WO2017049020A1; JP2021092821A

Abstract

An apparatus for driving an electro-optic display may comprise: a first switch designed to supply a voltage to the electro-optic display during a first drive phase; a second switch designed to control the voltage during a second driving phase; and a resistor coupled to the first and second switches for controlling a decay rate of the voltage during the second drive phase.

Description

Apparatus and method for driving display

The present application is a divisional application of the chinese invention patent application entitled "apparatus and method for driving a display" with application number 201680053155.9.

Reference to related applications

This application claims the benefit of provisional application serial No. 62/219,606 filed on day 9, 16 of 2015.

This application also relates to U.S. provisional application 62/370,703 filed on 3/8/2016, which in turn relates to U.S. provisional application 62/261,104 filed on 30/11/2015 and U.S. provisional application 62/111,927 filed on 4/2/2015.

The present application further relates to co-pending application serial No. 15/014,236 filed on day 4/2/2015. The entire disclosures of the foregoing applications, as well as all U.S. patents and publications and co-pending applications mentioned below, are also incorporated herein by reference.

Technical Field

The present invention relates to a method for driving a bistable electro-optic display and to an apparatus for use in such a method. More particularly, the present invention relates to a driving method and apparatus for adjusting a gate-on voltage value after an active refresh to reduce transistor degradation associated with voltage stress that may be caused by remnant voltage discharge.

Disclosure of Invention

According to one aspect of the subject matter disclosed herein, an apparatus for driving an electro-optic display may comprise: a first switch designed to supply a voltage to the electro-optic display during a first drive phase; a second switch designed to control the voltage during a second driving phase; and a resistor coupled to the first switch and the second switch for controlling a decay rate of the voltage during the second drive phase. In some embodiments, only one of the first and second switches is engaged during the first and second drive phases. In still other embodiments, both the first and second switches are disengaged during the third drive phase.

Drawings

Various aspects and embodiments of the present application will be described with reference to the following drawings. It should be understood that the drawings are not necessarily drawn to scale. Items appearing in multiple figures are denoted by the same reference numeral in all of the figures in which they appear.

FIG. 1A is a schematic diagram of a simple gate-on voltage circuit for an electro-optic display according to some embodiments.

Fig. 1B is a graph illustrating gate-on voltage versus time during active update and voltage decay phases, including a post-drive discharge phase in which the gate-on voltage decays exponentially to ground, according to some embodiments.

Fig. 1C is a graph illustrating gate-on voltage versus time during an active refresh period and a voltage decay phase having a preferred voltage profile, in accordance with some embodiments.

FIG. 2A is a schematic diagram of a gate-on voltage circuit of an electro-optic display including resistors according to some embodiments.

Fig. 2B is a graphical schematic diagram depicting gate-on voltage over time for the circuit of fig. 2A, according to some embodiments.

FIG. 3A is a schematic diagram of a gate-on voltage circuit of an electro-optic display including resistors and capacitors according to some embodiments.

Fig. 3B is a graphical schematic depicting the gate-on voltage of the circuit of fig. 3A over time, according to some embodiments.

FIG. 4A is a schematic diagram of a gate-on voltage circuit of an electro-optic display including resistors and capacitors according to some embodiments.

Fig. 4B is a graphical schematic diagram depicting gate-on voltage over time for the circuit of fig. 4A, according to some embodiments.

FIG. 5A is a schematic diagram of a gate-on voltage circuit of an electro-optic display including resistors and capacitors according to some embodiments.

FIG. 5B is a schematic diagram of a gate-on voltage circuit of an electro-optic display including resistors and capacitors according to some embodiments.

FIG. 6A is a schematic diagram of a gate-on voltage circuit of an electro-optic display including a plurality of capacitors and resistors, according to some embodiments.

Fig. 6B is a graphical schematic depicting the gate-on voltage of the circuit of fig. 6A over time, according to some embodiments.

FIG. 7 is a schematic diagram of a gate-on voltage circuit of an electro-optic display including a zener diode according to some embodiments.

FIG. 8A is a schematic diagram of a gate-on voltage circuit of an electro-optic display including resistors and capacitors according to some embodiments.

Fig. 8B is a graphical schematic diagram depicting the gate-on voltage of the circuit of fig. 8A over time, according to some embodiments.

Fig. 9 is a graphical illustration of a comparison of the performance of the device shown in fig. 8A with a conventional device.

Fig. 10A is a graph illustrating maximum grayscale tone shift for multiple updates with and without remnant voltage discharge according to some embodiments.

Fig. 10B is a graph illustrating maximum ghost offset for multiple updates with and without residual discharge, according to some embodiments.

Fig. 11A is a graph illustrating maximum grayscale tone shift for multiple updates with residual discharge, without residual discharge, and with residual discharge and negative bias, according to some embodiments.

Fig. 11B is a graph illustrating maximum ghost offsets for multiple updates with residual discharge, without residual discharge, and with residual voltage discharge and reduced charge bias, in accordance with some embodiments.

Fig. 12A is a schematic diagram illustrating a signal-timing diagram of gate voltage versus time, according to some embodiments.

Fig. 12B is a schematic diagram illustrating a signal-timing diagram of voltage versus time, according to some embodiments.

Detailed Description

Term(s) for

An electro-optic display comprises a layer of electro-optic material, the term used herein in its conventional meaning in the imaging arts denoting a material having first and second display states differing in at least one optical characteristic, the material being changed from its first display state to its second display state by application of an electric field to the material. In the displays of the present disclosure, to the extent that the electro-optic medium has a solid outer surface, the electro-optic medium may be solid (such displays may conveniently be referred to hereinafter as "solid electro-optic displays"), but the medium may, and often does, have an internal liquid or gas-filled space. Accordingly, the term "solid electro-optic display" includes encapsulated electrophoretic displays, encapsulated liquid crystal displays, and other types of displays discussed below.

Although the optical property may be a color perceptible to the human eye, it may be another optical property, such as light transmission, reflection, luminescence, or, in the case of a display for machine reading, a false color in the sense of a change in reflectivity of electromagnetic wavelengths outside the visible range. The term "L star" may be used herein and may be denoted by "L x". L has the general CIE definition: l116 (R/R0)1/3-16, where R is reflectance and R0 is standard reflectance value.

The term "grey state" is used herein in its conventional meaning in the imaging art to refer to a state intermediate two extreme optical states of a pixel, and does not necessarily imply a black-white transition between the two extreme states. For example, several of the patents and published applications mentioned below describe electrophoretic displays in which the extreme states are white and dark blue, so that the intermediate "gray state" is effectively pale blue. In fact, as mentioned before, the transition between the two extreme states may not be a color change at all.

The terms "bistable" and "bistable" are used herein in their conventional meaning in the art to refer to displays comprising display elements having first and second display states which differ in at least one optical property such that, after any given element has been driven by an addressing pulse of finite duration to assume either its first or second display state, that state will last at least several times, for example at least four times, the minimum duration of the addressing pulse used to change the state of the display element after the addressing pulse has ended. It is shown in published U.S. patent application No.2002/0180687 that some particle-based electrophoretic displays that support gray scale are stable not only in their extreme black and white states, but also in their intermediate gray states, and so are some other types of electro-optic displays. This type of display is appropriately referred to as "multi-stable" rather than bi-stable, but for convenience the term "bi-stable" may be used herein to encompass bi-stable and multi-stable displays.

The term "remnant voltage" is used herein to refer to a persistent or decaying electric field that may remain in the electro-optic display after the end of an addressing pulse (a voltage pulse used to change the optical state of the electro-optic medium). The decay rate of the remnant voltage of an electro-optic display may become lower as the remnant voltage approaches the threshold value. Even relatively low remnant voltages (e.g., remnant voltages of about 200mV or less) can create artifacts in electro-optic displays, including but not limited to: a shift in the optical state associated with the addressing pulse, a shift in the optical state of the display over time, and/or ghosting.

The remnant voltage applies a "remnant impulse" to the electro-optic medium for a long period of time, and strictly speaking, this remnant impulse, rather than the remnant voltage, may be responsible for the effect on the optical state of the electro-optic display, which is generally believed to be caused by the remnant voltage. Such remnant voltages may cause undesirable effects on the image displayed on the electro-optic display including, but not limited to, the so-called "ghosting" phenomenon in which traces of a previous image remain visible after the display has been overwritten.

The "shift" in the optical state associated with the addressing pulse refers to the situation: wherein a first application of a particular addressing pulse to the electro-optic display results in a first optical state (e.g., a first gray tone) and a subsequent application of the same addressing pulse to the electro-optic display results in a second optical state (e.g., a second gray tone). Since the voltage applied to a pixel of the electro-optic display during the application of the addressing pulse comprises the sum of the remnant voltage and the voltage of the addressing pulse, the remnant voltage may cause a shift in the optical state.

"drift" of the optical state of the display over time refers to the situation: wherein the optical state of the electro-optic display changes when the display is static (e.g. during periods when addressing pulses are not applied to the display). Since the optical state of a pixel may depend on the residual voltage of the pixel, and the residual voltage of the pixel may decay over time, the residual voltage may cause the optical state to drift.

As described above, "ghost" refers to a situation in which: wherein the tracks of the previous image are still visible after the electro-optic display has been overwritten. The residual voltage may cause "edge ghosting", a type of ghost in which the contours (edges) of a portion of the previous image remain visible.

The term "impulse" is used herein in its conventional meaning of the integral of voltage with respect to time in the imaging art. However, some bistable electro-optic media act as charge converters, and for such media an alternative definition of impulse, i.e. the integral of the current with respect to time (which is equal to the total charge applied) may be used. Depending on whether the medium is to be a voltage-time impulse converter or a charge impulse converter, an appropriate impulse definition should be used.

Several types of electro-optic displays are known. One type of electro-optic display is a rotating bichromal member type, such as described in U.S. patent nos. 5,808,783; 5,777,782, respectively; 5,760,761, respectively; 6,054,071, respectively; 6,055,091; 6,097,531, respectively; 6,128,124, respectively; 6,137,467, respectively; and 6,147,791 (although this type of display is commonly referred to as a "rotating bichromal ball" display, the term "rotating bichromal member" is more accurate since in some of the patents mentioned above the rotating members are not spherical). Such displays use a large number of small bodies (which may be, but are not limited to, spherical or cylindrical) with two or more portions having different optical properties, and an internal dipole. These bodies are suspended in liquid-filled cavities within a matrix, the cavities being filled with liquid so that the bodies can rotate freely. The appearance of the display is changed by applying an electric field thereto, thus rotating the body to various positions and changing which parts of the body are seen through the viewing surface. This type of electro-optic medium may be bistable.

Another type of electro-optic display uses an electrochromic medium, such as in the form of a nano-chromic film, that includes an electrode formed at least in part from a semiconducting metal oxide and a plurality of dye molecules attached to the electrode that are capable of reversible color change; see, e.g., Nature1991, 353,737 to O' Regan, B et al; and Information Display, 18(3), 24 of Wood, d. (3 months 2002). See also Bach, U et al adv.mater, 2002,14(11), 845. Such types of nanochromic films are also described in, for example, U.S. patent No.6,301,038, international application publication No. WO 01/27690, and U.S. patent application 2003/0214695. This type of media may be bistable.

Another type of electro-optic display is a particle-based electrophoretic display in which a plurality of charged particles move through a suspending fluid under the influence of an electric field. Some attributes of Electrophoretic Displays are described in U.S. patent No.6,531,997 entitled "Methods for Addressing Electrophoretic Displays," published 3/11 2003, which is incorporated herein in its entirety.

Electrophoretic displays may have the attributes of good brightness and contrast, wide viewing angles, state bistability, and low power consumption compared to liquid crystal displays. Nevertheless, the long-term image quality of some particle-based electrophoretic displays can be problematic. For example, the particles that make up some electrophoretic displays may settle, resulting in an insufficient lifetime for such displays.

As described above, the electrophoretic medium may comprise a suspending fluid. The suspending fluid may be a liquid, but gaseous suspending fluids may be used to produce electrophoretic media; see, for example, Kitamura, T.et al, "electric tuner movement for electronic Paper-like display", IDW Japan, 2001, Paper HCS1-1 and Yamaguchi, Y.et al, "tuner display using insulating Paper charged switchgear", IDW Japan, 2001, Paper AMD 4-4. See also european patent application 1,429,178; 1462847, respectively; and 1,482,354; and international application WO 2004/090626; WO 2004/079442; WO 2004/077140; WO 2004/059379; WO 2004/055586; WO 2004/008239; WO 2004/006006; WO 2004/001498; WO 03/091799; and WO 03/088495. Some gas-based electrophoretic media may be susceptible to the same types of problems as some liquid-based electrophoretic media due to particle settling when the media is used in an orientation that allows settling, such as in a sign in which the media is arranged in a vertical plane. In fact, particle settling is more problematic in some gas-based electrophoretic media than in some liquid-based electrophoretic media, since the lower viscosity of gaseous suspending fluids allows electrophoretic particles to settle more quickly than liquid suspending fluids.

A number of patents and applications assigned to or in the name of the Massachusetts Institute of Technology (MIT), E Ink corporation, E Ink California, LLC, and related companies describe various techniques for use in packaging and microcell electrophoresis and other electro-optic media. An encapsulated electrophoretic medium comprises a number of small capsules, each of which itself comprises an internal phase comprising electrophoretically mobile particles in a fluid medium and capsule walls surrounding the internal phase. Typically, the package itself is held within a polymeric adhesive to form an adhesive layer between two electrodes. In microcell electrophoretic displays, the charged particles and fluid are not encapsulated within microcapsules, but rather are held within a plurality of cavities formed within a carrier medium (typically a polymer film). [ [ hereinafter, the term "microcavity electrophoretic display" may be used for both cover-up and microcell electrophoretic displays. Techniques described in these patents and applications include:

(a) electrophoretic particles, fluids, and fluid additives; see, e.g., U.S. Pat. nos. 7,002,728 and 7,679,814;

(b) a package, an adhesive and a packaging process; see, e.g., U.S. patent No.6,922,276; 7,411,719 ×;

(c) microcell structures, wall materials, and methods of forming microcells; see, e.g., U.S. patent No. 7,072,095 and U.S. patent application publication No. 2014/0065369;

(d) a method for filling and sealing a microcell; see, e.g., U.S. patent No. 7,144,942 and U.S. patent application publication No. 2008/0007815;

(e) films and sub-assemblies comprising electro-optic material; see, e.g., U.S. Pat. nos. 6,982,178; 7,839,564, respectively;

(f) backsheets, adhesive layers, and other auxiliary layers and methods for use in displays; see, e.g., U.S. patents 7,116,318 and 7,535,624;

(g) color formation and color adjustment; see, e.g., U.S. patent nos. 7,075,502 and 7,839,564;

(h) a method for driving a display; see, e.g., U.S. Pat. nos. 5,930,026; 6,445,489, respectively; 6,504,524; 6,512,354, respectively; 6,531,997, respectively; 6,753,999, respectively; 6,825,970, respectively; 6,900,851, respectively; 6,995,550, respectively; 7,012,600; 7,023,420, respectively; 7,034,783, respectively; 7,061,166, respectively; 7,061,662, respectively; 7,116,466, respectively; 7,119,772; 7,177,066, respectively; 7,193,625, respectively; 7,202,847, respectively; 7,242,514, respectively; 7,259,744; 7,304,787, respectively; 7,312,794, respectively; 7,327,511, respectively; 7,408,699, respectively; 7,453,445, respectively; 7,492,339, respectively; 7,528,822, respectively; 7,545,358, respectively; 7,583,251, respectively; 7,602,374, respectively; 7,612,760, respectively; 7,679,599, respectively; 7,679,813, respectively; 7,683,606, respectively; 7,688,297, respectively; 7,729,039, respectively; 7,733,311, respectively; 7,733,335, respectively; 7,787,169, respectively; 7,859,742, respectively; 7,952,557, respectively; 7,956,841, respectively; 7,982,479, respectively; 7,999,787, respectively; 8,077,141, respectively; 8,125,501, respectively; 8,139,050, respectively; 8,174,490, respectively; 8,243,013, respectively; 8,274,472, respectively; 8,289,250, respectively; 8,300,006, respectively; 8,305,341, respectively; 8,314,784, respectively; 8,373,649, respectively; 8,384,658, respectively; 8,456,414, respectively; 8,462,102, respectively; 8,537,105, respectively; 8,558,783, respectively; 8,558,785, respectively; 8,558,786, respectively; 8,558,855, respectively; 8,576,164, respectively; 8,576,259, respectively; 8,593,396, respectively; 8,605,032, respectively; 8,643,595, respectively; 8,665,206, respectively; 8,681,191, respectively; 8,730,153, respectively; 8,810,525, respectively; 8,928,562, respectively; 8,928,641, respectively; 8,976,444, respectively; 9,013,394, respectively; 9,019,197, respectively; 9,019,198, respectively; 9,019,318, respectively; 9,082,352, respectively; 9,171,508, respectively; 9,218,773, respectively; 9,224,338, respectively; 9,224,342, respectively; 9,224,344, respectively; 9,230,492, respectively; 9,251,736, respectively; 9,262,973, respectively; 9,269,311, respectively; 9,299,294, respectively; 9,373,289, respectively; 9,390,066, respectively; 9,390,661, respectively; and 9,412,314; and U.S. patent application publication No. 2003/0102858; 2004/0246562, respectively; 2005/0253777, respectively; 2007/0070032, respectively; 2007/0076289, respectively; 2007/0091418, respectively; 2007/0103427, respectively; 2007/0176912, respectively; 2007/0296452, respectively; 2008/0024429, respectively; 2008/0024482, respectively; 2008/0136774, respectively; 2008/0169821, respectively; 2008/0218471, respectively; 2008/0291129, respectively; 2008/0303780, respectively; 2009/0174651, respectively; 2009/0195568, respectively; 2009/0322721, respectively; 2010/0194733, respectively; 2010/0194789, respectively; 2010/0220121, respectively; 2010/0265561, respectively; 2010/0283804, respectively; 2011/0063314, respectively; 2011/0175875, respectively; 2011/0193840, respectively; 2011/0193841, respectively; 2011/0199671, respectively; 2011/0221740, respectively; 2012/0001957, respectively; 2012/0098740, respectively; 2013/0063333, respectively; 2013/0194250, respectively; 2013/0249782, respectively; 2013/0321278, respectively; 2014/0009817, respectively; 2014/0085355, respectively; 2014/0204012, respectively; 2014/0218277, respectively; 2014/0240210, respectively; 2014/0240373, respectively; 2014/0253425, respectively; 2014/0292830, respectively; 2014/0293398, respectively; 2014/0333685, respectively; 2014/0340734, respectively; 2015/0070744, respectively; 2015/0097877, respectively; 2015/0109283, respectively; 2015/0213749, respectively; 2015/0213765, respectively; 2015/0221257, respectively; 2015/0262255, respectively; 2016/0071465, respectively; 2016/0078820, respectively; 2016/0093253, respectively; 2016/0140910, respectively; and 2016/0180777;

(i) an application for a display; see, e.g., U.S. patent nos. 7,312,784 and 8,009,348; and 9,197,704; and

(j) non-electrophoretic displays, such as U.S. patent No.6,241,921 and U.S. patent application publication No. 2015/0277160; and U.S. patent application publication nos. 2015/0005720 and 2016/0012710.

Many of the above patents and applications recognize that the walls around the discrete microcapsules in an encapsulated electrophoretic medium may be replaced by a continuous phase, resulting in a so-called polymer-dispersed electrophoretic display, wherein the electrophoretic medium comprises a plurality of discrete droplets of an electrophoretic fluid and a continuous phase of a polymeric material, and the discrete droplets of electrophoretic fluid within such a polymer-dispersed electrophoretic display may be considered as packages or microcapsules, even if no discrete encapsulant film is associated with each individual droplet; see, for example, 2002/0131147, supra. Thus, for the purposes of this application, such polymer-dispersed electrophoretic media are considered to be a sub-species of encapsulated electrophoretic media.

A related type of electrophoretic display is the so-called "microcell electrophoretic display". In microcell electrophoretic displays, the charged particles and suspending fluid are not encapsulated within microcapsules, but are held within a plurality of cavities formed within a carrier medium (e.g., a polymer film). See, for example, international application publication No. WO 02/01281 and published U.S. application No. 2002/0075556, both assigned to Sipix Imaging, Inc.

Many of the above-mentioned patents and applications for E Ink and MIT also contemplate microcell electrophoretic displays and polymer dispersed electrophoretic displays. The term "encapsulated electrophoretic display" may refer to all such display types, which may also be collectively referred to as "microcavity electrophoretic display" to generalize the cross-wall morphology.

Another type of electro-optic display is the electro-wetting display developed by Philips and described in Hayes, RA et al, "Video-Speed Electronic Paper Based on electric wetting", Nature, 425,383-385 (2003). Such electrowetting displays can be made bistable as shown in co-pending application serial No. 10/711,802 filed on 6.10.2004.

Other types of electro-optic materials may also be used. Of particular interest, bistable ferroelectric liquid crystal displays (FLCs) are known in the art and exhibit remnant voltage behavior.

Although electrophoretic media may be opaque (because, for example, in many electrophoretic media, the particles substantially block transmission of visible light through the display) and operate in a reflective mode, some electrophoretic displays may be made to operate in a so-called "shutter mode" in which one display state is substantially opaque and one is light-transmissive. See, e.g., U.S. Pat. Nos. 6,130,774 and 6,172,798, U.S. Pat. Nos. 5,872,552; 6,144,361, respectively; 6,271,823, respectively; 6,225,971, respectively; and 6,184,856. Electrophoretic displays (similar to electrophoretic displays but relying on changes in electric field strength) can operate in a similar mode; see U.S. patent No.4,418,346. Other types of electro-optic displays can also operate in a shutter mode.

Encapsulated or microcell electrophoretic displays are not affected by the aggregation and settling failure modes of conventional electrophoretic devices and may provide further advantages such as the ability to print or coat displays on a variety of flexible and rigid substrates. (the use of the term "printing" is intended to include all forms of printing and coating including, but not limited to, pre-metered coatings such as die coating, slot or extrusion coating, slide or layer coating, curtain coating, roll coating such as knife roll coating, forward and reverse roll coating, gravure coating, dip coating, spray coating, meniscus coating, spin coating, brush coating, air knife coating, screen printing processes, electrostatic printing processes, thermal printing processes, ink jet printing processes, electrophoretic deposition, and other similar techniques). Thus, the resulting display may be flexible. In addition, because the display medium can be printed (using various methods), the display itself can be manufactured inexpensively.

The bistable or multistable behavior of particle-based electrophoretic displays and other electro-optic displays exhibiting similar behavior (such displays may be conveniently referred to hereinafter as "impulse-driven displays") is in sharp contrast to liquid crystal displays ("LCDs"). Twisted nematic liquid crystals are not bistable or multistable but act as voltage converters, and therefore the application of a given electric field to a pixel of such a display produces a particular grey level at the pixel, regardless of the grey level previously present at the pixel. Furthermore, the LC display is driven in only one direction (from non-transmissive or "dark" to transmissive or "bright"), and the reverse transition from the brighter to the darker state is achieved by reducing or eliminating the electric field. Furthermore the grey levels of the pixels of LC displays are not sensitive to the polarity of the electric field, only to its amplitude, and in fact commercial LC displays usually reverse the polarity of the drive field at frequent intervals for technical reasons. In contrast, bistable electro-optic displays act, to a first approximation, as impulse converters, so that the final state of a pixel depends not only on the applied electric field and the time at which the field is applied, but also on the state of the pixel before the electric field is applied.

A high resolution display may include individual pixels that can be addressed without interference from adjacent pixels. One way of obtaining such pixels is to provide an array of non-linear elements, such as transistors or diodes, having at least one non-linear element associated with each pixel to produce an "active matrix" display. The addressing or pixel electrode addressing a pixel is connected to a suitable voltage source via an associated non-linear element. When the non-linear element is a transistor, the pixel electrode may be connected to a drain of the transistor, and this arrangement will be assumed in the following description, although it is basically arbitrary, and the pixel electrode may be connected to a source of the transistor. In a high resolution array, pixels may be arranged in a two-dimensional array of rows and columns, such that any particular pixel is uniquely defined by the intersection of a given row and a given column. The sources of all transistors in each column may be connected to a single column electrode, and the gates of all transistors in each row may be connected to a single row electrode; also, the source to row and gate to column assignments can be reversed, if desired.

The display can be written in a row-by-row fashion. The row electrodes are connected to a row driver which can apply a voltage to a selected row electrode to ensure that all transistors in the selected row are conductive, while applying a voltage to all other rows to ensure that all transistors in these non-selected rows remain non-conductive. The column electrodes are connected to a column driver whose voltages placed on the column electrodes are selected to drive the pixels in the selected row to their desired optical states. (the voltages are relative to a common front electrode that may be disposed on the opposite side of the electro-optic medium from the non-linear array and extend across the entire display). After a pre-selection interval called the "line address time", the selected row is deselected, another row is selected, and the voltage on the column driver is changed in order to write the next row of the display.

Discharge of residual voltage

As described in U.S. provisional application 62/111,927 filed on 4/2/2015, which is incorporated herein by reference in its entirety, a preferred embodiment for dissipating the remnant voltage turns on all pixel transistors for an extended time. For example, all pixel transistors are made conductive by introducing a gate line (referred to herein as a "select line") voltage relative to a source line voltage to a value that places the pixel transistors in a relatively non-conductive state (for isolating the source line from the pixel) and in a relatively conductive state, as part of normal active matrix driving.

In some embodiments, specially designed circuitry may provide for addressing all pixels simultaneously. In standard active matrix operation, the select line control circuit typically does not set all gate lines to a value that achieves the above-described on-state of all pixel transistors. A convenient way of achieving this condition is provided by a select line driver chip having input control lines that allow external signals to apply all select line outputs to receive a condition of selected voltages supplied to the select driver to turn on the pixel transistors. By applying the appropriate voltage value to this special input control line, all transistors can be turned on. For example, for a display with n-type pixel transistors, some select drivers have an "Xon" control line input. The gate-on voltage is routed to all select lines by selecting the value of the voltage input to the Xon pin of the select driver. For simplicity, the description of the invention is written for backplanes that employ n-type pixel transistors. In this case, the gate-on voltage is positive. However, for backplanes made of p-type pixel transistors, all of the methods described herein can be employed by inverting all of the voltages described and illustrated in the present invention. In this case, the gate-on voltage will be negative.

The gate-on voltage is an important voltage in order to dissipate the remnant voltage of an electro-optically active matrix display. The application of the gate-on voltage across the entire display is indispensable for "post-drive discharge", which is typically applied at the end of the "active drive phase" (also referred to herein as an "image update" or "active update period"). The "post-drive discharge phase" (also referred to herein as the "remnant voltage discharge phase" or "remnant voltage discharge") is part of the "voltage decay phase", and these terms may be used interchangeably (and are used interchangeably herein) if the post-drive discharge phase is equal to the voltage decay phase.

However, as described in U.S. provisional application 62/219,606 filed on 9, 16, 2015 (the entire contents of which are incorporated herein by reference), holding the pixel transistors in the on state for the extended duration required for residual voltage discharge may result in pixel transistor degradation and/or changes in the optical performance of the display. It would be advantageous to be able to adjust the gate-on voltage value during the post-drive discharge phase to reduce and/or prevent the effect of holding the pixel transistor for an extended duration. The post-drive discharge may be performed after each active update, after a specified number of active updates, after a specified period of time, or upon user request. Furthermore, the post-drive discharge may be interrupted by active refresh, so that the gate-on voltage value may not reach a zero value.

Apparatus and methods for adjusting a gate turn-on voltage value after an active update phase are described.

E/O electricitySeed of Japanese apricot

As described above, prolonged periods of high gate voltage values, such as those experienced during remnant voltage discharge, may cause pixel transistor degradation. Reducing the high gate voltage value and/or accelerating the decay rate for dissipating the remnant voltage during the remnant voltage discharge may reduce or prevent pixel transistor degradation. The optimum decay rate for dissipating the remnant voltage in the display can be determined empirically by balancing the acceptable level of discharge efficiency and the effect on the transconductance of the pixel transistors. An advantage of the present invention is that post-drive discharge can be achieved at lower voltages that reduce pixel transistor degradation and prevent optical offset.

Various aspects described above, as well as other aspects, will now be described in detail below. It should be understood that these aspects may be used alone, may be used together, or may be used in any combination of two or more kinds as long as they are not mutually exclusive.

Electro-optic displays may receive power from external electronic devices (e.g., a display controller) and supply voltage from "power management" circuitry. The power management circuit may provide a plurality of voltages, including a "gate-on voltage" provided to a gate line (also referred to herein as a "select line") to turn on the transistor on the selected line. The power management circuit may be a discrete component or an integrated circuit (e.g., a power management integrated circuit ("PMIC")). The additional circuitry may include a pull-down resistor and/or a pull-down capacitor.

Figure 1A is a schematic diagram of a simple gate-on voltage circuit for an electro-optic display using a PMIC 102 showing the gate-on voltage line 104 from the PMIC 102 to a gate driver 106 of the active matrix display. The circuit of fig. 1 allows the gate-on voltage 104 at the end of active drive to be controlled by changing the value of the pull-down resistor R108. A high value of R108 will slow down the gate-on voltage decay rate, while a low value of R108 will speed up the gate-on voltage decay rate. Assuming a certain level of capacitive element ("C") (not shown) on line 104 from the PMIC to the gate driver, pull-down resistor ("R") 108 will cause gate pass line 104 to decay exponentially to zero volts with a time constant given by the resistance value ("R") multiplied by the line capacitance ("C"). The voltage decay through the R resistor 108 can be calculated as follows:

V(t)＝V_oe^-t/RC

wherein V₀Is an initial voltage and where the line capacitance C comprises the parasitic capacitance of the voltage line and any capacitance designed as part of the PMIC to stabilize the voltage.

The post-drive discharge method described in the above-referenced U.S. provisional application 62/111,927 utilizes a slow decay of the gate turn-on voltage. During the post-drive discharge phase (which typically occurs after the active refresh phase), the gate-on voltage is allowed to decay, typically through a resistor connected to ground. During the post-drive discharge all active matrix select lines will go to the gate-on voltage, which decays from its value to ground during active display drive.

Fig. 1B is a graph showing gate-on voltage versus time during an active refresh and voltage decay phase, which includes a post-drive discharge phase in which the gate-on voltage decays exponentially to ground. Time t-0 is at the end of the valid update. In fig. 1B, the "discharge after driving" period is defined from time t₁Is started and at time t₂And (6) ending. Time t₁May be as small as zero, in which case the post-drive discharge starts immediately after the refresh, or may be delayed until the gate-on voltage value decays or decreases to a preferred value. Time t₂Is selected to be large enough so that the post-drive discharge is in a sufficiently reduced displayIs effective or, if time allows, until the gate turn-on voltage decays to zero volts.

As mentioned above, it is advantageous to apply a "gate-on" voltage of sufficient magnitude to enable leakage of the pixel remnant voltage, rather than higher, to reduce transistor degradation. Higher than necessary voltage amplitude increases TFT bias stress and is less likely to improve residual voltage leakage. As shown in fig. 1B, the simplest implementation of post-drive discharge is to allow the "gate-on" voltage to decay exponentially during the post-drive discharge. A higher initial voltage value is sufficient to leak the remnant voltage in time, even though a lower later voltage value may be too small to leak the remnant voltage in time. Furthermore, it is advantageous to minimize, but not exceed, the time for all select lines to conduct to achieve sufficient remnant voltage discharge.

The present invention achieves these advantages by controlling the gate-on voltage by shaping the schedule of the gate-on voltage during the post-drive discharge phase. The present invention uses a metric K that is useful for assessing the advantageous properties of the "gate-on" voltage distribution during the post-drive discharge phase:

wherein T is_mIs that the "gate on" voltage starts at the end of the display update and time t until the end of the update₂Low voltage amplitude (V) in the time domain of_L) And high voltage amplitude (V)_H) Total time in between, and T_hIs that the "gate-on" voltage is greater than V_HThe total time of (c). t is t₂Is the time when the discharge ends without being interrupted by other display processes, e.g. the next image update, after driving. Value V_LAnd V_HMay be later defined or bounded based on display performance and usage. Described in more detail below as V_LAnd V_HA value is assigned. The voltages are defined with respect to one another and all with respect to the drive electronics (source)And/or select driver and display controller).

Natural number K (' K)_natural") can be defined as:

wherein V₀Are the "gate-on" voltages (all voltages defined with respect to the "gate-off" voltage for the display in question, as described above) applied during an image update or active update. For convenience, we define normalized K, referred to herein as:

k, K therein_naturalAnd alpha ("α") are both times t₂And a voltage parameter V_LAnd V_HAs a function of (c). Preferred voltage profiles have an alpha greater than 2, an alpha greater than 5 or preferably an alpha greater than 20 and wherein V_LAnd V_HSatisfies at least 2 of the following constraints: 1) v_LIs at least V₀5% of; 2) v_HLess than V ₀80% of; 3) v_HGreater than V_L(ii) a And 4) (V)_H-V_L)/[(V_H+V_L)/2]>0.1. A fourth constraint may be satisfied to ensure V_HAnd V_LIs separated from V_HAnd V_LIs significant compared to the average value of (c).

Fig. 1C is a graph showing gate-on voltage versus time during active refresh and during a voltage decay phase having a preferred voltage profile. The dashed line previously depicted and described in FIG. 1B shows a typical exponential decay after a valid update. The solid line shows an example of a more favorable voltage profile for the post-drive discharge phase, where the gate-on voltage value decays or decreases rapidly to a lower value and then from that decreasing value with the time of the post-drive discharge. As shown in FIG. 1C, the active refresh is completed before all select lines are turned "onThe initial rapid decrease in the subsequent gate turn-on value. Alternatively, all select lines may be turned on when t ═ 0. In another alternative, all select lines may be turned on after the gate turn-on voltage value is initially reduced and has decayed to a desired value or after a predetermined time. After the post-drive discharge effectively reduces charge polarization in the display sufficiently, or alternatively after the gate turn-on voltage decays to zero volts, all select lines may be turned off (t)₂)。

Fig. 2A is a schematic diagram of the simple circuit layout of fig. 1A, further including a "single pole, single throw" switch ("SW 1") 210 (which is "open" as shown) between the PMIC 202 and the gate driver 206. When the SW1 switch 210 is closed, the circuit actively drives the gate driver 206. When the SW1 switch 210 is open (at the end of active drive), the PMIC 202 will cease driving the gate high voltage 206 and the gate-on voltage decay rate will be determined by the various capacitances seen by the pull-down resistor R208 and the gate-on line 204.

FIG. 2B is a graphical illustration depicting the gate-on voltage of the circuit of FIG. 2A over time during the active drive phase 220 when the SW1 switch is closed and the voltage decay phase 222 when the SW1 switch is open.

FIG. 3A is a schematic diagram of a gate-on voltage circuit according to an embodiment of the invention. Figure 3A shows a gate-on voltage line 304 with a first "single pole single throw" switch ("SW 1") 310 from the PMIC 302 to the gate driver 306 of the active matrix display. The circuit also includes a resistor R308, a second "single pole double throw" switch ("SW 2") 312 (which is shown at position "a"), and a pull-down capacitor ("C1") 314.

Switches SW1 and SW2 are programmed to open and close at approximately the same time so that only one switch is engaged at a time. In operation, SW1 is closed and SW2 is open during active display driving, while SW1 is open and SW2 is closed during the voltage decay phase and the post-drive discharge. SW1 is an example of a single pole, single throw switch that is only connected in the closed position. SW2 is an example of a single pole double throw switch that switches between two points, always connecting to either position "a" or position "b".

By incorporating pull-down capacitors C ₁314, and the second switch SW 2312, the gate-on voltage value may decrease to a lower value and then may decay from the decreased voltage value. At the end of active drive, with SW1 open and SW2 in the "b" position, the drive voltage ("V") decay can be calculated according to the following equation:

where C is the line capacitance of the gate pass line 304 and V₀Is the initial voltage.

FIG. 3B is a graphical schematic depicting the gate turn-on voltage of the circuit of FIG. 3A over time during the active drive phase 320 when the SW1 switch is closed and the SW2 switch is in position "a", and during the voltage decay phase 322 when the SW1 switch is open and the SW2 switch is connected to position "B". As shown in fig. 3B, during the active drive phase 320 (when SW1 is closed and SW2 is at position "a"), the PMIC drives the gate driver 306. During the voltage decay phase (when SW1 is open and SW2 is in position "b"), the voltage value is quickly pulled to a smaller voltage value (i.e., V)₀C/(C+C₁) And is controlled by pull-down resistor R308 and capacitances C and C)₁The determined rate decays from the smaller value 322.

FIG. 4A is a schematic diagram of a gate-on voltage circuit according to another embodiment of the invention. Figure 4A shows the gate-on voltage line 404 with the first switch ("SW 1") 410 from the PMIC 402 to the gate driver 406 of the active matrix display. The circuit also includes a resistor R408, a second switch ("SW 2") 412 (which is shown in position "a"), a pull-down capacitor ("C1") 414, and a second pull-down resistor ("R1") 416. Pull-down capacitor C ₁414 and pull-down resistor R ₁416 in series with SW 2412; however, their positions relative to SW2 may be interchanged.

As shown in FIG. 4B, during the active drive phase 420 (when SW1 is closed and SW2 is in position "a"), the PMIC drives the gate driver 406 and couples the capacitor C at the active drive gate-on voltage value ₁414 charging. During the voltage decay phase 422 (when SW1 is on and SW2 is in position "b"), the gate-on voltage value decreases to capacitor C ₁414 and are controlled by resistors R408 and R ₁416, the determined rate decays. Capacitor C₁And resistors R and R₁The addition of (c) allows for greater control over the initial decrease in the value of the gate turn-on voltage and the rate of decay.

FIG. 5A is a schematic diagram of a gate-on voltage circuit equivalent to FIG. 3A according to another embodiment of the present invention. Figure 5A shows the gate-on voltage line 504 with the first switch ("SW 1") 510 from the PMIC 502 to the gate driver 506 of the active matrix display. The circuit also includes a second single pole double throw switch ("SW 2") 512 (which is shown in position "a") on the gate-on voltage line 504. SW 2512 engages pull-down resistor R508 and pull-down capacitor C ₁514. During the active drive phase (as shown in FIG. 3B 320), when SW1 is closed and SW2 is in position "a", capacitor C ₁514 will be charged. During the voltage decay phase (shown in FIG. 3B 322), when SW1 is open and SW2 is in position "B", the voltage value will first drop to capacitor C ₁514, then decays at a rate determined by resistor R508.

Using fig. 5A as an exemplary electrophoretic display, the PMIC may drive a gate-on voltage of +22 volts during the active update phase. During the post-drive discharge phase ("remnant voltage discharge"), the gate-on voltage value of +22 volts is too high, and a reduced gate high voltage value is preferred. In some displays, the remnant voltage discharge may be achieved by using a voltage value of about +8 volts. The preferred circuit of fig. 5A includes a capacitor C sufficient to cause the gate turn-on voltage to rapidly drop to about 10 to 12 volts after the active drive phase₁. Preferred capacitor C when attached to the display (SW2 in position "b") but PMIC is off (SW1 in position "b")₁The value is approximately equal to the capacitance of the gate pass line. Since different displays and drive electronics have different gate-on capacitances, a single capacitance value C₁Will not be applicable to all displays but may be based on the desired initial voltage dropAnd (4) selecting the row. Similar to resistor R508, a single resistor value will not be suitable for all displays, but may be selected based on the desired voltage decay rate.

Fig. 5B is a schematic diagram of a gate-on voltage circuit equivalent to fig. 4A according to another embodiment of the invention. FIG. 5B is a schematic diagram of the circuit of FIG. 5A, further including a pull-down resistor R ₁516. In FIG. 5B, SW 2512 engages pull-down resistor R508, pull-down capacitor C ₁514 and a pull-down resistor R ₁516. During the active drive phase (as shown in FIG. 4B 420), when SW1 is closed and SW2 is in position "a", capacitor C ₁514 will discharge to 0V. During the voltage decay phase (as shown in FIG. 4B 422), when SW1 is open and SW2 is in position "B", the voltage value will first drop to capacitor C ₁514, then by R508 and R ₁516 decay in rate.

FIG. 6A is a schematic diagram of a gate-on voltage circuit according to another embodiment of the invention. Figure 6A shows the gate-on voltage line 604 with the first switch ("SW 1") 610 from the PMIC 602 to the gate driver 606 of the active matrix display. The circuit also includes a pull-down resistor R608, a pull-down capacitor ("C)₁") 614, a second pull-down resistor (" R₁") 618, a second pull-down capacitor (" C)₂") 616 and a second switch (" SW2 ") 612 (" on "as shown) located at resistor R ₁618 and a pull-down capacitor C ₂616 in the middle. Pull-down capacitor C ₁614. Pull-down resistor R ₁618 and a pull-down capacitor C ₂616 are connected in series.

When the PMIC makes the grid conducting line reach V by closing SW1 and opening SW2_oAt home, cross C₁Is raised to V_o*C₂/(C₁+C₂). Selection capacitor C₁And C₂To set the voltage to a desired low level during the post-drive discharge period. Selection resistor R ₁618 to avoid current spikes that the PMIC cannot support, and R₁May be 0 ohm, in which case R₁And is not required. It is also noted herein that R ₁618 and C ₁614 may be swapped. Then, during the post-drive discharge period, SW1 is open and SW2 is closed so that the gate line is now held at a lower voltage, which is passed through resistors R608 and R₁The combined resistance of 618 decays slowly by discharge. The advantages of this alternative embodiment over the previous embodiment are 1) that switch SW2 is a "single pole single throw" switch that can be easily implemented with a transistor, and 2) by selecting a C that is much larger than the other capacitances experienced by gate line 604₁And C₂The desired low voltage can be more easily set substantially independent of the gate line capacitance.

As shown in FIG. 6B, during the active drive phase 620 (when SW1 is closed and SW2 is open), the PMIC drives the gate driver 606 at the gate-on voltage value for active drive and capacitor C is turned on₁And C₂Charging to a voltage value amounting to the "gate on" voltage value. During the voltage decay phase 622 (when SW1 is open and SW2 is closed), the turn-on voltage value drops to across C during active drive₁And then decays from this lower value. Capacitor C₁And C₂And resistors R and R₁Allows for greater control over the initial decrease in the value of the gate turn-on voltage (the amount of time and decrease) and the rate of decay after the initial decrease in value. These values may be set to optimize the reduction of the voltage value during the voltage decay phase, or one or both of these resistors may be removed from the circuit.

FIG. 7 is a schematic diagram of a gate-on voltage circuit according to another embodiment of the invention. Figure 7 shows the gate-on voltage line 704 with a first switch ("SW 1") 710 from the PMIC 702 to the gate driver 706 of the active matrix display. The circuit also includes a second switch ("SW 2") 712 (which is "on" as shown) on the gate-on voltage line 704. SW2712 engages pull-down resistor R708 and zener diode 714. During the discharge phase, when SW1 is open and SW2 is closed, the zener diode quickly drops the gate-on voltage value to a predetermined value (the "breakdown voltage" value described below), and the rate at which the voltage drops to that value is affected by optional resistor R708.

Zener diodes are commercially available diodes that allow current to flow in the forward direction in the same way as an ideal diode, but also allow it to flow in the opposite direction when the voltage is above a certain value ("breakdown voltage"). The zener diodes have different breakdown voltages and may be selected based on the desired breakdown voltage value for a particular display. Zener diodes are non-linear between voltage and current, but their response to voltage and current can be predicted. When the current is high, the zener diode will rapidly reduce the voltage, but once the breakdown voltage is reached, the current will turn off. This is another way to quickly reduce the value of the gate turn-on voltage during the voltage decay phase. It may be desirable to use more than one zener diode instead of one zener diode as shown in figure 7. It is common practice to use a series of two or more zener diodes to achieve the desired voltage above which the series of zener diodes will conduct current. Flexibility in selecting the voltage above which the voltage drops by zener diode conduction can be achieved by using a series of zener diodes. In this case, the effective "breakdown voltage" of such a series of zener diodes is the sum of the "breakdown voltages" of each of the constituent zener diodes.

This circuit has advantages over previous versions. In the previous version, SW2 was a "single pole double throw" switch and relied on capacitance values to achieve the required voltage at the beginning of the post-drive discharge period. In this version, SW2 is a "single pole, single throw" switch, which is much simpler. It uses a zener diode to control the desired voltage, giving more deterministic control of the voltage during the discharge phase than if the voltage were controlled using a capacitor during the discharge phase. The resistors in the figure are optional. We should show this example perhaps, but may also show an example without a resistor or explain an example where the resistance value may be zero.

According to another embodiment of the invention, a power management circuit (e.g., a power management integrated circuit PMIC) may be configured to actively control a gate turn-on voltage. During active update, the gate-on value may be set to allow the pixel to be sufficiently charged to the desired voltage for successful display operation. After active refresh, the gate-on voltage may be set to a reduced value during the post-drive discharge, where the lower magnitude is sufficient to achieve the post-drive discharge. The PMIC manages gate-on voltage control using switches that switch the gate-on voltage output to the display between a voltage for actively driving the display and different voltage values for driving post-discharge. In some embodiments, the switch is internal to the PMIC. In other embodiments, the switches and circuitry are external to the PMIC.

Fig. 8A illustrates yet another embodiment in accordance with the subject matter presented herein. Figure 8A shows a gate-on voltage line 804 coupled to a first switch ("SW 1") 810 from the PMIC to a gate driver 806 of the active matrix display, SW1 coupled to a first voltage source 812, the first voltage source 812 configured to provide a first voltage to the display. Additionally, a second voltage source 816 (typically a low voltage source) may also be coupled to the gate-on voltage line 804 through a second switch ("SW 2") 814 and configured to provide a second voltage to the active-matrix display. In addition, the reference voltage line 804 and the gate driver 806 may connect the capacitor C818 and the resistor R820 in parallel to provide greater control over the decay of the gate-on voltage.

Fig. 8B shows the decay of the gate-on voltage by the circuit configuration shown in fig. 8A. As shown, during active phase 840 (when SW1 is closed and SW2 is in position "a"), the PMIC drives the display with an active drive gate-on voltage value and charges capacitor C818. During the second active phase 842 (when SW1 is in position "b" and SW2 is closed), the PMIC drives the display at the voltage indicated by the second voltage source 816. In this second active phase 842, the display is driven at a voltage level that is close to the voltage value provided by the second voltage source 816 and the capacitor C818 is charged or discharged accordingly relative to the voltage value of the second voltage source 816. Finally, during the discharge phase 844 (when SW1 is in position "b" and SW2 is in position "a"), the gate-on voltage is designed to decay at a rate determined by the combination of capacitor C818 and resistor R820. This configuration allows for a faster initial reduction of the gate turn-on voltage, thereby speeding up the overall decay process and improving device reliability.

In use, as shown in FIG. 9, the configuration shown in FIG. 8A provides better reliability (lines 902 and 904) than some conventional configurations (lines 906 and 908) after a long period of use (e.g., 10 ten thousand updates).

Transistor and typical charge rate/transistor degradation

Thus, in some aspects, the subject matter described herein also provides methods of driving a bistable electro-optic display having a plurality of pixels in an active matrix array. Various types of active matrix transistors commercially available include amorphous silicon, microcrystalline, polycrystalline silicon, organic, and the like. The transistors in an active matrix display are typically designed to support an ON of 1: 1000: OFF ratio, since most active matrix displays have about 1000 rows. For an n-channel ("n-type") amorphous silicon thin film transistor ("a-Si TFT") in an active matrix display, the transistor is in the ON state (row selected) when there is a positive voltage ON the gate to source; when a negative voltage is present on the gate to source, the transistor is in the OFF state. Thus, n-type thin film pixel transistors typically experience a positive to negative charge ratio of 1: 1000. For p-channel ("p-type") a-Si TFTs in active matrix displays, the voltage polarity is reversed. When a negative voltage is present ON the gate to source, the p-type transistor is in an ON state; when a positive voltage is present on the gate to source, the p-type transistor is in the OFF state. Thus, p-type thin film pixel transistors typically experience a negative to positive charge ratio of 1: 1000. When ON: when the OFF ratio is changed so that the transistors are ON more frequently than the normal ratio, the transistors may degrade and adversely affect the optical performance of the display. Amorphous silicon transistors are very susceptible to degradation due to atypical charge biasing. One method for reducing this type of transistor degradation is by turning the transistor to its OFF position, thus ON: the OFF ratio will be closer to its typical value of 1:1000 to normalize ON: OFF ratio, as described more fully herein.

It will be appreciated that typical ON of active matrix displays: the OFF ratio may be different than the 1:1000 ratio and the aspects of the invention described herein still apply.

Charge biasing based on reducing remnant voltage of electro-optic display

According to the techniques disclosed herein and as more fully disclosed in U.S. provisional application 62/111,927 filed on 4.2.2015 (the entire contents of which are incorporated herein by reference), charge biasing may occur when the remnant voltage is discharged from the electro-optic display. The remaining voltage of a pixel of an electro-optic display may be discharged by activating the transistors of the pixel (i.e., turning all transistors ON) and setting the voltages of the front and back electrodes of the pixel to approximately the same value for a period of time. The amount of residual voltage discharged by the pixel during the residual voltage discharge pulse may depend, at least in part, on the rate at which the pixel discharges the residual voltage and the duration of the residual voltage discharge pulse. In some embodiments, the duration of time during which the residual voltage discharge pulse is applied (in the ON position) may be at least 50ms, at least 100ms, at least 300ms, at least 500ms, at least 1 second, or any other suitable duration

For example, all pixel transistors may be made conductive by bringing the gate line voltage relative to the source line voltage to a value that places the pixel transistors in their relatively conductive state compared to the non-conductive state used to isolate the pixels from the source lines (as part of conventional active matrix driving). For an n-type thin film pixel transistor this can be achieved by making the gate line reach a value significantly higher than the source line voltage value. For a p-type thin film pixel transistor this can be achieved by bringing the gate line to a value substantially lower than the source line voltage value. In an alternative embodiment, all pixel transistors may be turned on by making the gate line voltage zero and the source line voltage a negative (or positive for p-type transistors) voltage.

Alternatively, specially designed circuitry may provide for addressing all pixels simultaneously. In standard active matrix operation, the select line control circuit typically does not bring all gate lines to a value that achieves the above-described on-state of all pixel transistors. A convenient way of achieving this condition is provided by a select line driver chip having input control lines that allow external signals to apply all select line outputs to receive a condition of voltage supplied to the select driver to turn on the pixel transistors. By applying the appropriate voltage value to this special input control line, all transistors can be turned on. For example, for a display with n-type pixel transistors, some select drivers have an "Xon" control line input. By selecting the voltage value input to the Xon pin of the select driver, the "gate high" voltage is routed to all select lines and turns all transistors to the ON state.

When the remnant voltage is dissipated using these techniques, the positive-to-negative charge ratio experienced by, for example, an n-type transistor may vary from about 1:1000 to about 1:10 or even 1: 1. Such atypical charge biasing may cause transistor degradation and reduced display performance. As atypical charge biasing and transistor degradation increase, the current and voltage ("IV") curve of the display shifts in value over time. If the IV curve shifts to a higher value, more voltage is required to activate the transistor switch. The effect of the shift in the IV curve can be shown by optically measuring the resulting grayscale tone shift and ghost shift showing reflectance (measured in L star values (L)).

Gray tone shift/ghost shift

Typically 256 transitions are defined that switch the display from the 16 possible grey states currently on the display (including extreme black and extreme white) to the same grey state in the next image to be displayed. The grayscale tone shift measures 16 of these transitions. Ghost offsets measure the properties of the remaining 240 transformations.

The grayscale tone arrangement ("GTP") measures the optical states resulting from applying 16 transitions to all possible grayscale tones (including black and white) when starting from a white image. As shown in fig. 1A, the grayscale tone placement offset is the absolute value of the maximum L x offset over 16 grayscale tones at time k, which may be defined by the number of sequences minus the grayscale tone offset at time zero. The GTP shift (also referred to herein as the grayscale tone shift) may be calculated using the following formula: GTP shift (k) ═ max | (GTP (k) -GTP (0)) |, where GTP (0) is the initial GTP, and GTP (k) is the GTP measurement at time k. GTP offset is an absolute measurement of 16 transitions.

The ghosting measures the remaining 240 transitions from all possible 16 gray shades except white to all possible 16 gray shades and subtracts the GTP value for the final displayed gray shade. That is, the ghost measurement compares the optical state when a gray tone transitions from a non-white gray tone with the optical state when the same gray tone transitions from white. As shown in fig. 1B, the ghost offset is the absolute value of the maximum ghost at time k, which may be defined by the number of sequences minus the ghost at time zero. The ghost offset can be calculated using the following equation: GHOST shift (k) ═ max | (GHOST (k) -GHOST (0)) |, where GHOST (0) is the initial GHOST measurement, and GHOST (k) is the GHOST measurement at time k. Ghost offsets are relative measures based on GTP values.

Before measuring the GTP offset and the ghost offset, the display is cleared by switching the display from the current state to black, white, as shown in fig. 10A, 10B, 11A, and 11B. However, any display clearing technique may be used so long as it is consistent so that the measurements are comparable.

The various aspects described above, as well as additional aspects, will now be described in detail below. It should be understood that these aspects may be used alone, may be used together, or may be used in any combination of two or more kinds as long as they are not mutually exclusive.

Fig. 10A is a graph illustrating results of accelerated reliability testing at 45 degrees celsius by measuring optical response shifts relative to a maximum absolute gray tone shift of multiple updates with a residual voltage discharge 1002 and without a residual voltage discharge 1004 in accordance with some embodiments. Assume 50,000 updates per year of use. As shown in fig. 10A, the additional ON time experienced by the transistor due to the remnant voltage discharge (atypical charge bias) results in a significant greyscale tone shift of about 2L x after about 100,000 updates (or about two years later).

Fig. 10B is a graph illustrating results of accelerated reliability testing at 45 degrees celsius by measuring optical response offset relative to maximum absolute ghost offset with multiple updates of residual voltage discharge 1006 and no residual voltage discharge 1008 according to some embodiments. Assume 50,000 updates per year of use. As shown in fig. 10B, the additional ON time experienced by the transistor due to the remnant voltage discharge (atypical charge bias) resulted in a significant ghost shift of about 3L after about 100,000 updates (or about two years).

Fig. 11A is a graph illustrating results of accelerated reliability testing at 45 degrees celsius, according to some embodiments, by comparing the voltage versus voltage with residual discharge 1102, without residual discharge 1104, and with residual discharge and normalized ON: the maximum absolute gray tone shift of multiple updates of the OFF ratio 1110 measures the optical response shift. Assume 50,000 updates per year of use. As shown in fig. 11A, the additional ON time experienced by the transistor due to the remnant voltage discharge 1102 (atypical charge bias) results in a significant greyscale tone shift of about 2L after about 100,000 refreshes (or about two years or more) compared to refreshes without discharge 1104. When the update with the remnant voltage discharge is normalized or cancelled by turning the transistor to the OFF position for an additional period 1110, the result of the grayscale tone shift after about 100,000 updates is only about 0.25L compared to the update without the discharge 1104.

Fig. 11B is a graph illustrating results of accelerated reliability testing at 45 degrees celsius, according to some embodiments, by comparing the voltage at rest with discharge 1106, without discharge 1108, and with discharge and standard ON: the maximum absolute ghost offset of the multiple updates of the OFF ratio 1112 measure the optical response offset. Assume 50,000 updates per year of use. As shown in fig. 11B, the transistor experiences additional ON time due to the remnant voltage discharge 1106 (atypical charge bias) resulting in a significant ghost shift of about 3L x after about 100,000 refreshes (or about two years) compared to a refresh without the discharge 1108. When the update with the remaining voltage discharge is normalized or cancelled by transitioning the transistor to the OFF position for an additional period 1112, the result of the ghost shift after approximately 100,000 updates is only approximately 0.75L compared to the update without the discharge 1108.

Fig. 12A is a schematic signal-timing diagram showing gate voltage over time, according to some embodiments. Fig. 12A depicts a timing diagram of applied gate voltages for one optical update, including an active update period 1202 in an active matrix display having n-type transistors-each positive and negative going transition is reflected in a single frame of a series of multiple frames during the active update period, a residual voltage discharge (ON state) period 1204, and an OFF state period. In an n-type transistor, a positive gate voltage is applied to achieve the ON state 1204 and a negative voltage is applied to achieve the OFF state 1206. In one embodiment, the valid update period may be 500ms, the ON period may be 1 second, and the OFF period may be 2 seconds. These periods may vary depending on the display usage and/or the number of optical updates required over a defined period of time (e.g., every minute, every hour, etc.). As shown, a residual voltage discharge pulse (ON state) 1204 operates after active refreshing (i.e., optical refreshing) 302 to leak residual charge. The OFF state operates after the ON state to achieve an ON: OFF ratio. While a 1:1000 ratio may not be achievable, ON approaching a 1:1000 ratio: the OFF ratio (even 1:10) reduces transistor degradation.

Fig. 12B is a schematic signal-timing diagram showing multiple voltages versus time in which the display turns on all transistors simultaneously using Xon connections, according to some embodiments. Fig. 12B depicts a voltage diagram applied over time for one optical update in an active matrix display with n-type transistors, including an active update period 1202, a residual voltage discharge (ON state) period 1204, and an OFF state period. The four voltages shown are a high level gate line voltage ("VDDH") 1212, a low level gate line voltage ("VEE") 1218, a front electrode voltage ("VCOM") 1216, and a Xon voltage 1214. Each voltage has a separate zero voltage axis, depicted as the solid grey line. The voltage above the solid line gray line represents a positive voltage, and the voltage below the solid line gray line represents a negative voltage. In fig. 12B, the overall gate voltage depicted in fig. 12A is a combination of VDDH and VEE voltages. A gate driver output enable voltage ("VGDOE") (not shown) controls which gate voltage (i.e., VEE or VDDH) is applied. The Xon voltage activates all transistors simultaneously when grounded, which turns on all transistors during the discharge period 1204. During the OFF state period 1206, VDDH is grounded and the transistor is subject to an applied VEE (negative voltage), which is controlled to approach zero at the end of the period. By placing the transistor in the OFF position for an additional period, ON: the OFF ratio more closely reflects its typical value of 1: 1000. While maintaining 1:1000 ON: an OFF ratio is preferred, but the ratio is moved to any ON of its typical values: the OFF period (even if it is only 1:10, 1:50, or 1:100) can prevent the transistor from degrading.

The OFF period adds time to each update. Thus, the OFF period may be pre-allocated a certain amount of time, may be determined by the controller based on the frequency of the update, and/or may be interrupted. The OFF period preferably occurs after the ON period, but may occur at other times, including before the active update period. The OFF period may range from 500ms to 4 seconds, preferably from 1 second to 2 seconds. The OFF period may extend to 10 seconds depending on the optical update time and the number of optical updates within a period of time.

Further description of some embodiments

It is to be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. Reference throughout this specification to "one embodiment" or "an embodiment" or "some embodiments" means that a particular feature, structure, material, or characteristic described in connection with the embodiments is included in at least one embodiment, but not necessarily all embodiments. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," or "in some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment.

Throughout this disclosure, the words "comprise," "comprising," and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense unless the context clearly requires otherwise; that is, in the sense of "including, but not limited to". Moreover, the words "herein," "below," "above," "below," and words of similar import refer to this application as a whole and not to any particular portions of this application. When the word "or" is used to reference a list of two or more items, the word encompasses all of the following interpretations of the word: any item in the list; all items in the list; and any combination of items in the list.

Having thus described several aspects of at least one embodiment of this technology, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the technology. Accordingly, the foregoing description and drawings merely provide non-limiting examples.

Claims

1. An apparatus for driving an electro-optic display, comprising:

a first switch configured to engage an electro-optic display and provide a voltage to the electro-optic display during a first drive phase;

a diode having one end connected to the resistor and the other end connected to ground;

a second switch coupled to the diode and the resistor, the second switch configured to switch between a first position and a second position, wherein in the first position the second switch engages the diode and the resistor and connects to the electro-optic display to discharge a voltage, and in the second position the switch disconnects the diode and the resistor from the electro-optic display.

2. The apparatus of claim 1, wherein only one of the first switch and the second switch is engaged during a first or second drive phase.

3. The apparatus of claim 1, wherein the first switch and the second switch are disengaged during a third drive phase.

4. The apparatus of claim 1, wherein the electro-optic display is an electrophoretic display.

5. The apparatus of claim 4, wherein the electrophoretic display comprises an electro-optic material comprising a rotating bichromal member or an electrochromic material.

6. An apparatus for driving an electro-optic display, comprising:

a resistor connected to a capacitor in a parallel configuration, the resistor and the capacitor coupled to an electro-optic display;

a first switch connected to a first voltage source and configured to engage and drive the electro-optic display at a first voltage level during a first drive phase; and

a second switch connected to a second voltage source and configured to engage and drive the electro-optic display at a second voltage level during a second drive phase;

wherein the first and second switches are configured to be disconnected from the respective first and second voltage sources during a third drive phase to discharge a second voltage through the resistor and the capacitor.

7. The apparatus of claim 6, wherein the first switch and the second switch are disengaged during a third drive phase.

8. The apparatus of claim 6, wherein the first switch and the second switch are disengaged during a third drive phase.

9. The apparatus of claim 6, wherein the electro-optic display is an electrophoretic display.

10. The apparatus of claim 9, wherein the electrophoretic display comprises an electro-optic material comprising a rotating bichromal member or an electrochromic material.