CN113223439A

CN113223439A - Display panel

Info

Publication number: CN113223439A
Application number: CN202110509753.5A
Authority: CN
Inventors: 纪宏宪; 黄圣淼; 黄郁升
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2020-11-19
Filing date: 2021-05-11
Publication date: 2021-08-06
Anticipated expiration: 2041-05-11
Also published as: TW202221675A; CN113223439B; TWI753660B

Abstract

A display panel is provided. The display panel includes a driving circuit, a first pixel, and a second pixel. The driving circuit has a driving end for generating a driving current according to the mode selection signal and a voltage at the driving end. The first pixel includes a plurality of first sub-pixels. The second pixel is adjacent to the first pixel and comprises a plurality of second sub-pixels. When the mode selection signal indicates the power-saving display mode, at least one first selected sub-pixel in the first pixels is lighted, at least one second selected sub-pixel in the second pixels is lighted, and the display wavelength of the at least one first selected sub-pixel is different from the display wavelength of the at least one second selected sub-pixel.

Description

Display panel

Technical Field

The present invention relates to a display panel, and more particularly, to a display panel capable of switching display modes and effectively reducing power consumption.

Background

With the rapid development of liquid crystal display panels, panel technologies with low power consumption have become widespread. However, in the application of wearable electronic products and vehicular electronic products, when the power of the battery in the electronic product is about to be exhausted, if the image displayed by the electronic product is still displayed in a normal operation mode (e.g., a high-frequency and high-resolution color display mode), the power consumption of the battery is faster, and the service life of the electronic product is further affected.

In view of the above, it is a key issue of those skilled in the art to adjust the display mode of the display panel according to the power state of the battery to reduce the overall power consumption.

Disclosure of Invention

The invention provides a display panel, which can switch display modes and effectively reduce the whole power consumption.

The invention provides a display panel. The display panel includes a driving circuit, a first pixel, and a second pixel. The driving circuit has a driving end for generating a driving current according to the mode selection signal and a voltage at the driving end. The first pixel includes a plurality of first sub-pixels. The second pixel is adjacent to the first pixel and comprises a plurality of second sub-pixels. When the mode selection signal indicates the power-saving display mode, at least one first selected sub-pixel in the first pixels is lighted, at least one second selected sub-pixel in the second pixels is lighted, and the display wavelength of the at least one first selected sub-pixel is different from the display wavelength of the at least one second selected sub-pixel.

Based on the above, the display panel according to the embodiments of the invention can partially light up the sub-pixels or the light emitting elements in the power saving display mode, so that the sub-pixels or the light emitting elements can only display black or white light. Therefore, the display panel of the invention can effectively reduce the overall power consumption so as to achieve the effect of power saving.

Drawings

Fig. 1 is a schematic diagram of a display panel according to a first embodiment of the invention.

FIG. 2 is a timing diagram of the display panel of FIG. 1 according to one embodiment of the present invention.

FIG. 3 is a timing diagram of the display panel of FIG. 1 according to another embodiment of the present invention.

Fig. 4 is a schematic diagram of a display panel according to a second embodiment of the invention.

Fig. 5 is a schematic diagram of a display panel according to a third embodiment of the invention.

FIG. 6 is a timing diagram of the display panel of FIG. 5 according to the embodiment of the invention.

Fig. 7 is a schematic diagram of a display panel according to a fourth embodiment of the invention.

FIG. 8 is a timing diagram of the display panel of FIG. 7 according to the embodiment of the invention.

Description of reference numerals:

100. 400, 500, 700: display panel

110. 410, 510, 710: driving circuit

111. 411, 511, 711: data write circuit

112. 412, 512, 712: laser circuit

113. 413, 513, 713: initialization circuit

114. 414, 514, 714: voltage holding circuit

415. 515, 715: impedance adjusting circuit

AOD: mode selection signal

A11-A13, A21-A23, A31-A33, A41-A42, A51-A53: control switch

B11, B12, B21: auxiliary switch

BK 1: vertical blanking interval

C11-C13, C21-C23, C31-C33, C41-C42, C51-C53, CD1, CD 2: capacitor with a capacitor element

D11-D13, D21-D23, D31-D33, D41-D42, D51-D53: light emitting element

ELVSS: reference ground voltage

EMG: control signal

ELVDD: supply voltage

EM 1-EM 15: laser control signal

ID: drive current

M1-M9, M21-M35: transistor with a metal gate electrode

MP: driving transistor

PD: drive end

PX 1-PX 5: pixel

RD: read control signal

SP 11-SP 13, SP 21-SP 23, SP 31-SP 33, SP 41-SP 42, SP 51-SP 53: sub-pixel

T1-T5: pixel selection switch

TEM1, TEM 2: laser time interval

T11-T13, T11 '-T13', T21 '-T23': sub laser time interval

TRW 11-TRW 13, TRW 11': initialization time interval

VDATA: data voltage

VBP: operating voltage

VREF: reference voltage

WR: write control signal

Detailed Description

The term "coupled" as used throughout this disclosure, including the claims, may refer to any direct or indirect connection means. For example, if a first device couples (or connects) to a second device, it should be construed that the first device may be directly connected to the second device or the first device may be indirectly connected to the second device through some other device or some connection means. Further, wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts. Elements/components/steps in different embodiments using the same reference numerals or using the same terms may be referred to one another in relation to the description.

Fig. 1 is a schematic diagram of a display panel according to a first embodiment of the invention. Referring to fig. 1, in the present embodiment, a display panel 100 includes a driving circuit 110, pixel selection switches T1-T5, pixels PX 1-PX 5, and auxiliary switches B11, B12, and B21. The display panel 100 may select the corresponding pixels PX1 to PX5 through the pixel selection switches T1 to T5, respectively, to light one sub-pixel of the selected pixels. Further, the pixels PX1 to PX5 of the present embodiment may share the same drive circuit 110.

Regarding the circuit configuration of the drive circuit 110, in the present embodiment, the drive circuit 110 includes a drive transistor MP, a capacitor CD1, a data write circuit 111, a laser circuit 112, an initialization circuit 113, and a voltage holding circuit 114. The first terminal of the driving transistor MP is coupled to the power voltage ELVDD, and the driving terminal PD of the driving transistor MP is coupled to the second terminal of the capacitor CD 1. The driving transistor MP generates a driving current ID according to the voltage at the driving terminal PD based on the power voltage ELVDD.

The data write circuit 111 includes a transistor M1. The first terminal of the transistor M1 is coupled to the data voltage VDATA, the second terminal of the transistor M1 is coupled to the first terminal of the capacitor CD1, and the control terminal of the transistor M1 receives the write control signal WR. The laser circuit 112 includes a transistor M2. The first terminal of the transistor M2 is coupled to the operating voltage VBP, the second terminal of the transistor M2 is coupled to the first terminal of the capacitor CD1, and the control terminal of the transistor M2 receives the control signal EMG.

The initialization circuit 113 includes transistors M3 and M4. The first terminal of the transistor M3 is coupled to the driving terminal PD of the driving transistor MP, the second terminal of the transistor M3 is coupled to the second terminal of the driving transistor MP, and the control terminal of the transistor M3 receives the write control signal WR. The first terminal of the transistor M4 is coupled to the reference voltage VREF, the second terminal of the transistor M4 is coupled to the second terminal of the driving transistor MP, and the control terminal of the transistor M4 receives the read control signal RD.

The voltage holding circuit 114 includes transistors M5, M6, and a capacitor CD 2. The second terminal of the transistor M5 is coupled to the first terminal of the capacitor CD1, and the control terminal of the transistor M5 receives the mode selection signal AOD. The second terminal of the transistor M6 is coupled to the second terminal of the capacitor CD1, and the control terminal of the transistor M6 receives the mode selection signal AOD. The capacitor CD2 is coupled between the first terminal of the transistor M5 and the first terminal of the transistor M6.

In the present embodiment, a control signal generator (not shown) disposed outside the display panel 100 may generate a corresponding mode selection signal AOD to the driving circuit 110 according to the received indication signal. For example, if the indication signal indicates that the power of the battery in the electronic device or the display device is maintained in a normal state (e.g., the power of the battery is higher than or equal to a predetermined threshold), the control signal generator (not shown) may generate the mode selection signal AOD to be disabled (e.g., a high voltage level) to the driving circuit 110, so that the display panel 100 can perform the display operation in the normal display mode.

In contrast, if the indication signal indicates that the power of the battery in the electronic device or the display device is about to be exhausted (e.g., the power of the battery is lower than the predetermined threshold), the control signal generator (not shown) may generate the mode selection signal AOD which is enabled (e.g., at a low voltage level) to the driving circuit 110, so that the display panel 100 may perform the display operation in the power-saving display mode. In other words, the display panel 100 can switch the display mode according to the mode selection signal AOD indicating the normal display mode or the power saving display mode.

Regarding the circuit configurations of the pixel selection switches T1-T5, in the present embodiment, the pixel selection switches T1-T5 are respectively coupled between the driving circuit 110 and the pixels PX 1-PX 5. For example, taking the pixel selection switch T1 as an example, a first terminal of the pixel selection switch T1 is coupled to the driving circuit 110, a second terminal of the pixel selection switch T1 is coupled to the pixel PX1, a control terminal of the pixel selection switch T1 receives the laser control signal EM1, and the arrangement relationship between the remaining pixel selection switches T2 to T5 and the pixels PX2 to PX5 can be similar. The pixel selection switches T2-T5 can be controlled by laser control signals EM 2-EM 5 respectively.

On the other hand, regarding the circuit arrangement of the pixels PX1 to PX5, the pixels PX1 to PX5 include a plurality of sub-pixels SP11 to SP13, SP21 to SP23, SP31 to SP33, SP41 to SP42, and SP 51. The pixel PX2 is adjacent to the pixel PX1, the pixel PX3 is adjacent to the pixel PX2, the pixel PX4 is adjacent to the pixel PX3, and the pixel PX5 is adjacent to the pixel PX 4. For example, in the present embodiment, the pixel PX1 includes 3 sets of sub-pixels SP11 to SP 13; the pixel PX2 includes 3 groups of sub-pixels SP21 to SP 23; the pixel PX3 includes 3 groups of sub-pixels SP31 to SP 33; the pixel PX4 includes 2 groups of sub-pixels SP41 to SP 42; the pixel PX5 includes 1 group of sub-pixels SP 51.

Further, in the pixel PX1 shown in fig. 1, the sub-pixels SP11 to SP13 include control switches a11 to a13, light emitting elements D11 to D13, and capacitors C11 to C13. Taking the sub-pixel SP11 as an example, the sub-pixel SP11 may be composed of a control switch a11, a light emitting element D11 and a capacitor C11.

Specifically, a first terminal of the control switch a11 is coupled to a second terminal of the pixel selection switch T1, and a control terminal of the control switch a11 receives the laser control signal EM 4. An anode terminal of the light emitting device D11 is coupled to the second terminal of the control switch a11 and the first terminal of the capacitor C11, and a cathode terminal of the light emitting device D11 is coupled to the second terminal of the capacitor C11 and the ground reference voltage ELVSS. The circuit configurations of the remaining sub-pixels SP 12-SP 13 can be analogized by referring to the description of the sub-pixel SP11, and thus are not described again. The control switches A12 to A13 in the sub-pixels SP12 to SP13 can be respectively controlled by laser control signals EM5 to EM 6.

On the other hand, in the pixels PX2 to PX5 shown in fig. 1, the sub-pixels SP21 to SP23 include control switches a21 to a23, light emitting elements D21 to D23, and capacitors C21 to C23; the sub-pixels SP 31-SP 33 comprise control switches A31-A33, light-emitting elements D31-D33 and capacitors C31-C33; the sub-pixels SP 41-SP 42 comprise control switches A41-A42, light-emitting elements D41-D42 and capacitors C41-C42; the sub-pixel SP51 includes a control switch a51, a light emitting element D51, and a capacitor C51.

It should be noted that the circuit configurations within the sub-pixels SP 21-SP 23, SP 31-SP 33, SP 41-SP 42, and SP51 can be analogized by referring to the related description of the sub-pixel SP11, and therefore, the description thereof is omitted.

Control switches A21-A23 in the sub-pixels SP 21-SP 23 can be respectively controlled by laser control signals EM 4-EM 6; control switches A31 to A33 in the sub-pixels SP31 to SP33 can be respectively controlled by laser control signals EM4 to EM 6; control switches A41 to A42 in the sub-pixels SP41 to SP42 can be respectively controlled by laser control signals EM5 to EM 6; the control switch a51 in the sub-pixel SP51 may be controlled by the laser control signal EM 6.

Particularly, the Light Emitting elements D11 to D13, D21 to D23, D31 to D33, D41 to D42, and D51 of the present embodiment may be, for example, Organic Light Emitting Diodes (OLEDs), Micro Light Emitting diodes (Micro LEDs), or other Light Emitting elements, which is not limited in the invention. The sub-pixels SP11 to SP13, SP21 to SP23, SP31 to SP33, SP41 to SP42, and SP51 may be sub-pixels corresponding to different display wavelengths (for example, sub-pixels respectively displaying three primary colors of red, green, and blue), and the present embodiment is not limited to the number and the arrangement order of the sub-pixels of the three primary colors of red, green, and blue in the sub-pixels SP11 to SP13, SP21 to SP23, SP31 to SP33, SP41 to SP42, and SP 51. For example, in the present embodiment, the sub-pixels SP11, SP21, SP31 and SP41 may be sub-pixels displaying red, the sub-pixels SP12, SP22, SP32 and SP42 may be sub-pixels displaying green, and the sub-pixels SP13, SP23, SP33 and SP51 may be sub-pixels displaying blue, but the present invention is not limited thereto.

Regarding the circuit configurations of the auxiliary switches B11, B12 and B21, in the present embodiment, a first terminal of the auxiliary switch B11 is coupled to a second terminal of the pixel selection switch T1, a second terminal of the auxiliary switch B11 is coupled to an anode terminal of the light emitting element D11 of the sub-pixel SP11, and the auxiliary switch B11 is controlled by the laser control signal EM 2. The first terminal of the auxiliary switch B12 is coupled to the second terminal of the pixel selection switch T1, the second terminal of the auxiliary switch B12 is coupled to the anode terminal of the light emitting element D12 of the sub-pixel SP12, and the auxiliary switch B12 is controlled by the laser control signal EM 3. The first terminal of the auxiliary switch B21 is coupled to the second terminal of the pixel selection switch T2, the second terminal of the auxiliary switch B21 is coupled to the anode terminal of the light emitting element D23 of the sub-pixel SP23, and the auxiliary switch B21 is controlled by the laser control signal EM 3.

It should be noted that the embodiments of the invention are not limited to the number of the auxiliary switches and the coupling manner shown in fig. 1, and those skilled in the art can set the number of the auxiliary switches and the coupling manner according to the requirement of the display panel 100.

In the present embodiment, the transistors M1 to M6, the driving transistor MP, the pixel selection switches T1 to T5, the control switches a11 to a13, a21 to a23, a31 to a33, a41 to a42, a51, and the auxiliary switches B11, B12, and B21 may be implemented by P-type transistors, but the present invention is not limited thereto.

Referring to fig. 1 and fig. 2 together, fig. 2 is a timing diagram of the display panel 100 according to the embodiment of the invention shown in fig. 1. The upper part of fig. 2 is a timing diagram of the display panel 100 operating in the normal display mode, and the lower part of fig. 2 is a timing diagram of the display panel 100 operating in the power saving display mode.

In the present embodiment, one laser time Interval TEM1 of the display panel 100 can be divided into a plurality of sub-laser time intervals, a plurality of initialization time intervals, and a Vertical blanking Interval (Vertical Blank Interval). For clarity of the drawings, fig. 2 only illustrates the initialization time intervals TRW11 to TRW13, the sub-laser time intervals T11 to T13, and the vertical blanking period BK1 as an example. The plurality of initialization time intervals, the plurality of sub-laser time intervals, and the vertical blanking period in the laser time interval TEM2 continuing to the laser time interval TEM1 can be analogized by referring to the description of the initialization time intervals TRW11 to TRW13, the sub-laser time intervals T11 to T13, and the vertical blanking period BK 1.

Referring to fig. 1 and the upper timing diagram (i.e., the normal display mode) of fig. 2, in the present embodiment, the voltage holding circuit 114 of the driving circuit 110 may be turned off according to the disabled (e.g., high voltage level) mode selection signal AOD. Then, when the display panel 100 operates in the initialization time interval TRW11, the transistors M4 and M3 of the initialization circuit 113 can be turned on sequentially according to the enabled (e.g., low voltage level) read control signal RD and the write control signal WR to provide the reference voltage VREF to the driving terminal PD of the driving transistor MP (or the second terminal of the capacitor CD). At this time, the transistor M1 of the data writing circuit 111 can be turned on according to the write control signal WR being enabled (e.g., low voltage level) to provide the data voltage VDATA to the first terminal of the capacitor CD.

In this regard, the driving circuit 110 may complete the initialization operation for the driving end PD at the initialization time interval TRW 11. It should be noted that in the embodiment, before the display panel 100 performs the operation in each sub-laser time interval, the driving circuit 110 performs an initialization operation to reset the voltage at the driving end PD and provide the corresponding data voltage VDATA. The details of the driving circuit 110 in the initialization time intervals TRW12 and TRW13 can be analogized by referring to the related description of the driving circuit 110 in the initial time interval TRW11, and therefore, the details are not repeated.

Then, when the display panel 100 operates in the sub-laser time interval T11 after the initialization time interval TRW11, the transistor M2 of the laser circuit 112 can be turned on according to the enabled (e.g., low voltage level) control signal EMG to provide the operating voltage VBP to the first terminal of the capacitor CD. At this time, the driving circuit 110 may pull up the voltage level of the driving terminal PD to ELVDD-VTH + VBP-VDATA by the coupling effect of the capacitor CD, where VTH is a threshold voltage of the driving transistor MP.

Further, in the sub-laser interval T11, the laser control signals EM1 and EM4 may be set to an enabled state (e.g., a low voltage level). In this case, the pixel selection switch T1 and the control switch a11 of the sub-pixel SP11 may be turned on according to the laser control signals EM1 and EM4, respectively, and the driving circuit 110 may select to supply the driving current ID to the sub-pixel SP11 to light the light emitting element D11 based on the power supply voltage ELVDD and according to the voltage on the driving terminal PD through the conduction path of the pixel selection switch T1 and the control switch a 11. The gray-scale brightness of the lighted light-emitting element can be adjusted by the voltage level of the data voltage VDATA.

Then, the display panel 100 continues to perform the initialization operation in the initialization time interval TRW12 through the driving circuit 110. Also, in the sub-laser time interval T12 after the initialization time interval TRW12, the laser control signals EM1 and EM5 may be set to an enabled state (e.g., a low voltage level). In this case, the pixel selection switch T1 and the control switch a12 of the sub-pixel SP12 can be turned on according to the laser control signals EM1 and EM5, respectively, and the driving circuit 110 can selectively provide the driving current ID to the sub-pixel SP12 through the conduction paths of the pixel selection switch T1 and the control switch a12 to light the light emitting element D12.

Similarly, after the driving circuit 110 completes the initialization operation in the initialization time interval TRW13, the pixel selection switch T1 and the control switch a13 of the sub-pixel SP13 are turned on according to the enabled (e.g., low voltage level) laser control signals EM1 and EM6 during the sub-laser time interval T13, respectively. Also, the driving circuit 110 can selectively supply the driving current ID to the sub-pixel SP13 through the conduction path of the pixel selection switch T1 and the control switch a13 to light the light emitting element D13.

It should be noted that, in the normal display mode of the present embodiment, the operation modes of the pixel selection switches T2 to T5 and the corresponding pixels PX2 to PX5 in the remaining sub-laser time intervals in the laser time interval TEM1 can be analogized by referring to the description of the pixel selection switch T1 and the corresponding pixels PX1 in the sub-laser time intervals T11 to T13, and therefore, the description thereof is omitted.

Then, when the display panel 100 operates in the vertical blanking period BK1, the read control signal RD, the write control signal WR, the control signal EMG, and the laser control signals EM 1-EM 6 can be set to an disable state (e.g., a high voltage level). In this case, the display panel 100 does not light any one of the sub-pixels in the vertical blank period BK 1. After the display panel 100 completes the vertical blanking period BK1, the display panel 100 continues to operate in the laser time interval TEM2 according to the display mode in the laser time interval TEM 1.

In other words, in the normal display mode of the present embodiment, the display panel 100 may sequentially turn on the sub-pixels SP11 to SP13, SP21 to SP23, SP31 to SP33, SP41 to SP42, and SP51 one by one in the laser time interval TEM1, and only one sub-pixel may be turned on in one sub-laser time interval.

On the other hand, referring to fig. 1 and the lower timing diagram of fig. 2 (i.e., the power saving display mode), in the present embodiment, the transistors M5 and M6 of the voltage holding circuit 114 can be turned on according to the mode selection signal AOD being enabled (e.g., at a low voltage level).

It should be noted that, according to the characteristics between the capacitor CD1 and the driving terminal PD of the driving transistor MP, when the display panel 100 operates at a low frequency (i.e., the power saving display mode) and the capacitance of the capacitor CD1 is too small, the voltage variation rate at the driving terminal PD of the driving transistor MP is increased. In this case, the on state of the driving transistor MP is unstable due to the voltage variation of the driving terminal PD.

Therefore, through the design of the voltage holding circuit 114, when the mode selection signal AOD indicates the power-saving display mode, the driving circuit 110 can connect the capacitor CD2 and the capacitor C1 in the voltage holding circuit 114 in parallel to each other according to the mode selection signal AOD, so as to increase the overall capacitance. Under this design, the driving circuit 110 can maintain the voltage level at the driving terminal PD of the driving transistor MP in the power saving display mode to reduce the voltage variation rate, thereby avoiding the half-on or half-off of the driving transistor MP.

In addition, since the on-resistance of the transistor is relatively small when the transistor is operated in the linear region, the driving transistor MP of the present embodiment can be operated in the linear region in the power-saving display mode to effectively reduce the power consumption of the driving transistor MP.

Referring to fig. 1 and the lower-half timing diagram (i.e., the power saving display mode) of fig. 2 again, in the embodiment, when the display panel 100 operates in the initialization time interval TRW 11', the driving circuit 110 can initialize the driving end PD. For details of the operation of the driving circuit 110 in the initialization time interval TRW 11', reference may be made to the related description of the driving circuit 110 in the initial time interval TRW11 for analogy, and thus, the description thereof is omitted.

In the sub-laser time interval T11 'after the initialization time interval TRW 11', the laser control signals EM1 and EM2 may be set to an enabled state (e.g., a low voltage level). In this case, the pixel selection switch T1 and the auxiliary switch B11 may be turned on according to the laser control signals EM1 and EM2, respectively, and the driving circuit 110 may select to provide the driving current ID to the sub-pixel SP11 to light the light emitting element D11 based on the power supply voltage ELVDD and a conduction path through the pixel selection switch T1 and the auxiliary switch B11 according to the voltage at the driving terminal PD.

Then, in the sub-laser time interval T12 'after the sub-laser time interval T11', the laser control signals EM1 and EM3 may be set to an enabled state (e.g., a low voltage level). In this case, the pixel selection switch T1 and the auxiliary switch B12 can be turned on according to the laser control signals EM1 and EM3, respectively, and the driving circuit 110 can selectively provide the driving current ID to the sub-pixel SP12 through the conduction paths of the pixel selection switch T1 and the auxiliary switch B12 to light the light emitting element D12.

On the other hand, in the sub-lasing time interval T13 'after the sub-lasing time interval T12', the laser control signals EM2 and EM3 may be set to an enabled state (e.g., a low voltage level). In this case, the pixel selection switch T2 and the auxiliary switch B21 can be turned on according to the laser control signals EM2 and EM3, respectively, and the driving circuit 110 can selectively provide the driving current ID to the sub-pixel SP23 through the conduction paths of the pixel selection switch T2 and the auxiliary switch B21 to light the light emitting element D23.

It should be noted that in the power-saving display mode, the driving circuit 110 only performs one initialization operation on the driving terminal PD of the driving transistor MP in the laser time interval TEM1, so that the sub-pixels SP11, SP12, and SP23 all receive the same data voltage VDATA, so that the light-emitting elements D11, D12, and D23 only display black or white light, but not red, green, or blue light, in the power-saving display mode, thereby reducing the power consumption of the display panel 100.

In addition, a clock control signal generator (not shown) disposed outside the display panel 100 may generate the laser control signals EM1 to EM6 to the display panel 100. In the power-saving display mode, the clock control signal generator (not shown) may set the laser control signals EM 4-EM 6 to remain in a disabled state (e.g., a high voltage level). In other words, in the power-saving display mode, the display panel 100 only controls the switches T1 and T2 and the auxiliary switches B11, B12 and B21 and uses the sub-pixels SP11, SP12 and SP23 as the selected sub-pixels according to the laser control signals EM1 to EM3 to sequentially light the corresponding light-emitting elements D11, D12 and D23.

In particular, in the embodiment shown in fig. 2, the clock control signal generator (not shown) may set the operating frequency of the laser control signals EM 1-EM 3 to a first frequency (e.g., 45 hertz (Hz)), but the invention is not limited thereto.

FIG. 3 is a timing diagram of the display panel of FIG. 1 according to another embodiment of the present invention. Referring to fig. 1 and fig. 3, details of the operation of the display panel 100 in the timing diagram (i.e., the normal display mode) of the upper half of fig. 3 can be analogized with reference to the description of the operation of the display panel 100 in the normal display mode mentioned in fig. 1 and fig. 2, and therefore are not repeated.

It should be noted that, unlike the embodiment shown in fig. 2, in the power saving display mode shown in fig. 3, the clock control signal generator (not shown) may adjust the operating frequency of the laser control signals EM 1-EM 3 from the first frequency (e.g., 45Hz) to the second frequency (e.g., 90Hz, but the invention is not limited thereto), so that the light emitting elements D11, D12, and D23 corresponding to the sub-pixels SP11, SP12, and SP23 may repeatedly emit light in the laser time interval TEM 1. Therefore, the present embodiment can effectively reduce the chance of flicker (flicker) of the display panel 100 at a low operating frequency. The second frequency may be greater than the first frequency.

The details of the display panel 100 operating in the initialization time interval TRW11 'and the sub-laser time intervals T11' -T13 'and T21' -T23 'shown in fig. 3 can be analogized by referring to the description of the display panel 100 operating in the initialization time interval TRW 11' and the sub-laser time intervals T11 '-T13' mentioned in fig. 1 and 2, and thus are not described again.

Fig. 4 is a schematic diagram of a display panel according to a second embodiment of the invention. Referring to fig. 4, in the present embodiment, the display panel 400 includes a driving circuit 410, pixel selection switches T1 to T5, pixels PX1 to PX5, and auxiliary switches B11, B12, and B21. The display panel 400 is substantially the same or similar to the display panel 100, wherein the same or similar elements are provided with the same or similar reference numerals. Unlike the embodiment of fig. 1, the driving circuit 410 includes a driving transistor MP, a capacitor CD1, a data writing circuit 411, a laser circuit 412, an initialization circuit 413, a voltage holding circuit 414, and an impedance adjusting circuit 415.

Specifically, in the present embodiment, the impedance adjusting circuit 415 includes transistors M7 to M9. The first terminal of the transistor M7 is coupled to the power supply voltage ELVDD, and the control terminal of the transistor M7 receives the mode selection signal AOD. The first terminal of the transistor M8 is coupled to the driving terminal PD of the driving transistor MP, and the control terminal of the transistor M8 receives the mode selection signal AOD. The first terminal of the transistor M9 is coupled to the second terminal of the transistor M7, the second terminal of the transistor M9 is coupled to the initialization circuit 413, and the control terminal of the transistor M9 is coupled to the second terminal of the transistor M8.

Further, when the mode selection signal AOD is set to an disable state (e.g., a high voltage level) (i.e., the display panel 400 operates in the normal display mode), the impedance adjusting circuit 415 may be turned off according to the mode selection signal AOD. In contrast, when the mode selection signal AOD is set to an enabled state (e.g., a low voltage level) (i.e., the display panel 400 operates in the power saving display mode), the impedance adjusting circuit 415 may be turned on according to the mode selection signal AOD.

For example, when the mode selection signal AOD indicates the power-saving display mode, the transistors M7 and M8 of the impedance adjusting circuit 415 can be turned on according to the mode selection signal AOD, so that the driving transistor MP and the transistor M9 are connected in parallel. In a state where the driving transistor MP and the transistor M9 are connected in parallel, the width of the parallel connected transistors can be effectively increased. Therefore, the impedance adjusting circuit 415 may reduce the resistance of the on-resistance of the driving transistor MP according to the mode selection signal AOD when the width of the driving transistor MP is increased, and thereby further reduce the power consumption of the display panel 400.

It should be noted that, regarding the design of the impedance adjusting circuit 415, the width-to-length ratio of the transistor M9 may be larger than the width-to-length ratio of the transistor M7 and/or the transistor M8, but the present invention is not limited thereto.

On the other hand, the driving transistor MP, the capacitor CD1, the data writing circuit 411, the laser circuit 412, the initialization circuit 413, the voltage holding circuit 414, the pixel selection switches T1 to T5, the pixels PX1 to PX5, and the auxiliary switches B11, B12, and B21 shown in fig. 4 can be analogized by referring to the description of the driving transistor MP, the capacitor CD1, the data writing circuit 111, the laser circuit 112, the initialization circuit 113, the voltage holding circuit 114, the pixel selection switches T1 to T5, the pixels PX1 to PX5, and the auxiliary switches B11, B12, and B21 in the normal display mode and the power saving display mode mentioned in fig. 1 to 3, and thus description thereof is omitted.

Fig. 5 is a schematic diagram of a display panel according to a third embodiment of the invention. Referring to fig. 5, the display panel 500 includes a driving circuit 510 and pixels PX 1-PX 5. In the present embodiment, the driving circuit 510 includes a driving transistor MP, a capacitor CD1, a data writing circuit 511, a laser circuit 512, an initialization circuit 513, a voltage holding circuit 514, and an impedance adjusting circuit 515.

Specifically, in the present embodiment, the laser circuit 512 includes transistors M21 to M35. The transistors M21-M35 may be coupled in parallel between the operating voltage VBP and the first terminal of the capacitor CD1, and the transistors M21-M35 may be controlled by the laser control signals EM 1-EM 15, respectively. It should be noted that the driving circuit 510 shown in fig. 5 can be analogized with the related descriptions of the driving

circuits

110 and 410 mentioned in fig. 1 to fig. 4, and therefore, the description thereof is omitted.

On the other hand, regarding the circuit configuration of the pixels PX1 to PX5, the pixels PX1 to PX5 include a plurality of sub-pixels. For example, in the present embodiment, the pixel PX1 includes 3 sets of sub-pixels SP11 to SP 13; the pixel PX2 includes 3 groups of sub-pixels SP21 to SP 23; the pixel PX5 includes 3 groups of sub-pixels SP51 to SP 53. Specifically, for the sake of clarity of the drawing, the display panel 500 shown in fig. 5 omits 2 groups of pixels between the pixel PX2 and the pixel PX5, wherein, in the omitted 2 groups of pixels, the pixel adjacent to the pixel PX2 and the pixel adjacent to the pixel PX5 both include 3 groups of sub-pixels, and the circuit configuration inside the pixels can be analogized with reference to the related descriptions of the pixels PX1, PX2, and PX5, and therefore, the description thereof is omitted.

Further, in the embodiment of fig. 5, the sub-pixels SP11 to SP13 include control switches a11 to a13, light emitting elements D11 to D13, and capacitors C11 to C13; the sub-pixels SP 21-SP 23 comprise control switches A21-A23, light-emitting elements D21-D23 and capacitors C21-C23; the sub-pixels SP51 to SP53 include control switches a51 to a53, light emitting elements D51 to D53, and capacitors C51 to C53. Wherein the control switches A11-A13 can be respectively controlled by laser control signals EM 1-EM 3; the control switches A21-A23 can be respectively controlled by laser control signals EM 4-EM 6; the control switches A51-A53 can be controlled by laser control signals EM 13-EM 15 respectively.

It should be noted that, regarding the coupling manner of the internal components of each sub-pixel, the analogy can be made with reference to the related description of the sub-pixel SP11 shown in fig. 1, and thus the description is omitted.

Regarding the display mode of the display panel 500, in the present embodiment, when the mode selection signal AOD indicates the normal display mode, the laser control signals EM 1-EM 15 can be sequentially set to an enabled state (e.g., a low voltage level), so that the driving circuit 510 can sequentially light the light emitting elements corresponding to the sub-pixels SP 11-SP 53 one by one. For details of the display panel 500 operating in the normal display mode, the description can be analogized with reference to the related descriptions of fig. 1 to 5, and therefore, the description is omitted.

FIG. 6 is a timing diagram of the display panel of FIG. 5 according to the embodiment of the invention. Referring to fig. 5 and fig. 6, fig. 6 is a timing diagram of the display panel 500 operating in the power saving display mode. In the power-saving display mode, the clock control signal generator (not shown) may set the laser control signals EM 4-EM 15 to remain in a disabled state (e.g., high voltage level), and in the sub-laser time intervals T11 '-T13', the clock control signal generator (not shown) may sequentially enable (e.g., low voltage level) the laser control signals EM 1-EM 3. In other words, in the power-saving display mode, the display panel 500 only controls the switches a 11-a 13 to make the sub-pixels SP 11-SP 13 as the selected sub-pixels according to the laser control signals EM 1-EM 3, so as to sequentially light the corresponding light-emitting elements D11, D12, and D13.

Similar to the embodiment of fig. 1, in the power-saving display mode, since the driving circuit 510 only performs one initialization operation on the driving terminal PD of the driving transistor MP in the laser time interval TEM1, the sub-pixels SP11 to SP13 all receive the same data voltage VDATA, so that the light emitting elements D11, D12 and D13 only display black or white light, but not red, green or blue light, in the power-saving display mode, thereby reducing the power consumption of the display panel 500.

For details of the display panel 500 operating in the power saving display mode, the description can be analogized with reference to the related descriptions of fig. 1 to 5, and thus the details are not repeated.

Fig. 7 is a schematic diagram of a display panel according to a fourth embodiment of the invention. Referring to fig. 7, the display panel 700 includes a driving circuit 710, pixel selection switches T1 to T5, and pixels PX1 to PX 5. In the present embodiment, the driving circuit 710 includes a driving transistor MP, a capacitor CD1, a data writing circuit 711, a laser circuit 712, an initialization circuit 713, a voltage holding circuit 714, and an impedance adjusting circuit 715. It should be noted that the driving circuit 710 shown in fig. 7 can be analogized with the related descriptions of the driving

circuits

On the other hand, regarding the circuit configuration of the pixels PX1 to PX5, the pixels PX1 to PX5 include a plurality of sub-pixels. For example, in the present embodiment, the pixel PX1 includes 5 groups of sub-pixels SP11 to SP 15; the pixel PX2 includes 4 groups of sub-pixels SP21 to SP 24; the pixel PX4 includes 2 groups of sub-pixels SP41 to SP 42; the pixel PX5 includes 1 group of sub-pixels SP 51.

In particular, for the sake of clarity of the drawing, the display panel 700 shown in fig. 7 omits the pixels between the pixel PX2 and the pixel PX4, where the omitted pixels include 3 groups of sub-pixels, and the circuit configuration inside the omitted pixels can be analogized with reference to the description of the pixels PX1, PX2, PX4, and PX5, and therefore, the description thereof is omitted.

In other words, the number of sub-pixels (or light-emitting elements) in the pixels PX1 to PX5 is 5, 4, 3, 2, or 1 in this order. That is, the number of sub-pixels (or light emitting elements) in the pixels PX1 to PX5 is an arithmetic series.

Further, in the embodiment of fig. 7, the sub-pixels SP11 to SP15 include control switches a11 to a15, light emitting elements D11 to D15, and capacitors C11 to C15; the sub-pixels SP 21-SP 24 comprise control switches A21-A24, light-emitting elements D21-D24 and capacitors C21-C24; the sub-pixels SP 41-SP 42 comprise control switches A41-A42, light-emitting elements D41-D42 and capacitors C41-C42; the sub-pixel SP51 includes a control switch a51, a light emitting element D51, and a capacitor C51.

Wherein, the pixel selection switches T1-T5 can be respectively controlled by laser control signals EM 1-EM 5; the control switches A11-A15 can be respectively controlled by laser control signals EM 2-EM 6; the control switches A21-A24 can be respectively controlled by laser control signals EM 3-EM 6; the control switches A41-A42 can be respectively controlled by laser control signals EM 5-EM 6; control switch a51 may be controlled by laser control signal EM 6.

Regarding the display mode of the display panel 700, in the embodiment, when the mode selection signal AOD indicates the normal display mode, the pixel selection switches T1 to T5 and the control switches a11 to a51 of the display panel 700 can sequentially turn on the light emitting elements corresponding to the sub-pixels SP11 to SP51 one by one according to the laser control signals EM1 to EM 5. Accordingly, details of the display panel 700 operating in the normal display mode can be analogized with reference to the related descriptions of fig. 1 to 5, and thus are not described again.

FIG. 8 is a timing diagram of the display panel of FIG. 7 according to the embodiment of the invention. Referring to fig. 7 and fig. 8, fig. 8 is a timing diagram of the display panel 700 operating in the power saving display mode. In the power saving display mode, the laser control signals EM1 and EM2 may be set to an enabled state (e.g., a low voltage level) when the display panel 700 operates in the sub-laser time interval T11 'after the initialization time interval TRW 11'.

In this case, the pixel selection switch T1 and the control switch a11 may be turned on according to the laser control signals EM1 and EM2, respectively, and the driving circuit 110 may select to provide the driving current ID to the sub-pixel SP11 to light the light emitting element D11 based on the power supply voltage ELVDD and the voltage on the driving terminal PD through the conduction path of the pixel selection switch T1 and the control switch a 11.

Then, in the sub-laser time interval T12 'after the sub-laser time interval T11', the laser control signals EM1 and EM3 may be set to an enabled state (e.g., a low voltage level). In this case, the pixel selection switch T1 and the control switch a12 can be turned on according to the laser control signals EM1 and EM3, respectively, and the driving circuit 110 can selectively provide the driving current ID to the sub-pixel SP12 through the conduction paths of the pixel selection switch T1 and the control switch a12 to light the light emitting element D12.

On the other hand, in the sub-lasing time interval T13 'after the sub-lasing time interval T12', the laser control signals EM2 and EM3 may be set to an enabled state (e.g., a low voltage level). In this case, the pixel selection switch T2 and the control switch a21 can be turned on according to the laser control signals EM2 and EM3, respectively, and the driving circuit 110 can selectively provide the driving current ID to the sub-pixel SP21 through the conduction paths of the pixel selection switch T2 and the control switch a21 to light the light emitting element D21.

In other words, in the power-saving display mode, the display panel 700 only uses the sub-pixels SP11, SP12 and SP21 as the selected sub-pixels according to the laser control signals EM1 to EM3 through the pixel selection switches T1 and T2 and the control switches a11, a12 and a21, so as to sequentially light the corresponding light-emitting elements D11, D12 and D21.

Similar to the embodiment of fig. 1, in the power-saving display mode, since the driving circuit 710 only performs one initialization operation on the driving terminal PD of the driving transistor MP in the laser time interval TEM1, the sub-pixels SP11, SP12, and SP21 all receive the same data voltage VDATA, so that the light-emitting elements D11, D12, and D21 only display black or white light, but not red, green, or blue light, in the power-saving display mode, thereby reducing the power consumption of the display panel 700.

As can be seen from the above descriptions of the embodiments in fig. 1 to fig. 8, when the display panel operates in the normal display mode, the display panel can select the sub-pixels or the light emitting elements that need to emit light according to the timing state of the laser control signal, so that the driving circuit can sequentially light the sub-pixels or the light emitting elements in each pixel one by one, and the light emitting time of the sub-pixels adjacent to each other can not completely overlap. In addition, since the display panel does not need to perform the circuit switching operation through an additional multiplexer or excessive laser control lines, and each pixel can share the same driving circuit, the embodiments of fig. 1 to 8 can effectively increase the layout space of the display panel.

In addition, the embodiments of fig. 1 to 8 can also relatively increase the size of the driving transistor while increasing the layout space of the display panel, so that the driving transistor can generate a larger driving current to the lighted sub-pixel or light emitting element. Therefore, the sub-pixels or light emitting elements of the embodiments of fig. 1 to 8 can operate at the best efficiency point, thereby improving the display quality.

On the other hand, when the display panel operates in the power saving display mode, the driving circuit can maintain the voltage level at the driving end of the driving transistor through the voltage holding circuit to reduce the voltage change rate at the driving end, thereby avoiding the half-on or half-off of the driving transistor under low frequency operation. In addition, the driving circuit can also reduce the resistance value of the on resistance of the driving transistor through the impedance adjusting circuit. In the power-saving display mode, the display panel can partially light up some sub-pixels or light-emitting elements, and make these sub-pixels or light-emitting elements only display black or white bright light. Therefore, the display panel of the invention can effectively reduce the overall power consumption so as to achieve the effect of power saving.

In summary, the driving circuit of the display panel according to the embodiments of the invention can maintain the voltage level at the driving end of the driving transistor through the voltage holding circuit in the power saving display mode to reduce the voltage variation rate at the driving end, thereby stabilizing the on state of the driving transistor when the driving transistor operates at a low frequency. In addition, the driving circuit can also reduce the resistance value of the on resistance of the driving transistor through the impedance adjusting circuit. In addition, the display panel can partially light up some sub-pixels or light emitting elements in the power saving display mode, so that the sub-pixels or light emitting elements only display black or white bright light. Therefore, the display panel of the invention can effectively reduce the overall power consumption so as to achieve the effect of power saving.

Claims

1. A display panel, comprising:

the driving circuit is provided with a driving end and is used for generating a driving current according to a mode selection signal and the voltage on the driving end;

a first pixel including a plurality of first sub-pixels; and

a second pixel adjacent to the first pixel and including a plurality of second sub-pixels, wherein,

when the mode selection signal indicates a power-saving display mode, at least one first selected sub-pixel of the first pixels is lighted, at least one second selected sub-pixel of the second pixels is lighted, and the display wavelength of the at least one first selected sub-pixel is different from the display wavelength of the at least one second selected sub-pixel.

2. The display panel of claim 1, wherein the display panel further comprises a plurality of third pixels comprising a plurality of third sub-pixels, wherein

When the mode selection signal indicates a normal display mode, the first sub-pixels, the second sub-pixels and the third sub-pixels are sequentially lighted one by one in a laser time interval.

3. The display panel of claim 2, wherein the first pixel, the second pixel, or each of the third pixels comprises:

n light emitting elements; and

and the N control switches are respectively coupled to the N light-emitting elements and controlled by N laser control signals, wherein N is a positive integer.

4. The display panel of claim 1, wherein the display panel further comprises:

a plurality of first auxiliary switches coupled to the driving circuit and the first pixels; and

and at least one second auxiliary switch coupled to the driving circuit and the second pixel, wherein when the mode selection signal indicates the power saving display mode, the first auxiliary switches and the second auxiliary switches are sequentially turned on, so that the at least one first selected sub-pixel of the first pixel and the at least one second selected sub-pixel of the second pixel are sequentially turned on.

5. The display panel of claim 4, wherein the first auxiliary switches and the at least one second auxiliary switch are respectively controlled by a plurality of laser control signals, wherein when the mode selection signal indicates the power saving display mode, the operating frequencies of the laser control signals are adjusted from a first frequency to a second frequency, wherein the second frequency is greater than the first frequency.

6. The display panel of claim 1, wherein the driving circuit comprises:

a data write circuit for providing a data voltage according to a write control signal;

a laser circuit coupled to the data write circuit and providing an operating voltage according to a control signal;

a first capacitor having a first terminal coupled to the data write circuit and a second terminal coupled to the driving terminal;

a driving transistor having the driving end, wherein a first end of the driving transistor is coupled to a power voltage;

an initialization circuit, coupled to the second terminal of the driving transistor, the driving terminal of the driving transistor, the first pixel and the second pixel, for providing a reference voltage according to the write control signal and a read control signal; and

and a voltage holding circuit coupled between the first end and the second end of the first capacitor and used for holding the voltage on the driving end of the driving transistor according to the mode selection signal.

7. The display panel of claim 6, wherein the driving circuit further comprises:

an impedance adjusting circuit coupled to the driving transistor and the initialization circuit,

when the mode selection signal indicates the power-saving display mode, the impedance adjusting circuit adjusts the resistance value of the on-resistance of the driving transistor according to the mode selection signal.

8. The display panel of claim 7, wherein the impedance adjusting circuit comprises:

a first transistor, having a first terminal coupled to the first terminal of the driving transistor and a control terminal receiving the mode selection signal;

a second transistor, having a first terminal coupled to the driving terminal of the driving transistor and a control terminal receiving the mode selection signal; and

a third transistor, wherein a first terminal of the third transistor is coupled to the second terminal of the first transistor, a second terminal of the third transistor is coupled to the initialization circuit, and a control terminal of the third transistor is coupled to the second terminal of the second transistor.

9. The display panel according to claim 8, wherein a width-to-length ratio of the third transistor is larger than a width-to-length ratio of the first transistor or a width-to-length ratio of the second transistor.

10. The display panel of claim 6, wherein the voltage holding circuit comprises:

a first transistor having a second terminal coupled to the first terminal of the first capacitor and a control terminal receiving the mode selection signal;

a second transistor having a second terminal coupled to the second terminal of the first capacitor and a control terminal receiving the mode selection signal; and

a second capacitor having a first terminal coupled to the first terminal of the first transistor and a second terminal coupled to the first terminal of the second transistor.

11. The display panel of claim 6, wherein the data write circuit comprises a first transistor, wherein a first terminal of the first transistor is coupled to the data voltage, a second terminal of the first transistor is coupled to a first terminal of the first capacitor, and a control terminal of the first transistor receives the write control signal.

12. The display panel of claim 6, wherein the laser circuit comprises a first transistor, wherein a first terminal of the first transistor is coupled to the operating voltage, a second terminal of the first transistor is coupled to a first terminal of the first capacitor, and a control terminal of the first transistor receives the control signal.

13. The display panel of claim 6, wherein the initialization circuit comprises a first transistor and a second transistor, wherein a first terminal of the first transistor is coupled to the driving terminal of the driving transistor, a second terminal of the first transistor is coupled to a second terminal of the driving transistor, a control terminal of the first transistor receives the write control signal, a first terminal of the second transistor is coupled to the reference voltage, a second terminal of the second transistor is coupled to a second terminal of the driving transistor, and a control terminal of the second transistor receives the read control signal.

14. The display panel of claim 6, wherein the driving transistor operates in a linear region when the mode selection signal indicates the power saving display mode.