CN113219867A - Multi-core heterogeneous protection measurement and control device - Google Patents
Multi-core heterogeneous protection measurement and control device Download PDFInfo
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Abstract
The application discloses a multi-core heterogeneous protection measurement and control device. The protection measurement and control device comprises a multi-Core chip control module, wherein the multi-Core chip control module comprises a Core1, a Core2 and a DPU chip, and the multi-Core chip control module is respectively integrated with the Core1 service system, the Core2 service system and the DPU chip power special system; the Core1 is used for running a real-time operating system to realize logic functions; the Core2 is used for running a non-real-time operating system and realizing the functions of protection starting and non-real-time transaction processing; the DPU chip power special system is used for realizing a protection control logic algorithm in an IP core mode and customizing a protection measurement and control function aiming at an application scene of primary equipment of a power system.
Description
Technical Field
The application relates to the technical field of protection measurement and control devices, in particular to a multi-core heterogeneous protection measurement and control device.
Background
The requirements of total station information digitization, communication platform networking, information sharing standardization and the like are provided in the construction process of the intelligent digital transformer substation, equipment, a system and network integration are promoted, and higher requirements are provided for digital access output, communication, data processing and logic processing capacity and the like of secondary equipment such as relay protection of various voltage levels. Therefore, continuously improving the platformized software and hardware level becomes an important direction for promoting the optimized improvement of secondary equipment such as relay protection.
With the continuous improvement of the automation degree of the power system, the trend of digitalization and intellectualization of the relay protection measurement and control device is increasingly obvious, and the relay protection measurement and control device has the characteristics of function diversification, rich communication interfaces, high reliability, high performance index and the like. At present, a protection measurement and control device adopts a distributed design principle of a plurality of board cards in hardware design, board card interconnection is realized through a backplane bus, and meanwhile, the universality of the board cards is ensured. The board design can adopt single-core multi-CPU and multi-CPU core modes. In the single-core mode, the device functions are realized on different board cards; in multi-core mode, device functions are distributed across multiple CPU cores. The design of a merging unit, an intelligent terminal, a measurement and control function and a protection function all-in-one device for medium and low voltage intervals is realized based on a main CPU processing module, a DSP processing module and an FPGA comprehensive processing module. The structure can ensure the real-time performance of data exchange and the reliability of a protection function, but has the problems of data sharing, equipment interval expansion, clock signal synchronization, high power consumption and the like.
In the prior art, under a single-core mode, the functions of the device are tightly coupled, and the non-real-time monitoring function influences the real-time protection function of a core; in the general multi-core chip mode, chip resources are wasted, and a protection measurement and control device with the characteristics of miniaturization, low cost, high integration level, low power consumption and the like cannot be constructed.
Disclosure of Invention
The embodiment of the disclosure provides a multi-core heterogeneous protection measurement and control device, which at least solves the problems that in the prior art, the device function coupling is tight and the non-real-time monitoring function affects the real-time protection function of a core under a single-core mode; and under the general multi-core chip mode, chip resources are wasted, and a protection measurement and control device with the characteristics of miniaturization, low cost, high integration level, low power consumption and the like cannot be constructed.
According to an aspect of the embodiments of the present disclosure, there is provided a multi-core heterogeneous protection measurement and control device, including: the multi-Core chip control module is used for integrating a Core1 service system, a Core2 service system and a DPU chip power special system; the Core1 is used for running a real-time operating system to realize logic functions; the Core2 is used for running a non-real-time operating system and realizing the functions of protection starting and non-real-time transaction processing; the DPU chip power special system is used for realizing a protection control logic algorithm in an IP core mode and customizing a protection measurement and control function aiming at an application scene of primary equipment of a power system.
Optionally, the dual-Core system composed of the Core1 and the Core2 communicates with each other through an on-chip cache, wherein the on-chip cache is a Mailbox mechanism and is used for data classified transmission between two cores; data are interacted between the DPU chip and the Core1 through an on-chip bus, and data are interacted between the DPU chip and the Core2 through the on-chip bus.
Optionally, the Mailbox mechanism implements inter-core data classification transmission; the Core1 and the Core2 write data into the Mailbox, the Mailbox informs the Core1 and the Core2 to read data from the Mailbox after receiving the data, link layer data transceiving is completed, and a transport layer protocol and an application layer protocol are realized on a link layer.
Optionally, the protection control logic algorithm comprises at least one of: a pre-data processing algorithm, an electrical parameter calculation algorithm, a data management algorithm and a network communication algorithm.
Optionally, the pre-data processing algorithm performs pre-preprocessing, data synchronization and organization on the valid data, and is configured to perform at least one of the following: 9-2 message processing, digital filtering, synchronous data interpolation, GOOSE message filtering, optical difference synchronization and 9-2 message organization and transmission.
Optionally, the electrical parameter calculation algorithm includes implementing specific electrical parameter calculation and optimization processing according to application requirements, and includes at least one of the following: phasor calculation, harmonic calculation, FFT, half-wave differential fourier, abrupt change, zero sequence, negative sequence, and inter-harmonic.
Optionally, the data management algorithm is used for compressed storage of data.
Optionally, the network communication algorithm uploads data for a link layer, and includes efficient coding, decoding, and processing of a communication packet, including at least one of: HDLC message coding and decoding, GOOSE message coding and decoding, 9-2 message coding and decoding, B code time synchronization, repeated message filtering and broadcast storm suppression.
Optionally, the protection measurement and control device further comprises a signal conditioning circuit, an a/D conversion circuit, an optical coupling isolation circuit, a reset circuit, an internal clock circuit, a GPS/beidou timing circuit, a storage circuit, a key circuit, a screen display circuit, a high/low speed communication circuit, a power supply module, an alternating current input module, a digital output module and a printing serial port; the signal conditioning circuit is used for amplifying the signals of the alternating current input quantity of the protection measurement and control device, processing higher harmonics and eliminating or reducing signal time delay; the A/D conversion circuit is used for converting the analog quantity into the digital quantity; the optical coupling isolation circuit is used for isolating the output signal from the electricity of the input signal; the reset circuit is used for initializing an internal circuit; the internal clock circuit is used for providing a device operation clock; the GPS/Beidou timing circuit is used for receiving and processing a GPS/Beidou clock signal; the storage circuit comprises a double-rate synchronous dynamic random access memory and a Flash memory and is used for storing device parameters, protection fixed values and fault waveforms; the key circuit is used for man-machine interaction; the screen display circuit is used for displaying information of the protection measurement and control device, and the protection measurement and control device comprises an electrical quantity, parameters and an alarm; the high/low speed communication circuit comprises an Ethernet interface based on a PHY chip, an optical fiber interface based on HDLC and an 232/485 serial port, and is used for exchanging information with other equipment or systems; the alternating current input module is used for acquiring current/voltage signals output by various sensors; the digital quantity input module is used for the acquisition device to receive various input signals; the digital output module is used for acquiring tripping and closing of the device and outputting the tripping and closing to other related protection measurement and control devices; the printing serial port is used for connecting a printing device.
In the present invention, a protection measurement and control device based on multi-core isomerism is provided, which includes: the multi-core heterogeneous chip comprises a multi-core heterogeneous chip control module, an A/D conversion circuit, a signal conditioning circuit, an optical coupling isolation circuit, a reset circuit, an internal clock circuit, a GPS/Beidou time correction circuit, a storage circuit, a key circuit, a screen display circuit, a high/low speed communication circuit, a power supply module, an alternating current input module, a digital quantity input module and a digital quantity output module.
The scheme of the invention integrates a high-integration protection measurement and control device overall design scheme, a hardware external interface and the like. The multi-core heterogeneous chip realizes function integration, the number of components is reduced by more than 30%, and the area of a printed board is reduced by more than 40%; the device design is simplified, the reliability is improved, and the cost is reduced; the IP core is autonomous and controllable, safe and reliable, the algorithm is fully completed, the operation load of the processing core is reduced, and high-complexity protection logic can be operated; the use of the special algorithm creates conditions for protecting the customization of the measurement and control device, and is beneficial to the deep fusion of primary and secondary equipment.
Further, the problem that the real-time protection function of a core is influenced by a non-real-time monitoring function due to tight coupling of device functions in a single-core mode in the prior art is solved; in the general multi-core chip mode, chip resources are wasted, and a protection measurement and control device with the characteristics of miniaturization, low cost, high integration level, low power consumption and the like cannot be constructed.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the disclosure and together with the description serve to explain the disclosure and not to limit the disclosure. In the drawings:
fig. 1 is a schematic diagram of a multi-core heterogeneous protection measurement and control device according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a multi-core chip control module according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of a dual core communication mechanism according to an embodiment of the disclosure.
Detailed Description
The exemplary embodiments of the present invention will now be described with reference to the accompanying drawings, however, the present invention may be embodied in many different forms and is not limited to the embodiments described herein, which are provided for complete and complete disclosure of the present invention and to fully convey the scope of the present invention to those skilled in the art. The terminology used in the exemplary embodiments illustrated in the accompanying drawings is not intended to be limiting of the invention. In the drawings, the same units/elements are denoted by the same reference numerals.
Unless otherwise defined, terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Further, it will be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.
According to a first aspect of the embodiment, a multi-core heterogeneous protection measurement and control device is provided. The protection measurement and control device comprises a multi-Core chip control module, a Core1 service system, a Core2 service system and a DPU chip power special system, wherein the multi-Core chip control module is used for integrating the Core1 service system, the Core2 service system and the DPU chip power special system; the Core1 is used for running a real-time operating system to realize logic functions; the Core2 is used for running a non-real-time operating system and realizing the functions of protection starting and non-real-time transaction processing; the DPU chip power special system is used for realizing a protection control logic algorithm in an IP core mode and customizing a protection measurement and control function aiming at an application scene of primary equipment of a power system.
Referring to fig. 1, the present invention provides a protection measurement and control device based on multi-core isomerism, including: the multi-core heterogeneous chip comprises a multi-core heterogeneous chip control module, an A/D conversion circuit, a signal conditioning circuit, an optical coupling isolation circuit, a reset circuit, an internal clock circuit, a GPS/Beidou time correction circuit, a storage circuit, a key circuit, a screen display circuit, a high/low speed communication circuit, a power supply module, an alternating current input module, a digital quantity input module and a digital quantity output module.
The multi-core heterogeneous chip control module is respectively connected with an A/D conversion circuit, an optical coupling isolation circuit, a reset circuit, a clock circuit, a storage circuit, a key circuit, a screen display circuit, a high/low speed communication circuit and a power module, the A/D conversion circuit is connected with a signal conditioning circuit, the optical coupling isolation circuit is connected with a digital quantity input module, a digital quantity output module, a GPS/Beidou timing circuit and a printing serial port, and the signal conditioning circuit is connected with an alternating current quantity input module.
The alternating current input module comprises a voltage transformer, a current transformer, a Rogowski coil, an LPCT low-power consumption sensor and the like, is sequentially connected with a signal conditioning circuit and an A/D conversion circuit, and is used for converting an alternating current signal into a digital signal which can be processed by a chip; the digital quantity input module is used for collecting common switching quantity signals such as position signals of load switch equipment, position signals of a circuit breaker, fusing signals of a fuse and the like, and can also collect non-electric quantity signals such as heavy gas action tripping, light gas action warning and the like, the digital quantity output module is mainly used for functions of outlet tripping, signal warning and the like of various protection devices, the key and the display module are mainly used for man-machine interaction, and the communication module is used for communicating with other intelligent equipment and a monitoring center.
The alternating current signal collected by the protection measurement and control device comprises three-phase measurement current, three-phase protection current, zero sequence current, three-phase voltage, energy storage coil current, opening coil current, closing coil current, temperature and humidity in primary equipment and the like. The three-phase measuring current is sampled by a linear current transformer of 5A/3.53V or an LPCT signal of a quadratic rating of 3.53V, the three-phase protection current signal is sampled by a current transformer of 100A/7.07V or a Rogowski coil of 1000A/22.5mV, the zero-sequence current is sampled by a current transformer of 20A/7.07V and the measuring current in a combined mode, and the three-phase voltage is sampled by a voltage transformer of 220V/7.07V.
The digital output module adopts a starting relay locking mode, a control signal of the starting relay is controlled by the kernel of the multi-core chip, and a positive power supply of the outlet relay can be opened only after the starting relay acts, so that partial decoupling of digital output control is realized, and protection misoperation caused by device damage is avoided. When output is needed, the starting relay is firstly conducted, the photoelectric coupler is conducted, the starting relay acts, the normally open contact of the relay is closed, and the tripping or alarming circuit is conducted.
The protection measurement and control device is provided with rich protection algorithms, including three-section type overcurrent protection, state quantity automatic identification differential protection, zero sequence protection, overload protection, reclosing, small current grounding, interruption lockout protection, control circuit disconnection, spring non-energy storage, PT disconnection alarm and the like. The protection measurement and control device divides different protection algorithms into independent modules according to a modular design concept, each module has independent inlet conditions and outlet states, each module is provided with a control soft pressing plate, the protection function of the device can be configured by controlling the input or the exit of the soft pressing plates, and the setting value and the outlet mode (tripping or alarming) of each protection function can be configured by keys or a communication network. The modularized design ensures that the protection function has extremely strong readability and portability, the cooperation relation among all modules is clear, and the improvement of the reliability of protection is facilitated.
Referring to fig. 2, the multi-Core heterogeneous chip control module provided by the invention is composed of three parts, namely a Core1, a Core2 and a DPU, and integrates a Core1/Core2 service subsystem and a DPU power special subsystem to form a multi-Core heterogeneous architecture. The Core1 and the Core2 exchange data through on-chip cache, and the DPU and the Core1/Core2 exchange data through on-chip buses. The chip 1 is used for realizing the functions of CPU, DSP, FPGA logic and the like, realizing the integration of the device, improving the functional integration of the device and realizing the physical isolation and decoupling of the real-time function and the non-real-time function operation on software. The device has the advantages of effectively reducing the overall power consumption of the device, improving the reliability and expandability of the device, simultaneously having flexible protection function configuration and protection outlet configuration functions, simplifying the management and use of the protection setting value and being convenient to use and maintain.
Referring to fig. 3, the Core1 and the Core2 dual cores of the protection measurement and control device based on multi-Core heterogeneous communication communicate with each other through an on-chip cache, and the cache is set as a Mailbox mechanism. And realizing the classified transmission of data between two cores based on a Mailbox mechanism. Both Core1 and Core2 complete writing data to the Mailbox, the Core1 and Core2 are notified of reading by an interrupt upon receipt by the Mailbox, and Core1 and Core2 read data from the Mailbox. The data receiving and sending of the link layer are completed through the steps, the transmission layer and the application protocol are realized on the link layer, and the reliable communication between the double cores is established.
Therefore, function integration is realized through the multi-core heterogeneous chip, the number of components is reduced by more than 30%, and the area of the printed board is reduced by more than 40%; the device design is simplified, the reliability is improved, and the cost is reduced; the IP core is autonomous and controllable, safe and reliable, the algorithm is fully completed, the operation load of the processing core is reduced, and high-complexity protection logic can be operated; the use of the special algorithm creates conditions for protecting the customization of the measurement and control device, and is beneficial to the deep fusion of primary and secondary equipment. Further, the problem that the real-time protection function of a core is influenced by a non-real-time monitoring function due to tight coupling of device functions in a single-core mode in the prior art is solved; in the general multi-core chip mode, chip resources are wasted, and a protection measurement and control device with the characteristics of miniaturization, low cost, high integration level, low power consumption and the like cannot be constructed.
Optionally, the dual-Core system composed of the Core1 and the Core2 communicates with each other through an on-chip cache, wherein the on-chip cache is a Mailbox mechanism and is used for data classified transmission between two cores; data are interacted between the DPU chip and the Core1 through an on-chip bus, and data are interacted between the DPU chip and the Core2 through the on-chip bus.
Optionally, the Mailbox mechanism implements inter-core data classification transmission; the Core1 and the Core2 write data into the Mailbox, the Mailbox informs the Core1 and the Core2 to read data from the Mailbox after receiving the data, link layer data transceiving is completed, and a transport layer protocol and an application layer protocol are realized on a link layer.
Optionally, the protection control logic algorithm comprises at least one of: a pre-data processing algorithm, an electrical parameter calculation algorithm, a data management algorithm and a network communication algorithm.
Optionally, the pre-data processing algorithm performs pre-preprocessing, data synchronization and organization on the valid data, and is configured to perform at least one of the following: 9-2 message processing, digital filtering, synchronous data interpolation, GOOSE message filtering, optical difference synchronization and 9-2 message organization and transmission.
Optionally, the electrical parameter calculation algorithm includes implementing specific electrical parameter calculation and optimization processing according to application requirements, and includes at least one of the following: phasor calculation, harmonic calculation, FFT, half-wave differential fourier, abrupt change, zero sequence, negative sequence, and inter-harmonic.
Optionally, the data management algorithm is used for compressed storage of data.
Optionally, the network communication algorithm uploads data for a link layer, and includes efficient coding, decoding, and processing of a communication packet, including at least one of: HDLC message coding and decoding, GOOSE message coding and decoding, 9-2 message coding and decoding, B code time synchronization, repeated message filtering and broadcast storm suppression.
Optionally, the protection measurement and control device further comprises a signal conditioning circuit, an a/D conversion circuit, an optical coupling isolation circuit, a reset circuit, an internal clock circuit, a GPS/beidou timing circuit, a storage circuit, a key circuit, a screen display circuit, a high/low speed communication circuit, a power supply module, an alternating current input module, a digital output module and a printing serial port; the signal conditioning circuit is used for amplifying the signals of the alternating current input quantity of the protection measurement and control device, processing higher harmonics and eliminating or reducing signal time delay; the A/D conversion circuit is used for converting the analog quantity into the digital quantity; the optical coupling isolation circuit is used for isolating the output signal from the electricity of the input signal; the reset circuit is used for initializing an internal circuit; the internal clock circuit is used for providing a device operation clock; the GPS/Beidou timing circuit is used for receiving and processing a GPS/Beidou clock signal; the storage circuit comprises a double-rate synchronous dynamic random access memory and a Flash memory and is used for storing device parameters, protection fixed values and fault waveforms; the key circuit is used for man-machine interaction; the screen display circuit is used for displaying information of the protection measurement and control device, and the protection measurement and control device comprises an electrical quantity, parameters and an alarm; the high/low speed communication circuit comprises an Ethernet interface based on a PHY chip, an optical fiber interface based on HDLC and an 232/485 serial port, and is used for exchanging information with other equipment or systems; the alternating current input module is used for acquiring current/voltage signals output by various sensors; the digital quantity input module is used for the acquisition device to receive various input signals; the digital output module is used for acquiring tripping and closing of the device and outputting the tripping and closing to other related protection measurement and control devices; the printing serial port is used for connecting a printing device.
The scheme provided by the embodiment integrates a protection measurement and control device with high integration level, and comprises a general design scheme, a hardware external interface and the like. The multi-core heterogeneous chip realizes function integration, the number of components is reduced by more than 30%, and the area of a printed board is reduced by more than 40%; the device design is simplified, the reliability is improved, and the cost is reduced; the IP core is autonomous and controllable, safe and reliable, the algorithm is fully completed, the operation load of the processing core is reduced, and high-complexity protection logic can be operated; the use of the special algorithm creates conditions for protecting the customization of the measurement and control device, and is beneficial to the deep fusion of primary and secondary equipment.
Further, the problem that the real-time protection function of a core is influenced by a non-real-time monitoring function due to tight coupling of device functions in a single-core mode in the prior art is solved; in the general multi-core chip mode, chip resources are wasted, and a protection measurement and control device with the characteristics of miniaturization, low cost, high integration level, low power consumption and the like cannot be constructed.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The scheme in the embodiment of the application can be implemented by adopting various computer languages, such as object-oriented programming language Java and transliterated scripting language JavaScript.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (9)
1. A multi-core heterogeneous protection measurement and control device is characterized by comprising:
the multi-Core chip control module is used for integrating a Core1 service system, a Core2 service system and a DPU chip power special system;
the protection measurement and control device comprises a multi-Core chip control module, the multi-Core chip control module comprises a Core1, a Core2 and a DPU chip, and the multi-Core chip control module is respectively integrated with the Core1 service system, the Core2 service system and the DPU chip power special system;
the Core1 is used for running a real-time operating system to realize logic functions;
the Core2 is used for running a non-real-time operating system and realizing the functions of protection starting and non-real-time transaction processing;
the DPU chip power special system is used for realizing a protection control logic algorithm in an IP core mode and customizing a protection measurement and control function aiming at an application scene of primary equipment of a power system.
2. The apparatus of claim 1,
the dual-Core system formed by the Core1 and the Core2 is communicated through an on-chip cache, wherein the on-chip cache is a Mailbox mechanism and is used for classified transmission of data between two cores;
data are interacted between the DPU chip and the Core1 through an on-chip bus, and data are interacted between the DPU chip and the Core2 through the on-chip bus.
3. The apparatus of claim 2,
the Mailbox mechanism realizes the classified transmission of data between two cores;
the Core1 and the Core2 write data into the Mailbox, the Mailbox informs the Core1 and the Core2 to read data from the Mailbox after receiving the data, link layer data transceiving is completed, and a transport layer protocol and an application layer protocol are realized on a link layer.
4. The apparatus of claim 1,
the protection control logic algorithm comprises at least one of: a pre-data processing algorithm, an electrical parameter calculation algorithm, a data management algorithm and a network communication algorithm.
5. The apparatus of claim 4,
the pre-processing algorithm is used for performing pre-processing, data synchronization and organization aiming at effective data and is used for executing at least one of the following steps: 9-2 message processing, digital filtering, synchronous data interpolation, GOOSE message filtering, optical difference synchronization and 9-2 message organization and transmission.
6. The apparatus of claim 4,
the electric parameter calculation algorithm comprises the following steps of realizing specific electric parameter calculation and optimization according to application requirements, wherein the specific electric parameter calculation and optimization comprises at least one of the following steps: phasor calculation, harmonic calculation, FFT, half-wave differential fourier, abrupt change, zero sequence, negative sequence, and inter-harmonic.
7. The apparatus of claim 4, comprising:
the data management algorithm is used for compressed storage of data.
8. The apparatus of claim 4,
the network communication algorithm uploads data aiming at a link layer, and comprises coding, decoding and processing of communication messages, wherein the network communication algorithm comprises at least one of the following steps: HDLC message coding and decoding, GOOSE message coding and decoding, 9-2 message coding and decoding, B code time synchronization, repeated message filtering and broadcast storm suppression.
9. The apparatus of claim 1,
the protection measurement and control device also comprises a signal conditioning circuit, an A/D conversion circuit, an optical coupling isolation circuit, a reset circuit, an internal clock circuit, a GPS/Beidou time correction circuit, a storage circuit, a key circuit, a screen display circuit, a high/low speed communication circuit, an alternating current input module, a digital quantity output module and a printing serial port;
the signal conditioning circuit is used for amplifying the signals of the alternating current input quantity of the protection measurement and control device, processing higher harmonics and eliminating or reducing signal time delay;
the A/D conversion circuit is used for converting the analog quantity into the digital quantity;
the optical coupling isolation circuit is used for isolating the output signal from the electricity of the input signal;
the reset circuit is used for initializing an internal circuit;
the internal clock circuit is used for providing a device operation clock;
the GPS/Beidou timing circuit is used for receiving and processing a GPS/Beidou clock signal;
the storage circuit comprises a double-rate synchronous dynamic random access memory and a Flash memory and is used for storing device parameters, protection fixed values and fault waveforms;
the key circuit is used for man-machine interaction;
the screen display circuit is used for displaying information of the protection measurement and control device, and the protection measurement and control device comprises an electrical quantity, parameters and an alarm;
the high/low speed communication circuit comprises an Ethernet interface based on a PHY chip, an optical fiber interface based on HDLC and an 232/485 serial port, and is used for exchanging information with other equipment or systems;
the alternating current input module is used for acquiring current/voltage signals output by various sensors;
the digital quantity input module is used for the acquisition device to receive various input signals;
the digital output module is used for acquiring tripping and closing of the device and outputting the tripping and closing to other related protection measurement and control devices;
the printing serial port is used for connecting a printing device.
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