CN113206148A - Trench MOSFET and method of manufacturing the same - Google Patents

Trench MOSFET and method of manufacturing the same Download PDF

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Publication number
CN113206148A
CN113206148A CN202110381679.3A CN202110381679A CN113206148A CN 113206148 A CN113206148 A CN 113206148A CN 202110381679 A CN202110381679 A CN 202110381679A CN 113206148 A CN113206148 A CN 113206148A
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gate
conductor
trench
insulating layer
semiconductor substrate
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CN113206148B (en
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王加坤
孙鹤
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Hangzhou Xinmai Semiconductor Technology Co ltd
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Hangzhou Chuangqin Sensor Technology Co Ltd
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors

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Abstract

Disclosed are a trench MOSFET and a method of manufacturing the same, the trench MOSFET including: a semiconductor substrate of a first doping type; a trench extending from an upper surface of the semiconductor substrate to an inside thereof; a first insulating layer and a shield conductor located inside the trench, the first insulating layer being located at a lower sidewall and a bottom of the trench and separating the shield conductor from the semiconductor substrate; the grid conductor and the grid dielectric layer are positioned on the upper part of the groove, and the grid dielectric layer is positioned on the upper side wall of the groove and separates the grid conductor from the semiconductor substrate; and a gate conductive channel connected to the gate conductor; the thickness of the position of the gate conductor connected with the gate conductive channel meets the process requirement of the through hole, the gate conductor cannot be penetrated through, the problem of short circuit between the gate and the shielding conductor is avoided to a great extent, and the reliability of the MOSFET is improved.

Description

Trench MOSFET and method of manufacturing the same
Technical Field
The present invention relates to semiconductor technology, and more particularly, to a trench MOSFET and a method of manufacturing a trench MOSFET.
Background
The shielding grid groove MOSFET is used as a power device and has the characteristics of high breakdown voltage, low on-resistance and high switching speed.
As shown in fig. 1, the conventional shielded gate trench MOSFET device includes a gate contact hole 101 connected to a gate conductor 102 and a source contact hole 103 connected to a connector contact region 104, where the gate conductor 102 of the shielded gate trench MOSFET has a structure with a thin middle and two thick sides, and a conventional gate conductor connection method is to form a contact hole in the middle of the gate conductor, where the gate conductor is relatively thin, and if the quality of an oxide layer below the gate conductor is poor, the gate conductor is easily short-circuited with the shield conductor below the gate conductor.
Disclosure of Invention
Accordingly, the present invention is directed to a trench MOSFET and a method for fabricating the same to solve the problem of gate-source alignment.
According to a first aspect of the present invention, there is provided a trench MOSFET comprising: a semiconductor substrate of a first doping type; a trench extending from an upper surface of the semiconductor substrate to an inside thereof; a first insulating layer and a shield conductor located inside the trench, the first insulating layer being located at a lower sidewall and a bottom of the trench and separating the shield conductor from the semiconductor substrate; the grid conductor and the grid dielectric layer are positioned on the upper part of the groove, and the grid dielectric layer is positioned on the upper side wall of the groove and separates the grid conductor from the semiconductor substrate; and a gate conductive channel connected to the gate conductor; the thickness of the position of the gate conductor connected with the gate conductive channel meets the process requirement of the through hole and cannot be penetrated through.
Preferably, the gate conductor in one trench corresponds to one or two gate conductive channels.
Preferably, when the gate conductor has a different thickness in the vertical direction of the trench MOSFET, the gate conductive channel extends to a portion of the gate conductor where the thickness is thicker.
Preferably, the gate conductor is located at least on an upper surface of the first insulating layer.
Preferably, the gate conductor and the shield conductor are isolated from each other by a second insulating layer formed by oxidizing a part of the shield conductor.
Preferably, an upper surface of the shield conductor is lower than a lower surface of the gate conductor.
Preferably, an upper surface of the shield conductor is not lower than a lower surface of the gate conductor.
Preferably, the gate conductor has an inverted concave shape, and a thickness of a portion of the gate conductor on the shield conductor is smaller than a thickness of a portion thereof on the first insulating layer.
Preferably, the gate conductor includes a first portion and a second portion separated from each other by the second insulating layer.
Preferably, the gate conductor includes a first portion and a second portion separated from each other, and the first portion and the second portion are respectively located at both sides of the shield conductor.
Preferably, the width of the upper section of the shield conductor between the gate conductors is smaller than the width of the lower section of the shield conductor.
Preferably, the shielding conductor is a polysilicon material.
Preferably, when the number of the gate conductive channels is one, one of the gate conductive channels is in contact with any thicker portion of the gate conductor.
Preferably, when the number of the gate conductive channels is two, the two gate conductive channels are respectively in contact with the thicker portions of the two gate conductors.
Preferably, the number of the gate conductive channels is two, and the two gate conductive channels are respectively in contact with the first portion and the second portion.
Preferably, the method further comprises the following steps: the semiconductor device comprises an interlayer dielectric layer positioned on the upper surface of the semiconductor substrate, a gate metal electrode and a source metal electrode positioned on the interlayer dielectric layer, and a drain electrode positioned on the lower surface of the semiconductor substrate, wherein the gate metal electrode and the source metal electrode are separated.
Preferably, the gate conductive channel includes a contact hole extending from an upper surface of the interlayer dielectric layer into the gate conductor, and a metal filled in the contact hole, and the gate metal electrode contacts the gate conductor through the gate conductive channel.
Preferably, the method further comprises the following steps: the body region of the second doping type is positioned on two sides of the groove, extends from the upper surface of the semiconductor substrate to the interior of the semiconductor substrate and is adjacent to the groove; a source region of a first doping type located in the body region adjacent to the trench, and a body contact region of a second doping type located in the body region.
Preferably, the semiconductor device further comprises a source region conductive channel which extends from the upper surface of the interlayer dielectric layer, penetrates through the source region and reaches the body contact region, and the source metal electrode is in contact with the body contact region through the source region conductive channel.
Preferably, the semiconductor base includes a substrate of a first doping type and an epitaxial semiconductor layer of the first doping type on the substrate, and the trench is located in the epitaxial semiconductor layer.
According to a second aspect of the present invention, there is provided a method of manufacturing a trench MOSFET, comprising: forming a groove extending from the upper surface to the interior of the groove in a semiconductor substrate, wherein the semiconductor substrate is of a first doping type; forming a first insulating layer and a shielding conductor in the trench, wherein the first insulating layer is positioned on the lower side wall and the bottom of the trench and separates the shielding conductor from the semiconductor substrate, and the upper surface of the shielding conductor is higher than that of the first insulating layer; forming a gate dielectric layer on the side wall which is not covered by the first insulating layer on the upper part of the groove, filling a gate conductor on the upper part of the groove, and isolating the gate conductor from the semiconductor substrate by the gate dielectric layer; and simultaneously when the gate dielectric layer is formed, the exposed part of the shielding conductor by the first insulating layer is also oxidized.
Preferably, the gate dielectric layer is formed by a thermal oxidation process.
Preferably, the shield conductor and the gate conductor are separated by a second insulating layer formed by oxidizing the shield conductor.
Preferably, one or two gate conductive channels are formed in connection with the gate conductor.
Preferably, when the upper surface of the shielding conductor is lower than the upper surface of the trench and the exposed portion of the shielding conductor is completely oxidized by the first insulating layer, the gate conductor forms an inverted "concave" shape, and the thickness of the portion of the gate conductor on the shielding conductor is smaller than that of the portion of the gate conductor on the first insulating layer.
Preferably, when the upper surface of the shield conductor is not lower than the upper surface of the trench and the exposed portion of the shield conductor by the first insulating layer is completely oxidized, the gate conductor forms two portions separated from each other and separated by the second insulating layer.
Preferably, when the upper surface of the shielding conductor is lower than the upper surface of the trench and the exposed portion of the shielding conductor by the first insulating layer is not completely oxidized, the gate conductor is located at two portions separated from each other and located at two sides of the non-oxidized shielding conductor respectively.
Preferably, the width of the upper section of the shield conductor between the gate conductors is smaller than the width of the lower section of the shield conductor.
Preferably, the method further comprises the following steps: forming an interlayer dielectric layer on the upper surface of the semiconductor substrate; and forming a grid metal electrode and a source metal electrode which are positioned on the upper surface of the interlayer dielectric layer, and forming a drain electrode which is positioned on the lower surface of the semiconductor substrate.
Preferably, the method for forming the gate conductive channel comprises: forming a contact hole extending from an upper surface of the interlayer dielectric layer to the gate conductor before forming the gate metal electrode; and a metal filled in the contact hole.
Preferably, when the number of the gate conductive channels is one, one of the gate conductive channels is in contact with any thicker portion of the gate conductor.
Preferably, when the number of the gate conductive channels is two, the two gate conductive channels are respectively in contact with the thicker portions of the two gate conductors.
Preferably, the number of the gate conductive channels is two, and the two gate conductive channels are respectively in contact with the first portion and the first portion.
Preferably, the method further comprises the following steps: forming a body region of the second doping type, which is positioned at two sides of the groove and extends from the upper surface of the semiconductor substrate to the interior of the groove, wherein the body region is adjacent to the groove; forming a source region of a first doping type in the body region adjacent to the trench, and forming a body contact region of a second doping type in the body region.
Preferably, the method further comprises forming a source region conductive via extending from an upper surface of the interlevel dielectric layer to the body contact region.
Preferably, the semiconductor base includes a substrate of a first doping type and an epitaxial layer of the first doping type on the substrate, and the trench is located in the epitaxial layer.
According to the trench MOSFET and the manufacturing method thereof provided by the invention, in the process of forming the gate dielectric layer, the shielding conductor exposed by the first insulating layer is also oxidized to form the second insulating layer, and then the gate conductor is deposited, so that the steps of the process are simplified, and the process cost is reduced. In addition, the grid conductive channel is arranged at the thicker parts of the two sides of the grid conductor so as to prevent the grid conductive channel from being positioned at the thinner part of the middle of the grid conductor to cause short circuit between the grid conductor and the shielding conductor and improve the reliability of the MOS.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a cross-sectional view of a prior art trench MOSFET;
fig. 2 shows a cross-sectional view of a trench MOSFET according to a first embodiment of the invention;
fig. 3 shows a cross-sectional view of a trench MOSFET according to a second embodiment of the invention;
fig. 4 shows a cross-sectional view of a trench MOSFET according to a third embodiment of the invention;
fig. 5a-5c show cross-sectional views of various stages of a method of fabricating a trench MOSFET, in accordance with an embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly above another layer, another region, the expression "a directly above B" or "a above and adjacent to B" will be used herein. In the present application, "a is directly in B" means that a is in B and a and B are directly adjacent, rather than a being in a doped region formed in B.
In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed. The term "laterally extending" refers to extending in a direction substantially perpendicular to the depth direction of the trench.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Unless otherwise specified below, various portions of the semiconductor device may be composed of materials well known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as GaAs, InP, GaN, SiC, and group IV semiconductors such as Si, Ge. The gate conductor may be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of the various conductive materials. The gate dielectric may be formed of SiO2Or a dielectric constant greater than SiO2For example, the material composition of (1) includes oxides, nitrides, oxynitrides, silicates, aluminates, titanates. Further, the gate dielectric may be formed of not only a material known to those skilled in the art, but also a material for the gate dielectric developed in the future.
The invention discloses a trench MOSFET, which is characterized by comprising: a semiconductor substrate of a first doping type; a trench extending from an upper surface of the semiconductor substrate to an inside thereof; a first insulating layer and a shield conductor located inside the trench, the first insulating layer being located at a lower sidewall and a bottom of the trench and separating the shield conductor from the semiconductor substrate; the grid conductor and the grid dielectric layer are positioned on the upper part of the groove, and the grid dielectric layer is positioned on the upper side wall of the groove and separates the grid conductor from the semiconductor substrate; and a gate conductive channel connected to the gate conductor; the thickness of the position of the gate conductor connected with the gate conductive channel meets the process requirement of the through hole and cannot be penetrated through.
In particular, the present invention may be presented in a variety of forms, some examples of which are described below.
Fig. 2 shows a cross-sectional view of a trench MOSFET according to a first embodiment of the invention.
The trench MOSFET includes a semiconductor substrate, a trench 203 in the semiconductor substrate, a first insulating layer 204 inside the trench 203, a shield conductor 205, a gate dielectric layer 206 and a gate conductor 207, and a gate conductive channel 212 connected to the gate conductor 207. Specifically, the trench 203 extends from the upper surface of the semiconductor substrate into the interior thereof, the trench 203 terminating in the semiconductor substrate. The first insulating layer 204 is located at the lower sidewall and bottom of the trench 203 and separates the shield conductor 205 from the semiconductor substrate. The gate dielectric layer 206 and the gate conductor 207 are located at the upper part of the trench, the gate dielectric layer 206 is located at the upper side wall of the trench 203 and separates the gate conductor 207 from the semiconductor substrate, and the gate conductor 207 is located at least on the upper surface of the first insulating layer 204. The shield conductor 205 is isolated from the gate conductor 207 by a second insulating layer 208, and the second insulating layer 208 is formed by oxidizing a portion of the shield conductor 205. The thickness of the gate conductor 207 connected to the gate conductive via 212 is sufficient for the process requirement of the via and is not penetrated. The gate conductor 207 in one trench corresponds to one or two gate conductive channels 212. In the present embodiment, the first insulating layer 204 may be made of oxide or nitride, such as silicon oxide or silicon nitride; the gate dielectric layer 206 and the second insulating layer 208 are oxide layers formed by a thermal oxidation process. Shield conductor 205 and gate conductor 207 may be comprised of polysilicon.
In this embodiment, the upper surface of the shielding conductor 205 is lower than the upper surface of the gate conductor 207, the gate conductor 207 is in an inverted "concave" shape, and the thickness of the portion of the gate conductor 207 on the shielding conductor 205 is smaller than the thickness of the portion of the gate conductor 207 on the first insulating layer 204, i.e., the gate conductor 207 includes two thicker portions. When the number of the gate conductive channels 212 is one, the gate conductive channels 212 are connected to any thicker portion of the gate conductor 207; when the number of the gate conductive paths 212 is two, the two gate conductive paths 212 are respectively connected to the two thicker portions of the gate conductor 207.
The trench MOSFET further includes an interlayer dielectric layer 216 on the upper surface of the semiconductor substrate and a metal electrode over the interlayer dielectric layer 216. The metal electrodes include a gate metal electrode 215 and a source metal electrode 214. The gate conductive via 212 includes a first contact hole extending from an upper surface of the interlayer dielectric layer 216 into the gate conductor 207 and a metal material filling the first contact hole. The gate metal electrode 215 is in contact with the gate conductor 207 through the gate conductive via 212.
The trench MOSFET further includes body regions 209, source regions 210, and body contact regions 211 in the semiconductor substrate. Specifically, the body region 209 is located in an upper region of the semiconductor substrate adjacent to the trench and is of the second doping type, wherein a junction depth of the body region 209 does not exceed a depth of the gate conductor 207 in the trench; source region 210 is located in body region 209 and is of a first doping type; and body contact region 211 is in body region 209 and is of a second doping type. The body contact region 211 has a doping concentration greater than that of the body region 209 to reduce the subsequent ohmic contact resistance with the source electrode. The second doping type is opposite to the first doping type, the first doping type is one of an N type and a P type, and the second doping type is the other of the N type and the P type. The trench MOSFET further includes a source region conductive channel 213, the source region conductive channel 213 including a second contact hole starting from the upper surface of the interlayer dielectric layer 216, passing through the source region 210, extending to the body contact region 211, and a metal material filled in the second contact hole. The source metal electrode 214 contacts the body contact region 211 through the source region conductive channel 213.
In the present application, the semiconductor base comprises a semiconductor substrate 201 and an epitaxial semiconductor layer 202 located thereon, said semiconductor substrate 201 being, for example, composed of silicon and being of a first doping type. The first doping type is one of an N-type and a P-type, and the second doping type is the other of the N-type and the P-type. To form the N-type epitaxial semiconductor layer or region, N-type dopants (e.g., P, As) may be implanted in the epitaxial semiconductor layer and region. To form the P-type epitaxial semiconductor layer or region, a P-type dopant (e.g., B) may be doped into the epitaxial semiconductor layer and region. In one example, the semiconductor substrate 201 is doped N-type.
An epitaxial semiconductor layer 202 of the first doping type is located on a surface of the semiconductor substrate 201 opposite to the drain electrode 220 (i.e., on a first surface of the semiconductor substrate 201), and the trench 203 is located in the epitaxial semiconductor layer 202. The epitaxial semiconductor layer 202 is composed of, for example, silicon, and the epitaxial semiconductor layer 202 is a lightly doped layer with respect to the semiconductor substrate 201. The second surface of the semiconductor substrate is thinned by a thinning technique, and the drain electrode 220 is formed on the second surface. In some embodiments, a buffer layer may be further disposed between the semiconductor substrate 201 and the epitaxial semiconductor layer 202, and the buffer layer has the same doping type as the semiconductor substrate, in order to reduce the instability of the interface between the semiconductor substrate and the epitaxial semiconductor layer due to the defect of the substrate.
Fig. 3 shows a cross-sectional view of a trench MOSFET according to a second embodiment of the invention.
The trench MOSFET of this embodiment is different from the trench MOSFET of the first embodiment in that the shape of the gate conductor is different, and other structures are completely the same, and are not described herein again.
In this embodiment, the upper surface of the shielding conductor 305 is lower than the lower surface of the gate conductor 307, and the gate conductor 307 includes a first portion and a second portion separated from each other, and the first portion and the second portion are separated by the second insulating layer 308. The number of the gate conductive paths 312 is two, and the two gate conductive paths 312 are in contact with the first portion and the second portion of the gate conductor 307, respectively.
Fig. 4 shows a cross-sectional view of a trench MOSFET according to a third embodiment of the invention.
The trench MOSFET of this embodiment is different from the trench MOSFET of the first embodiment in that the shapes of the gate conductor and the shield conductor are different, and other structures are completely the same, and are not described herein again.
In this embodiment, the upper surface of the shielding conductor 405 is not lower than the lower surface of the gate conductor 407, and the gate conductor 407 includes a first portion and a second portion separated from each other, and the first portion and the second portion are respectively located on two sides of the shielding conductor 405. The width of the upper section of the shield conductor 405 between the gate conductors 407 is smaller than the width of the lower section of the shield conductor 405. The number of the gate conductive paths 412 is two, and the two gate conductive paths 412 are respectively in contact with the first portion and the second portion of the gate conductor 407.
According to the trench MOSFET structure provided by the invention, the thickness of the position of the gate conductor connected with the gate conductive channel meets the process requirement of a through hole by changing the position of the gate conductive channel, and the gate conductor cannot be penetrated through, so that the problem of short circuit between the gate and a shielding conductor is avoided to a great extent, and the MOS reliability is improved.
The invention provides a method for manufacturing a trench MOSFET, which comprises the following steps: forming a groove extending from the upper surface to the interior of the groove in a semiconductor substrate, wherein the semiconductor substrate is of a first doping type; forming a first insulating layer and a shielding conductor in the trench, wherein the first insulating layer is positioned on the lower side wall and the bottom of the trench and separates the shielding conductor from the semiconductor substrate, and the upper surface of the shielding conductor is higher than that of the first insulating layer; forming a gate dielectric layer on the side wall which is not covered by the first insulating layer on the upper part of the groove, filling a gate conductor on the upper part of the groove, and isolating the gate conductor from the semiconductor substrate by the gate dielectric layer; and simultaneously when the gate dielectric layer is formed, the exposed part of the shielding conductor by the first insulating layer is also oxidized.
In particular, fig. 5a to 5c depict various stages of a method of fabricating a trench MOSFET according to the present invention.
As shown in fig. 5a, a trench 203 is formed in the semiconductor substrate extending from the surface to the inside thereof. Specifically, in the present application, the semiconductor base includes a semiconductor substrate 201 and an epitaxial semiconductor layer 202 on the semiconductor substrate 201. Forming a patterned barrier layer on the epitaxial semiconductor layer 202; the epitaxial semiconductor layer 202 is etched using the barrier layer as a mask, and a trench 203 is further formed in the epitaxial semiconductor layer 202. The trench extends into the epitaxial semiconductor layer 202 from the upper surface of the epitaxial semiconductor layer 202. For example, the depth of the trench can be controlled by controlling the time of etching.
Subsequently, a first insulating layer and an electrode conductor are formed within the trench. Specifically, a first insulating layer 204 is formed inside the trench 203 by means of thermal oxidation or chemical vapor deposition, that is, the first insulating layer 204 covers the bottom and the side wall of the trench; the first insulating layer 204 may be composed of an oxide or a nitride, for example, silicon oxide or silicon nitride.
A shield conductor 205 is then formed inside the trench by means of low pressure chemical vapor deposition. A first insulating layer 204 separates the shield conductor 205 from the epitaxial semiconductor layer 202. The shield conductor 205 may be comprised of polysilicon.
As shown in fig. 5b, a back-etching of the shielding conductor 205 selective to the first insulating layer 202 is employed such that the upper surface of the shielding conductor 205 is lower than the upper surface of the trench 203; the first insulating layer 204 is then etched such that the upper surface of the first insulating layer 204 is lower than the upper surface of the shield conductor 205.
Of course, in other embodiments, the shielding conductor may not be etched back, so that the upper surface of the shielding conductor is not lower than the upper surface of the trench 203.
Subsequently, in fig. 5c, a thermal oxidation technique is used to form an oxide layer, which is the gate dielectric layer 206, on the sidewalls of the upper portion of the trench, so that the sidewalls of the upper portion of the trench are covered by the formed gate dielectric layer 206. Meanwhile, in the thermal oxidation process, the shielding conductor 205 exposed by the first insulating layer 204 is also completely oxidized to be the second insulating layer 208, and the first insulating layer 204, the second insulating layer 208 and the gate dielectric layer 206 form a conformal shape. Wherein thermal oxidation techniques generally involve chemical reaction of silicon with a gas containing an oxidizing substance, such as water vapor and oxygen, at elevated temperatures to produce a dense layer of silicon dioxide (SiO) on the wafer surface2) Thin films in silicon planar technologyAn important process.
Further, the trench covered with the gate dielectric layer 206 is filled with a gate conductor 207 by low pressure chemical vapor deposition. Specifically, the gate conductor 207 fills the entire trench. The gate conductor is formed in an inverted concave shape in which the thickness of the middle is smaller than the thicknesses of both sides thereof, and particularly, the thickness of the gate conductor above the shield conductor is smaller than the thickness thereof above the first insulating layer, due to the presence of the shield conductor oxidized to the second insulating layer.
In another embodiment, when the upper surface of the shielding conductor 205 in the step of fig. 5b is lower than the upper surface of the trench 203 and the shielding conductor 205 exposed by the first insulating layer 204 in the step of fig. 5c is not completely oxidized, the width of the upper section of the shielding conductor exposed by the first insulating layer is smaller than that of the lower section thereof, and two sides of the upper section are covered with a second insulating layer formed by oxidation. After subsequent formation of the gate conductor, the structure of gate conductor 407 and shield conductor 405 is formed as shown in fig. 4. The gate conductor 407 includes two portions located on either side of the upper section of the shield conductor 405, separated from the shield conductor by a second insulating layer 408.
In another embodiment, when the upper surface of the shielding conductor 205 in the step of fig. 5b is not lower than the upper surface of the trench 203, and the shielding conductor 205 exposed by the first insulating layer 204 in the step of fig. 5c is completely oxidized, and then a gate conductor is formed, the gate conductor 307 and the shielding conductor 305 as shown in fig. 3 are formed, the upper surface of the shielding conductor 305 is lower than the lower surface of the gate conductor 307, and the shielding conductor 305 includes two separated parts separated from each other by a second insulating layer 308 formed by oxidizing the shielding conductor.
Subsequently, in fig. 2, a first ion implantation is performed using conventional body implantation and drive-in techniques to form a body region 209 of the second doping type in an upper region of the epitaxial semiconductor layer 202 adjacent the trench, said body region 209 extending from the upper surface of said epitaxial semiconductor layer 202 into the interior thereof. Further, a second ion implantation is performed to form a source region 210 of the first doping type in the body region 209, the source region 210 extends from the upper surface of the epitaxial semiconductor layer 202 to the inside thereof, and the junction depth of the source region 210 is smaller than that of the body region 209. Body region 209 is of the opposite type as epitaxial semiconductor layer 202. By controlling the parameters of the ion implantation, such as implantation energy and dose, the desired depth and the desired doping concentration can be achieved, the depth of the body region 209 not exceeding the extension depth of the gate conductor 207 in the trench. Preferably, body region 209 and source region 210 are adjacent to the trenches, respectively, and are separated by gate dielectric layer 206 and gate conductor 207. In the process of forming the body region 209 and the source region 210, the gate dielectric layer left on the upper surface of the epitaxial semiconductor layer 202 in the previous step is not removed, so that the surface of the epitaxial semiconductor layer 202 can be protected from being damaged in the ion implantation process.
An interlevel dielectric layer 216 is formed on the upper surface of the epitaxial semiconductor layer 202. In the present embodiment, specifically, a dielectric layer is formed on the upper surface of the epitaxial semiconductor layer 202; further chemical mechanical planarization is carried out, and a part of the dielectric layer is removed to obtain a flat surface. The interlayer dielectric layer 120 is an oxide layer, such as silicon oxide. The interlayer dielectric layer 216 may be formed by a deposition process. Of course, those skilled in the art may also use other methods to remove a portion of the dielectric layer to obtain a flat surface, and is not limited herein.
Subsequently, etching a part of the interlayer dielectric layer 216 and the gate conductor to form a first contact hole, and etching a part of the interlayer dielectric layer 216 and the source region 210 to form a second contact hole; and then carrying out third ion implantation, and forming a body contact region 211 in the body region 209 through the second contact hole by using a self-alignment process, wherein the body contact region 211 is positioned on the surface of the etched body region 209, and the body contact region 211 is of a second doping type. Metal is filled in the first contact hole and the second contact hole to form a gate conductive channel 212 and a source conductive channel 213, respectively. In this embodiment, the gate conductor in one trench corresponds to one or two gate conductive channels 212, and when the number of the gate conductive channels 212 is one, the gate conductive channels 212 are connected to any thicker portion of the gate conductor 207; when the number of the gate conductive paths 212 is two, the two gate conductive paths 212 are respectively connected to the two thicker portions of the gate conductor 207.
In another embodiment, when the gate conductor structures shown in fig. 3 and 4 are formed, the number of the gate conductive channels is two, and the two gate conductive channels are respectively connected with the two portions of the gate conductor.
Subsequently, metal is deposited on the interlayer dielectric layer 216 to form a gate metal electrode 215 and a source metal electrode 214, the gate metal electrode 215 being in contact with the gate conductor 207 through the gate conductive via 212, and the source metal electrode 214 being in contact with the source region 210 and the body contact region 211 through the source conductive via 213. Subsequently, the drain electrode 220 is formed on the second surface of the semiconductor substrate 201 thinned by the thinning technique by the above-described known deposition process.
In the above embodiments, the gate electrode 215, the source electrode 214, and the drain electrode 220 may be respectively formed of a conductive material including a metal material such as an aluminum alloy or copper.
According to the method for forming the trench MOSFET structure, provided by the invention, in the process of forming the gate dielectric layer, the shielding conductor exposed by the first insulating layer is also oxidized to form the second insulating layer, and then the gate conductor is deposited, so that the steps of the process are simplified, and the process cost is reduced. In addition, the grid conductive channel is arranged at the thicker parts of the two sides of the grid conductor so as to prevent the grid conductive channel from being positioned at the thinner part of the middle of the grid conductor to cause short circuit between the grid conductor and the shielding conductor and improve the reliability of the MOS.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (36)

1. A trench MOSFET, comprising:
a semiconductor substrate of a first doping type;
a trench extending from an upper surface of the semiconductor substrate to an inside thereof;
a first insulating layer and a shield conductor located inside the trench, the first insulating layer being located at a lower sidewall and a bottom of the trench and separating the shield conductor from the semiconductor substrate;
the grid conductor and the grid dielectric layer are positioned on the upper part of the groove, and the grid dielectric layer is positioned on the upper side wall of the groove and separates the grid conductor from the semiconductor substrate; and
a gate conductive channel connected to the gate conductor;
the thickness of the position of the gate conductor connected with the gate conductive channel meets the process requirement of the through hole and cannot be penetrated through.
2. The trench MOSFET of claim 1 wherein the gate conductor in one trench corresponds to one or both gate conductive channels.
3. The trench MOSFET of claim 1 wherein the gate conductive channel extends to a portion of the gate conductor where the gate conductor is thicker when the gate conductor has a different thickness in a vertical direction of the trench MOSFET.
4. The trench MOSFET of claim 1 wherein the gate conductor is located at least on an upper surface of the first insulating layer.
5. The trench MOSFET of claim 2 wherein the gate conductor and the shield conductor are isolated by a second insulating layer formed by oxidizing a portion of the shield conductor.
6. The trench MOSFET of claim 5 wherein an upper surface of the shield conductor is lower than a lower surface of the gate conductor.
7. The trench MOSFET of claim 5 wherein an upper surface of the shield conductor is no lower than a lower surface of the gate conductor.
8. The trench MOSFET of claim 6 wherein the gate conductor is inverted "concave" and the portion of the gate conductor overlying the shield conductor has a thickness less than the portion of the gate conductor overlying the first insulating layer.
9. The trench MOSFET of claim 6 wherein the gate conductor comprises a first portion and a second portion separated from each other, the first portion and the second portion being separated by the second insulating layer.
10. The trench MOSFET of claim 7 wherein the gate conductor includes first and second portions that are separated from each other, the first and second portions being located on either side of the shield conductor.
11. The trench MOSFET of claim 10 wherein an upper section of the shield conductor between the gate conductors has a width less than a width of a lower section of the shield conductor.
12. The trench MOSFET of claim 1 wherein the shield conductor is a polysilicon material.
13. The trench MOSFET of claim 8 wherein one of said gate conductive channels is in contact with any thicker portion of said gate conductor when the number of said gate conductive channels is one.
14. The trench MOSFET of claim 8 wherein when the number of said gate conductive channels is two, both of said gate conductive channels are in contact with the thicker portions of both of said gate conductors, respectively.
15. The trench MOSFET of claim 9 or 10 wherein there are two of said gate conductive channels, both of said gate conductive channels being in contact with said first portion and said second portion respectively.
16. The trench MOSFET of claim 1, further comprising:
an interlayer dielectric layer on the upper surface of the semiconductor substrate,
a gate metal electrode and a source metal electrode on the interlayer dielectric layer, an
A drain electrode on the lower surface of the semiconductor substrate,
wherein the gate metal electrode and the source metal electrode are spaced apart.
17. The trench MOSFET of claim 16 wherein the gate conductive via includes a contact hole extending from an upper surface of the interlevel dielectric layer into the gate conductor and a metal filling in the contact hole, the gate metal electrode contacting the gate conductor through the gate conductive via.
18. The trench MOSFET of claim 16, further comprising:
the body region of the second doping type is positioned on two sides of the groove, extends from the upper surface of the semiconductor substrate to the interior of the semiconductor substrate and is adjacent to the groove;
a source region of the first doping type located in the body region adjacent to the trench, an
A body contact region of a second doping type located in the body region.
19. The trench MOSFET of claim 18 further comprising a source region conductive via extending from an upper surface of said interlevel dielectric layer through said source region to said body contact region, said source metal electrode contacting said body contact region through said source region conductive via.
20. The trench MOSFET of claim 1 wherein the semiconductor base comprises a substrate of the first doping type and an epitaxial semiconductor layer of the first doping type on the substrate, the trench being in the epitaxial semiconductor layer.
21. A method of fabricating a trench MOSFET, comprising:
forming a groove extending from the upper surface to the interior of the groove in a semiconductor substrate, wherein the semiconductor substrate is of a first doping type;
forming a first insulating layer and a shielding conductor in the trench, wherein the first insulating layer is positioned on the lower side wall and the bottom of the trench and separates the shielding conductor from the semiconductor substrate, and the upper surface of the shielding conductor is higher than that of the first insulating layer;
forming a gate dielectric layer on the upper part of the trench and on the sidewall uncovered by the first insulating layer,
filling a grid conductor on the upper part of the groove, wherein the grid conductor is isolated from the semiconductor substrate by the grid dielectric layer;
and simultaneously when the gate dielectric layer is formed, the exposed part of the shielding conductor by the first insulating layer is also oxidized.
22. The method of claim 21, wherein the gate dielectric layer is formed by a thermal oxidation process.
23. The method of claim 21, wherein the shield conductor and the gate conductor are separated by a second insulating layer formed by oxidizing the shield conductor.
24. The method of claim 23, wherein one or two gate conductive channels are formed in connection with the gate conductor.
25. The method of claim 24 wherein when the top surface of the shield conductor is lower than the top surface of the trench and the exposed portion of the shield conductor is fully oxidized by the first insulating layer, the gate conductor forms an inverted "concave" shape, and the thickness of the portion of the gate conductor overlying the shield conductor is less than the thickness of the portion overlying the first insulating layer.
26. The method of claim 24 wherein the gate conductor is formed in two parts separated from each other and separated by the second insulating layer when the upper surface of the shield conductor is not lower than the upper surface of the trench and the exposed portion of the shield conductor is fully oxidized by the first insulating layer.
27. The method of claim 24, wherein when the upper surface of the shield conductor is lower than the upper surface of the trench and the portion of the shield conductor exposed by the first insulating layer is not completely oxidized, the gate conductor is located at two portions separated from each other and located at two sides of the non-oxidized shield conductor.
28. The method of claim 27, wherein an upper section of the shield conductor between the gate conductors has a width less than a width of a lower section of the shield conductor.
29. The method of claim 24, further comprising:
forming an interlayer dielectric layer on the upper surface of the semiconductor substrate;
forming a gate metal electrode and a source metal electrode on the upper surface of the interlayer dielectric layer, an
And forming a drain electrode positioned on the lower surface of the semiconductor substrate.
30. The method of claim 29, wherein forming the gate conductive channel comprises:
forming a contact hole extending from an upper surface of the interlayer dielectric layer to the gate conductor before forming the gate metal electrode; and
and filling metal in the contact hole.
31. The method of claim 25 wherein one of said gate conductive vias is in contact with any thicker portion of said gate conductor when the number of said gate conductive vias is one.
32. The method of claim 25, wherein when the number of the gate conductive paths is two, the two gate conductive paths are in contact with the thicker portions of the two gate conductors, respectively.
33. The method of claim 26 or 27, wherein the number of gate conductive paths is two, and the two gate conductive paths are in contact with the first portion and the first portion, respectively.
34. The method of claim 29, further comprising:
forming a body region of the second doping type, which is positioned at two sides of the groove and extends from the upper surface of the semiconductor substrate to the interior of the groove, wherein the body region is adjacent to the groove;
forming a source region of the first doping type in the body region adjacent to the trench, an
Forming a body contact region of a second doping type in the body region.
35. The method of claim 34, further comprising forming a source conductive via extending from an upper surface of the interlevel dielectric layer to the body contact region.
36. The method of claim 21 wherein the semiconductor base comprises a substrate of a first doping type and an epitaxial layer of the first doping type on the substrate, the trench being in the epitaxial layer.
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