CN113206090B - CFET structure, preparation method thereof and semiconductor device applying CFET structure - Google Patents

CFET structure, preparation method thereof and semiconductor device applying CFET structure Download PDF

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CN113206090B
CN113206090B CN202110300887.6A CN202110300887A CN113206090B CN 113206090 B CN113206090 B CN 113206090B CN 202110300887 A CN202110300887 A CN 202110300887A CN 113206090 B CN113206090 B CN 113206090B
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layer
type
channel structure
stack part
type channel
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CN113206090A (en
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罗彦娜
殷华湘
吴振华
张青竹
曹磊
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Institute of Microelectronics of CAS
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

The invention relates to a CFET structure, a preparation method thereof and a semiconductor device using the same, in particular to a method for providing a substrate, forming a basic fin structure on the substrate, forming a first stack part and a second stack part on the basic fin, wherein the second stack part is vertically stacked on the first stack part; the first stack part is provided with at least one I-shaped channel structure; the second stack part is provided with at least one II-type channel structure; the crystal plane direction of the I-type channel structure in the first stack part is perpendicular to the crystal plane direction of the II-type channel structure in the second stack part. Forming a first surrounding gate structure disposed around the I-channel structure; a second surrounding gate structure is formed that is disposed around the type II channel structure. Compared with the prior art, the invention has the beneficial technical effects that: the invention utilizes the method of combining side wall masking and selective step etching to realize the Vertical integration of Vertical Nano-sheet and Horizontal Nano-sheet, thereby achieving the purpose of simultaneously optimizing the crystal directions of NMOS and PMOS channels and simultaneously optimizing the performances of NMOS and PMOS on a single wafer.

Description

CFET structure, preparation method thereof and semiconductor device applying CFET structure
Technical Field
The present invention relates to the field of semiconductor integration technologies, and in particular, to a method for manufacturing a CFET structure and a semiconductor device.
Background
In a complementary field effect transistor (Complementary Field-Effect Transistor, CFET) device structure, an nFET and a pFET share a gate electrode as a signal input terminal and a drain electrode as a signal output terminal, with the source electrode being grounded and powered respectively. The vertical stack nanowire or nano-sheet surrounding grid electrode field effect transistor has the advantages of keeping the electrical integrity, greatly saving the area of a chip, enhancing the driving current of the device and improving the integration level of the chip device. The n and p vertical stacks greatly reduce the area of the CMOS circuit and realize ultra-high integration. Area scaling brings power and performance advantages. For electrostatic control, complementary Gate-All-Around (GAA) structures consisting of n, p vertical stacks, NFETs and PFETs can employ different crystal orientations, different channel materials to optimize NFET and PFET carrier mobility. Compared with the traditional transistor, the CFET has complete CMOS transistor function, is close to ideal subthreshold swing, extremely low leakage current, extremely low noise, smaller mobility deterioration and high reliability, and the GAA has better control on the gate, improves the performance and reduces the leakage.
In the CFET structure manufactured in the epitaxial channel mode at present, a PMOS is usually arranged at the bottom layer, and an NMOS is arranged at the top layer, so that a stress scheme is conveniently applied to the PMOS device at the bottom layer to improve the performance of the PMOS device; because the top-layer device cannot apply stress or the current stress scheme has low income, the top-layer NMOS device has poor performance, and the balance of NMOS and PMOS is difficult to regulate and control; in the CFET structure manufactured by the epitaxial channel mode at present, channel crystal planes of the NMOS and the PMOS are the same crystal plane, and mobility of electrons and holes cannot be optimized at the same time.
Disclosure of Invention
In order to overcome the technical problems, the invention discloses the following technical scheme:
a CFET structure, characterized by: comprising the following steps:
a substrate;
a first stack portion disposed on the substrate and having at least one I-channel structure;
a second stack portion vertically stacked on the first stack portion, and having at least one type II channel structure;
a first surrounding gate structure disposed around the I-channel structure;
a second surrounding gate structure disposed around the type II channel structure;
the crystal plane direction of the I-type channel structure in the first stack part is perpendicular to the crystal plane direction of the II-type channel structure in the second stack part.
A method of making a CFET device, comprising: the method comprises the following steps:
providing a substrate, forming a basic fin structure on the substrate,
forming a first stack portion and a second stack portion on the base fin, the second stack portion being vertically stacked on the first stack portion; the first stack part is provided with at least one I-shaped channel structure; the second stack part is provided with at least one II-type channel structure; the crystal face direction of the I-type channel structure in the first stack part is perpendicular to the crystal face direction of the II-type channel structure in the second stack part;
forming a first surrounding gate structure disposed around the I-channel structure;
a second surrounding gate structure is formed that is disposed around the type II channel structure.
Compared with the prior art, the invention has the beneficial technical effects that: the invention utilizes the method of combining side wall masking and selective step etching to realize the Vertical integration of Vertical Nano-sheet and Horizontal Nano-sheet, thereby achieving the purpose of simultaneously optimizing the crystal directions of NMOS and PMOS channels and simultaneously optimizing the performances of NMOS and PMOS on a single wafer. The device preparation flow is compatible with the mainstream MOS device process. According to the method for combining the side wall masking and the selective etching process, an additional photoetching process is not required to be introduced, and the flow is very simple; the formed top layer and bottom layer devices have the self-alignment characteristic of the channel by combining the side wall masking and the selective etching process, so that the control of the thickness and the width of the channel is greatly ensured; the formed Vertical Nano-sheet on Horizontal Nano-sheet structure can form channel structures with different crystal planes at the top layer and the bottom layer, can optimize mobility of electrons and holes at the same time, and achieves the effect of optimizing NMOS and PMOS devices at the same time; the bottom Horizontal Nano-sheet can apply stress to the device by using a conventional source-drain epitaxial stress scheme, so that the performance of the device is improved; the driving capability and performance of the device can be adjusted by increasing the number of the Nano-sheets and adjusting the width of the Nano-sheets by the bottom Horizontal Nano-sheet; the top layer Vertical Nano-sheet device can adjust the driving capability and performance of the top layer device by adjusting the height of the Nano-sheets and the number of the Nano-sheets; under the condition of not increasing the area, the top layer device is provided with two nano sheets, the bottom layer device is provided with one nano sheet, and in the structure of N on the lower P, the performance of the top layer NMOS device is greatly increased, so that NP balance is realized; the regulation and control of the number of the nano sheets of the top device can be realized by adopting a conventional Fin Cut process.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures.
Fig. 1 is a schematic diagram of a fabricated substrate of a CFET device of the present invention.
FIG. 2 is a schematic diagram of a top mold formed in accordance with the present invention.
FIG. 3 is a schematic illustration of the formation of an interfacial oxide layer according to the present invention.
Fig. 4 is a schematic view of forming a sidewall according to the present invention.
Fig. 5 is a schematic diagram of the present invention.
Fig. 6 is a schematic diagram of the present invention.
Fig. 7 is a schematic diagram of the present invention.
Fig. 8 is a schematic diagram of the present invention.
Fig. 9 is a schematic diagram of an etched superlattice laminate in accordance with the invention.
Figure 10 is a schematic illustration of the formation of shallow trench isolation in accordance with the present invention.
Fig. 11 is a schematic diagram of forming a dummy gate according to the present invention.
Fig. 12 is a schematic diagram of an etched superlattice laminate to form a horizontal conductive channel in accordance with the invention.
Fig. 13 is a schematic diagram of the present invention for channel release.
Fig. 14 is a schematic diagram of a CFET device of the present invention formed with a surrounding gate.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be understood that the description is only illustrative and is not intended to limit the scope of the invention. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the present invention.
Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present invention, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
In this embodiment, a method for fabricating a CFET device is provided. The combined diagram is a schematic diagram of a preparation process of the CFET device of the present invention, and the preparation process of the CFET device 100 includes:
providing a substrate 100;
the CFET device is prepared by starting with a base 101 and epitaxially growing a first step on a bottom-most substrate 101 of the base 100 to form a stack of a plurality of Si/SiGe superlattice structures, the substrate 101 being part of a semiconductor wafer suitable for forming one or more IC devices, for example, a silicon (Si) substrate may be employed. The thickness of each layer in the superlattice structure directly determines the height of the nanoplatelet channel and the electrostatic properties. In one embodiment, the stack of Si/SiGe superlattice structures is three cycles. The thickness of the SiGe layer 102 is greater than the thickness of the Si layer 101' in the remaining superlattice structure period except that the thickness of the Si sinker 101 is greater than the thickness of the SiGe layer 102 in the bottommost period, wherein the Si layer materials in the Si/SiGe superlattice structure are all type I Si, as shown in fig. 1.
A type II Si layer 103 is then deposited on the top surface of the uppermost SiGe layer 102 of the stack of Si/SiGe superlattice structures, the thickness of the type II Si layer 103 being the greatest in the substrate 100. An interface oxide layer 104 is formed on the upper surface of the II-type Si layer 103, the interface oxide layer 104 is SiO 2 A layer of silicon nitride (SiN) is deposited sequentially over the interfacial oxide layer 104 X ) Layer 105 and amorphous silicon layer (a-Si) 106, the preparation of substrate 100 to prepare the CFET device is completed. The deposition process may employ thermal oxidation, chemical vapor deposition, sputtering (sputtering), and the like.
Patterning the amorphous silicon layer (a-Si) 106 by photolithography, etching, etc., to form top molds 106', in one embodiment, the amorphous silicon layer (a-Si) 106 is formed in an equally spaced stripe pattern, exposing silicon nitride (SiN) between adjacent top molds 106 X ) The surface of layer 105 is shown in fig. 2.
Then at the top mold 106' and exposing silicon nitride (SiN) X ) The surface of layer 105 is deposited with an oxide, such as SiO, in one embodiment, by thermal oxidation, chemical vapor deposition, sputtering (sputtering), etc., to form an interfacial oxide layer 107 2 Layers, as shown in fig. 3.
Then, the interfacial oxide layer 107 on the upper surface of the top mold 106' is etched by an etching process, so that the interfacial oxide layers 107 on both sides of the top mold 106' form a sidewall 107', as shown in fig. 4.
Using the side wall 107 'and the top mold 106' as masks, the etching process is continued to etch silicon nitride (SiN) X ) Layer 105 and interfacial oxide layer 104 form a silicon nitride (SiN) layer in accordance with top-mold 106' patterning X ) A die 105' and an interfacial oxide die 104', adjacent interfacial oxide die 104' exposing the type II Si layer 103 as shown in fig. 5.
Continuing to etch the type II Si layer 103 with the sidewall 107' and the top mold 106' as masks, and partially etching the Ge layer on the uppermost portion of the Si/SiGe superlattice structure, and then etching away the top mold 105', as shown in fig. 6.
One or more side walls 107' are etched by adopting an etching process, so that the number of the top layer channels can be regulated and controlled. Continuing etching with the remaining sidewall 107' as a mask pair, etching silicon nitride (SiN) X ) The mold 105 'and the interfacial oxide mold 104' form silicon nitride (SiN) X ) The plug 105 "and the interfacial oxide plug 104" expose the type II Si layer 103 between adjacent interfacial oxide plugs 104", as shown in fig. 7 and 8.
The remaining sidewall 107 is used as a mask to continue etching the type II Si layer 103, and a plurality of top vertical conductive channels 103 "are formed in the type II Si layer 103. The vertical conduction channel 103"si crystal orientation is horizontal as shown in fig. 9. In one embodiment, the number of vertical conductive channels 103' is an odd number.
The first sidewall 107' is then etched away, silicon nitride (SiN X ) Mandrel 105 "and interfacial oxide mandrel 104" and etching of the stack of Si/SiGe superlattice structures continues to the substrate 101 layer such that the substrate 101 layer is partially etched. To this end, a plurality of periodically distributed fins are formed. Shallow trench isolation (Shallow Trench Isolation, STI) 108 is disposed between two adjacent fins, and in one embodiment the shallow trench isolation (Shallow Trench Isolation, STI) 108 is formed of SiO 2 Its function is to isolate adjacent transistors as shown in fig. 10.
A sacrificial oxide layer 109 is then deposited on the surface of the fin, the sacrificial oxide layer 109 being, in one embodiment, siO 2 . Dummy gates 110 are formed which are periodically distributed in a direction perpendicular to the previous fin line. The material used for the dummy gate 110 may be, for example, polysilicon (PolySi), as shown in fig. 11.
The fins between the gates need to be cleaned completely, and the cleaned space is used for the growth of the source and drain in later steps. The SiGe material exposed at the surface is etched in, for example, by isotropic etching, and the etching process includes isotropic etching to etch uniformly in any direction. For example isotropic, gas phase etching. Such vapor phase etching may have a chemical composition of 100: 1.
And performing epitaxial growth of source/drain (S/D) on the Si surface between the cleaned grid electrodes. In the case of pFET, the source and drain materials are boron doped SiGe (SiGe: B), and in the case of nFET, the source and drain materials are phosphorus doped SiC (SiC: P): the method comprises the steps of firstly epitaxially growing a source electrode/drain electrode on a lower FET, then depositing an insulating medium, layering the upper FET and the lower FET, flattening the insulating medium, and connecting the source electrode and the drain electrode of the lower FET device to a BPR by adopting an etching process.
The dummy gate and the sacrificial oxide layer 109 formed of polysilicon (PolySi) are etched by an etching process, i.e., the dummy gate is removed, and the channel is released, thereby forming a horizontal conductive channel 101". The Si crystal orientation of the horizontal conductive channel 101 "is vertical as shown in fig. 12-13.
Forming a first stack part for the FET with the horizontal conducting channel on the lower layer of the substrate, and forming a second stack part for the FET with the vertical conducting channel on the upper layer; the first stack portion has at least one I-channel structure 101"; the second stack portion has at least one type II channel structure 103".
A surrounding gate structure is then formed around each of the released channel materials. In one embodiment, the type I and type II surrounding gate structures may be electrically connected such that they are complementary to each other; the I-shaped surrounding grid structure is completely arranged around the I-shaped channel structure; and a type II surrounding gate structure disposed entirely around the type II channel structure;
an interfacial layer 1012 and a metal work function layer 1011 are formed around the type I channel structure, type II channel structure by deposition, and the high-k dielectric layer may comprise a silicon oxide gate oxide. In one embodiment, a type I metal gate work function layer is deposited on the high-K dielectric layer of the outer layer of the type I channel structure, and a type II metal gate work function layer is deposited on the high-K dielectric layer of the outer layer of the type II channel structure.
The cleaned dummy gate space is then deposited with a conductive metal layer 1013. The conductive metal layer may deposit tungsten (W) or cobalt (Co).
In one embodiment, the type I channel is an nFET channel and the type II channel is a pFET channel, then the type I metal gate work function layer is Al, tiAl, tiAlx, tiAlCx, tiCx, taCx or a composite of several layers and the type II metal gate work function layer is TiN, taN, tiNx, taNx, tiNSi or a composite of several layers.
In one embodiment, the type I channel is a pFET channel and the type II channel is an nFET channel, the type I metal gate work function layer is TiN, taN, tiNx, taNx, tiNSi or a composite of several layers, and the type II metal gate work function layer is Al, tiAl, tiAlx, tiAlCx, tiCx, taCx or a composite of several layers.
The thickness of the metal gate work function layer outside the I, II type FET stacked up and down by the process CEFT device of the present embodiment is adjusted to adjust the threshold of the I, II type FET.
The CEFT device adjusts different N/PFET device thresholds by adjusting the thicknesses of the I-type metal gate work function layer and the II-type metal gate work function layer.
According to one embodiment of the present invention, a CFET device structure is provided, an exemplary structure of the CFET of the present invention is shown in fig. 14. As shown in fig. 14, the CFET device includes:
a substrate;
a first stack portion disposed on the substrate and having at least one I-channel structure;
a second stack portion vertically stacked on the first stack portion, and having at least one type II channel structure;
a first surrounding gate structure disposed around the I-channel structure;
a second surrounding gate structure disposed around the type II channel structure;
the crystal plane direction of the I-type channel structure in the first stack part is perpendicular to the crystal plane direction of the II-type channel structure in the second stack part.
The first stack portion includes one or more type I nfets and the second stack portion includes one or more pfets, or the first stack portion includes one or more nfets and the second stack portion includes one or more pfets.
The CEFT device structure described in the embodiments of the present invention may be prepared by the method described in the previous embodiments of the present invention, and based on the method described in the first embodiment of the present invention, a person skilled in the art can understand the specific structure and deformation of the device, so that the description thereof will not be repeated here.
The invention also discloses a semiconductor device, which comprises the CFET structure.
The technical scheme in the embodiment of the application at least has the following technical effects or advantages: the invention utilizes the method of combining side wall masking and selective step etching to realize the Vertical integration of Vertical Nano-sheet and Horizontal Nano-sheet, thereby achieving the purpose of simultaneously optimizing the crystal directions of NMOS and PMOS channels and simultaneously optimizing the performances of NMOS and PMOS on a single wafer. The device preparation flow is compatible with the mainstream MOS device process. According to the method for combining the side wall masking and the selective etching process, an additional photoetching process is not required to be introduced, and the flow is very simple; the formed top layer and bottom layer devices have the self-alignment characteristic of the channel by combining the side wall masking and the selective etching process, so that the control of the thickness and the width of the channel is greatly ensured; the formed Vertical Nano-sheet on Horizontal Nano-sheet structure can form channel structures with different crystal planes at the top layer and the bottom layer, can optimize mobility of electrons and holes at the same time, and achieves the effect of optimizing NMOS and PMOS devices at the same time; the bottom Horizontal Nano-sheet can apply stress to the device by using a conventional source-drain epitaxial stress scheme, so that the performance of the device is improved; the driving capability and performance of the device can be adjusted by increasing the number of the Nano-sheets and adjusting the width of the Nano-sheets by the bottom Horizontal Nano-sheet; the top layer Vertical Nano-sheet device can adjust the driving capability and performance of the top layer device by adjusting the height of the Nano-sheets and the number of the Nano-sheets; under the condition of not increasing the area, the top layer device is provided with two nano sheets, the bottom layer device is provided with one nano sheet, and in the structure of N on the lower P, the performance of the top layer NMOS device is greatly increased, so that NP balance is realized; the regulation and control of the number of the nano sheets of the top device can be realized by adopting a conventional Fin Cut process.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present invention are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the invention, and such alternatives and modifications are intended to fall within the scope of the invention.

Claims (9)

1. A method of making a CFET device, comprising: the method comprises the following steps:
s1, providing a substrate; epitaxially growing a superlattice laminate on the substrate, the superlattice laminate including an I-channel layer therein;
s2, sequentially depositing a II-type channel layer, a first interface oxide layer, a silicon nitride layer and an amorphous silicon layer on the upper surface of the laminated layer of the superlattice;
s3, patterning the amorphous silicon layer through photoetching and etching processes to form a top die, and depositing a second interface oxide layer on the top die and the surface of the exposed silicon nitride layer;
s4, etching the second interface oxide layers on the upper surface of the top die, so that the second interface oxide layers on the two sides of the top die form side walls;
s5, continuing to etch the silicon nitride layer and the first interface oxide layer by taking the side wall and the top die as masks to form a silicon nitride die and an interface oxide die;
s6, etching the II-type channel layer and the superlattice laminate by taking the side wall and the top mould as masks to form an I-type channel structure of the first stack part, and then etching away the top mould and part of the side wall;
s7, continuing etching by taking the reserved side wall as a mask pair, and etching a silicon nitride mandrel and an interface oxidation mandrel formed by the silicon nitride die and the interface oxidation die until a II-type channel layer is exposed between adjacent interface oxidation mandrels, so as to form a II-type channel structure of a second stack part;
s8, etching the side wall, the silicon nitride core die and the interface oxidation core die which are reserved, and continuing etching the superlattice lamination to the substrate layer, so that the substrate layer is partially etched, and a plurality of fins distributed periodically are formed;
s9, making periodically distributed dummy gates in the direction perpendicular to the fin line;
s10, forming an I-shaped surrounding grid structure which is completely arranged around the I-shaped channel structure; and a type II surrounding gate structure disposed entirely around the type II channel structure; the crystal plane direction of the I-type channel structure in the first stack part is perpendicular to the crystal plane direction of the II-type channel structure in the second stack part.
2. The method according to claim 1, characterized in that: the crystal face direction of the I-type channel structure in the first stack part is vertical, and the crystal face direction of the II-type channel structure in the second stack part is horizontal.
3. The method according to claim 1 or 2, characterized in that: the I-type channel structure is an nFET channel and the II-type channel structure is a pFET channel.
4. The method according to claim 1 or 2, characterized in that: the I-type channel structure is a pFET channel and the II-type channel structure is an nFET channel.
5. The method according to claim 1 or 2, characterized in that: the I-type surrounding grid structure and the II-type surrounding grid structure are electrically connected to form a complementary field effect transistor.
6. The method according to claim 1 or 2, characterized in that: the I-type channel structure is formed of I-type Si and the II-type channel structure is formed of II-type Si.
7. The method according to claim 1, characterized in that: the I-type surrounding grid structure comprises an I-type metal grid work function layer; the type II surrounding gate structure includes a type II metal gate work function layer.
8. The method according to claim 7, wherein: the I-type metal gate work function layer is a TiN, taN, tiNx, taNx, tiNSi layer or a composite layer of a plurality of layers.
9. The method according to claim 8, wherein: the II-type metal gate work function layer is a Al, tiAl, tiAlx, tiAlCx, tiCx, taCx layer or a composite layer of a plurality of layers.
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