CN113205851A - Shift register based on RAM and storage method thereof - Google Patents
Shift register based on RAM and storage method thereof Download PDFInfo
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Abstract
The invention provides a shift register based on a RAM (random access memory), which comprises a first adder, a second adder, a first flip-flop and a dual-port RAM, wherein a data input port of the flip-flop is connected with an output port of the second adder, an output port of the first flip-flop is respectively connected with an address input port of the first adder, an address input port of the second adder and a write address logic port of the dual-port RAM, an output port of the first adder is connected with a read address logic port of the RAM, an output port D0 of the dual-port RAM outputs data, a CLK (clock) port of the first flip-flop and a CLK (clock) port of the dual-port RAM input clock signals, an enable port of the first flip-flop and an enable port of the dual-port RAM input enable signals, and an address input end of the first adder inputs or dynamic data. Compared with the prior art, the invention can save the logic resource of the FPGA.
Description
Technical Field
The invention belongs to the technical field of register transmission level synthesis, and particularly relates to a shift register based on an RAM (random access memory) and a storage method thereof.
Background
The SRL (Shift Register Level) is a circuit commonly used in RTL (Register Transistor Level) design, and the integration and optimization of the SRL are important components of the RTL integration for an FPGA (Field Programmable Gate Array). When the scale of the SRL circuit design is large, or there is no SRL process library unit in the synthesis library, the circuit optimization implementation based on RAM (Random Access Memory) is a problem that must be solved for SRL synthesis. Two mainstream foreign commercial integrated software are taken as examples to illustrate the SRL scheme in the prior art.
The first is Xilinx's synthesis tool (ISE or Vivado) in which only netlists based on its SRL process library elements are generated for the user's SRL design. However, when the size of the user's SRL is large (the propagation chain length is long), the netlist generated by the user must be a cascade of many levels of SRL process library cells. The resulting performance of the circuit is poor compared to a RAM-based circuit implementation.
The second is an FPGA general purpose EDA tool, such as Synplify, for Xilinx FPGA, a netlist based on SRL process library units can be generated; for a Lattice FPGA, since there are no SRL process library cells in its process library, a netlist based on DRAM (Distributed RAM) can be generated for the user static SRL. However, there are the following problems:
(1) when the library has an SRL process library unit, only generating an SRL process library unit netlist without balancing SRL/RAM, which inevitably has the same problem as the Xilinx synthesis tool;
(2) for larger users SRL, the implementation should be based on RAM. However, Synplify only handles static SRLs and cannot handle dynamic SRLs; for dynamic SRL, it simply generates a cascaded netlist based on FF (flip-flops); the FF belongs to the general logic unit of the FPGA, which causes waste of the general logic unit;
(3) even for static SRL, synchronization can only generate a DRAM-based netlist, but cannot generate a BRAM (Block RAM) based netlist according to the intrinsic characteristics of the user SRL. While the use of DRAM is actually equivalent to the use of a universal Logic Unit (LUT), this "waste" of the universal logic unit can be significant when the user SRL is large.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a shift register based on a RAM and a storage method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
in a first aspect, the present invention provides a RAM-based shift register, comprising: a first adder, a second adder, a first flip-flop and a dual port RAM, the first and second adders including an address input port, a first input port and an output port, the first flip-flop including an input data port, a CLK port, an enable port and an output port, the dual port RAM including a write address logic port, a read address logic port, a data input port, an enable port and a CLK port, the data input port of the flip-flop being coupled to the output port of the second adder, the output port of the first flip-flop being coupled to the address input port of the first adder, the address input port of the second adder and the write address logic port of the dual port RAM, respectively, the output port of the first adder being coupled to the read address logic port of the RAM, the output port (D0) of the dual port RAM outputting data, clock signals are input into a CLK port of the first flip-flop and a CLK port of the dual-port RAM, enable signals are input into an enable port of the first flip-flop and an enable port of the dual-port RAM, and constant or dynamic data are input into an address input end of the first adder.
Optionally, the width of the output port of the dual-port RAM is m, and the width of the address input end of the first adder is n.
In a second aspect, the present invention provides a shift register based on RAM, including: the data input port of the second flip-flop is connected with the output port of the third adder, the output port of the second flip-flop is connected with the address input end of the third adder and the address input end of the single-port RAM, clock signals are input into the CLK ends of the second flip-flop and the single-port RAM, data are input into the data input end of the single-port RAM, and data are output from the output end of the single-port RAM.
Optionally, the single-port RAM is a shift register for synchronous writing and asynchronous reading, and the single-port RAM is driven by a second flip-flop to input a signal to an address input port of the single-port RAM through an output port of the single-port RAM.
In a third aspect, the present invention provides a storage method for a shift register based on a RAM, which provides a shift register, and the storage method includes:
acquiring user requirements;
the shift register is used for storing data to be stored in user requirements;
wherein the shift register includes: a first adder, a second adder, a first flip-flop and a dual port RAM, the first and second adders including an address input port, a first input port and an output port, the first flip-flop including an input data port, a CLK port, an enable port and an output port, the dual port RAM including a write address logic port, a read address logic port, a data input port, an enable port and a CLK port, the data input port of the flip-flop being coupled to the output port of the second adder, the output port of the first flip-flop being coupled to the address input port of the first adder, the address input port of the second adder and the write address logic port of the dual port RAM, respectively, the output port of the first adder being coupled to the read address logic port of the RAM, the output port (D0) of the dual port RAM outputting data, clock signals are input into a CLK port of the first flip-flop and a CLK port of the dual-port RAM, enable signals are input into an enable port of the first flip-flop and an enable port of the dual-port RAM, and constant or dynamic data are input into an address input end of the first adder.
In a fourth aspect, the present invention provides a storage method for a shift register based on a RAM, which provides a shift register, and the storage method includes:
acquiring user requirements; the user requirements comprise data to be stored;
determining the length of a required static shift register based on the user requirement;
when the required length of the static shift register is 2nThen, the shift register is used for storing data;
when the length of the required static shift register is more than 2nDetermining the number of the shift registers based on the length of the static shift register;
sequentially connecting a plurality of shift registers in series;
storing data by using a plurality of shift registers connected in series;
wherein, shift register includes: the data input port of the second flip-flop is connected with the output port of the third adder, the output port of the second flip-flop is connected with the address input end of the third adder and the address input end of the single-port RAM, clock signals are input into the CLK ends of the second flip-flop and the single-port RAM, data are input into the data input end of the single-port RAM, data are output from the output end of the single-port RAM, and n is the width of the address input port of the RAM.
Optionally, the length of the required static shift register is greater than 2nBased on the static shift registerThe step of determining the number of shift registers comprises:
when the length of the required static shift register is more than 2nConverting the length of the static shift register into the sum of powers of 2;
and counting the number of the powers of 2, and determining the number as the number of the shift registers.
The invention provides a shift register based on a RAM (random access memory), which comprises a first adder, a second adder, a first flip-flop and a dual-port RAM, wherein a data input port of the flip-flop is connected with an output port of the second adder, an output port of the first flip-flop is respectively connected with an address input port of the first adder, an address input port of the second adder and a write address logic port of the dual-port RAM, an output port of the first adder is connected with a read address logic port of the RAM, an output port D0 of the dual-port RAM outputs data, a CLK (clock) port of the first flip-flop and a CLK (clock) port of the dual-port RAM input clock signals, an enable port of the first flip-flop and an enable port of the dual-port RAM input enable signals, and an address input end of the first adder inputs or dynamic data. Compared with the prior art, the invention can save the logic resource of the FPGA.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of an internal structure of a shift register based on a RAM according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an external structure of a RAM-based shift register according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another RAM-based shift register according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of the change of the internal circuit of the shift register for FF absorption and BRAM generation provided by the embodiment of the present invention;
FIG. 5 is a flow chart of a storage method of a RAM-based shift register according to an embodiment of the present invention;
fig. 6 is a flowchart of another storage method of a shift register based on a RAM according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
As shown in fig. 1, the shift register based on RAM provided by the present invention includes: the first adder, the second adder, the first flip-flop and the dual-port RAM, the first adder and the second adder including an address input port A, a first input port B and an output port S, the first flip-flop including an input data port D, CLK port, an enable port CE and an output port Q, the dual-port RAM including a write address logic port WADDR, a read address logic port RADDR, a data input port DI, an enable port WE, a CLK port and an output port D0, the data input port of the flip-flop being connected to the output port of the second adder, the output port of the first flip-flop being connected to the address input port of the first adder, the address input port of the second adder and the write address logic port of the dual-port RAM, respectively, the output port of the first adder being connected to the read address logic port of the RAM, the output port D0 of the dual-port RAM outputs data, the CLK port of the first flip-flop and the CLK port of the dual-port RAM input clock signals, the enable port of the first flip-flop and the enable port of the dual-port RAM input enable signals, and the address input end of the first adder inputs constant or dynamic data.
The width of the output port of the dual-port RAM is m, and the width of the address input end of the first adder is n.
Referring to fig. 2, the present invention provides an abstract of a RAM-based shift register into a general, abstract SRL model. In fig. 2, the width of the data input port D and the data output port Q is m; if the width of the address input port addr is n, the length of the SRL is 2 n; CLK is a clock input port; the clock enabled CE port is optional. If the input of addr is a constant, then SRL is static SRL; otherwise dynamic SRL.
Referring to fig. 1, the internal structure circuit of a shift register based on RAM according to the present invention includes three parts:
1. a dual port RAM section. This is a synchronously writing, asynchronously reading DPR (Dual-Port RAM, Dual Port RAM, RAM with two independent addresses or two independent clocks);
2. flip-flop FF and an adder implementing waddr + 1. They are used to generate write addresses for the RAM;
3. an adder of waddr + addr-1 is implemented. They are used to generate read addresses for RAM
The above netlist in fact simulates the behavior of the SRL: the write address logic (waddr) is effectively a counter, implementing Q ═ Q +1, so that each memory bit is periodically written incrementally, as the SRL gradually passes each original data D from the initial FF to the last FF; the read address logic (raddr) generates waddr + addr-1 to implement the Q ═ RAM [ addr ] function with the RAM.
The shift register based on the RAM has the following characteristics:
1. origin of addr
Note that the read address logic is waddr + addr-1, and the logic addr-1 is-addr. Where addr denotes the bit-wise negation of addr. Thus one input to the read address adder (raddr) in the above figure is addr. This translation/reduction saves more logic resources than waddr + addr-1.
2. The area of the glue logic is only proportional to the length of the SRL
Here, the sticky logic refers to the circuits in fig. 1 except the RAM portion, i.e., the two adders and FF.
In a RAM-based implementation, the area of the glue logic is only proportional to the width of addr of the SRL, i.e., "n" in the upper figure.
For example, assuming that the length of one SRL is 42, the width of addr is 6 (32)<42<64＝26) Then both adders are 6 bits wide and FF is also 6 bits.
3. Area of RAM proportional to data width and length of SRL
In a RAM-based implementation, the area of the RAM is proportional to the size of the SRL, i.e., the data width and the length of the SRL.
For example, for an SRL32X42, i.e., an SRL of width 32 and length 42, the RAM in fig. 1 would be RAM32X64, where 32 is the data width of the RAM and 64 is the depth of the RAM. Assuming that there are RAM library cells DPR4X16 in a certain FPGA process library and this RAM32X64 is implemented with it, finally 32 DPRs 4X16 will be used: (data width of RAM) 32 ═ 4X 8 (data width of DPR4X 16), (depth of RAM) 64 ═ 16X 4 (depth of DPR4X 16), and the DPR4X16 number is 32 ═ 8X 4.
4. CE of SRL is to act on CE of generated FF and write enable WE of RAM simultaneously
When a CE is present in the SRL, this CE must act on both FF and RAM in the generating circuit: CE for FF and WE for RAM. So that the consistency of the generated circuit and the original SRL logic is guaranteed.
When the length of the static SRL is 2nThen the DPR-based scheme in fig. 1 can be "degenerated" to an SPR (Single-Port RAM, RAM with only one address and one clock) scheme. Thus, not only can the RAM itself save resources, but also the adder that generates the read address in the glue logic can be eliminated, thereby reducing the required glue logic resources. Furthermore, if the length of the SRL is large, so that the generated RAM itself is large, because the FF of the scheme directly drives the ADDR port of the RAM, the SPR can be split into the DPRs first, and the asynchronous read port absorbs the fanning-in FF, so that the originally generated DRAM can be changed into the BRAM, thereby effectively utilizing the BRAM resource in the FPGA and further saving the logic resource.
The invention provides a shift register based on a RAM (random access memory), which comprises a first adder, a second adder, a first flip-flop and a dual-port RAM, wherein a data input port of the flip-flop is connected with an output port of the second adder, an output port of the first flip-flop is respectively connected with an address input port of the first adder, an address input port of the second adder and a write address logic port of the dual-port RAM, an output port of the first adder is connected with a read address logic port of the RAM, an output port D0 of the dual-port RAM outputs data, a CLK (clock) port of the first flip-flop and a CLK (clock) port of the dual-port RAM input clock signals, an enable port of the first flip-flop and an enable port of the dual-port RAM input enable signals, and an address input end of the first adder inputs or dynamic data. Compared with the prior art, the invention can save the logic resource of the FPGA.
Example two
As shown in fig. 3, the shift register based on RAM provided by the present invention includes: the data input port of the second flip-flop is connected with the output port of the third adder, the output port of the second flip-flop is connected with the address input end of the third adder and the address input end of the single-port RAM, clock signals are input into the CLK ends of the second flip-flop and the single-port RAM, data are input into the data input end of the single-port RAM, and data are output from the output end of the single-port RAM.
The single-port RAM is a shift register for synchronous writing and asynchronous reading, and is driven by a second trigger through an address input port of the single-port RAM by inputting a signal to an output end of the second trigger.
When the length of the static SRL is 2nFor example, if length is 16, addr in fig. 1 is 15(16-1), and — (' b1111) ═ b0000 is 0, and then raddr ═ waddr +0 ═ waddr is waddr, the read address adder can be omitted, and the original DPR becomes SPR because raddr and waddr are the same.
The RAM in fig. 3 is synchronously writing and asynchronously reading, and its ADDR is driven by FF, so this FF can be absorbed, so that the DRAM generated at this time becomes BRAM, the specific change process is shown in fig. 4, since ADDR of RAM is driven by FF, it is first split by port, SPR becomes DPR, and ADDR of each port is driven by original FF, as shown in fig. 3 (B); the asynchronous read port then absorbs its fan-in FF to become the synchronous read port, so that the original DRAM becomes BRAM, as shown in FIG. 3 (C).
BRAM scales are large relative to typical SRLs. Therefore, the DRAM can be changed into BRAM only when the size of SRL reaches a certain threshold, otherwise, the resource of BRAM is wasted. When the static SRL is not large enough, it is still generated by DRAM.
The invention provides a shift register based on RAM, comprising: a second flip-flop, a third adder, and a single port RAM, the second flip-flop including an input data port, a CLK port, and an output port, the third adder comprising an address input port, a first input port, and an output port, the single port RAM comprising an address input port, a data input port, a CLK port, and a data output port, the data input port of the second flip-flop is connected with the output port of the third adder, the output port of the second flip-flop is connected with the address input end of the third adder and the address input end of the single-port RAM, the clock signal is input into the second flip-flop and the CLK terminal of the single-port RAM, data is input into the data input terminal of the single-port RAM, the output end of the single-port RAM outputs data, the invention can be realized by BRAM through conversion, and the occupation of the SRL on the logic resource of a common FPGA can be greatly saved.
EXAMPLE III
As shown in fig. 5, the storage method of a shift register based on a RAM provided by the present invention provides a shift register, and the storage method includes:
s51, acquiring user requirements;
s52, storing the data to be stored in the user requirement by using the shift register;
wherein the shift register includes: a first adder, a second adder, a first flip-flop and a dual port RAM, the first and second adders including an address input port, a first input port and an output port, the first flip-flop including an input data port, a CLK port, an enable port and an output port, the dual port RAM including a write address logic port, a read address logic port, a data input port, an enable port and a CLK port, the data input port of the flip-flop being coupled to the output port of the second adder, the output port of the first flip-flop being coupled to the address input port of the first adder, the address input port of the second adder and the write address logic port of the dual port RAM, respectively, the output port of the first adder being coupled to the read address logic port of the RAM, the output port (D0) of the dual port RAM outputting data, clock signals are input into a CLK port of the first flip-flop and a CLK port of the dual-port RAM, enable signals are input into an enable port of the first flip-flop and an enable port of the dual-port RAM, and constant or dynamic data are input into an address input end of the first adder.
The storage method of the shift register based on the RAM provided by the invention has the advantages that the conversion/simplification of the shift register is realized, and the logic resource is saved.
Example four
For the length of the shift register, there is the following analysis:
if SRL length is 2nSPR is used for realizing the method without DPR, so that the area of bonding logic is saved;
second, if the SPR is large enough, it can be implemented by BRAM instead of DRAM, which can greatly save general logic resources.
For static SRL, unlike dynamic SRL, it is essentially a constant length chain of cascaded FFs without any other logic.
In general, the length of an SRL is rarely exactly 2n. Based on the above three points, however, if the length of an SRL is relatively large, it is not 2nIt can be split, i.e. the original FF chain is split into a series of FF chains of different lengths, but of length 2nAnd further, these sub-SRLs may be implemented using BRAM or SPR, respectively. We refer to this process as length splitting of SRL.
Such a substantial portion of an original large, generic-length SRL may be implemented with BRAM and/or SPR, which may effectively save logic resources compared to a complete DPR implementation.
As shown in fig. 6, the storage method of a shift register based on a RAM provided by the present invention includes:
s61, acquiring user requirements; the user requirements comprise data to be stored;
s62, determining the length of the required static shift register based on the user requirement;
s63, when the length of the required static shift register is 2nThen, the shift register is used for storing data;
s64, when the length of the required static shift register is more than 2nDetermining the number of the shift registers based on the length of the static shift register;
s65, sequentially connecting a plurality of shift registers in series;
s66, storing data by using a plurality of shift registers connected in series;
wherein, shift register includes: the data input port of the second flip-flop is connected with the output port of the third adder, the output port of the second flip-flop is connected with the address input end of the third adder and the address input end of the single-port RAM, clock signals are input into the CLK ends of the second flip-flop and the single-port RAM, data are input into the data input end of the single-port RAM, and data are output from the output end of the single-port RAM.
With respect to area, delay and power consumption
Splitting is generally beneficial for area reduction:
1. the use of BRAM can greatly reduce the use of DRAM, thereby reducing the number of LUTs that will be occupied last, since DRAM is generally equivalent to LUT;
2. even with DRAM instead of BRAM, splitting means the use of more SPR than DPR, whereas in general the area of DPR of the same size is 2 times SPR; even more, the use of SPR implies a reduction in the use of one adder in the glue logic;
3. splitting results in a slight increase in the number of FFs, since the presence of each stage implies a set of glue logic, and the sum of the stages necessarily results in the generation of slightly more FFs.
Splitting means serial implementation, without necessarily using latency. Since the RAM portion is only one RAM block when implemented with only DPRs, the final implementation is that some banks in parallel are unique to RAM and a MUX. On the contrary, when the sub SRL is split into a plurality of cascaded sub SRLs, each sub SRL corresponds to one RAM block, and these cascaded RAM blocks inevitably cause relative deterioration of the delay. Especially when BRAM is used, the delay is worse a little bit.
On the other hand, the use of RAM, whether DRAM or BRAM, helps to save power consumption, especially when SRLs are both implemented with FFs and are relatively large in length.
The invention provides a storage method of a shift register based on a RAM, which uses the shift register of the second embodiment and obtains user requirements; the user requirements comprise data to be stored; determining the length of a required static shift register based on the user requirement; when the required length of the static shift register is 2nThen, the shift register is used for storing data; when the length of the required static shift register is more than 2nDetermining the number of the shift registers based on the length of the static shift register; sequentially connecting a plurality of shift registers in series; and storing the data by using a plurality of shift registers connected in series. Compared with the prior art, the invention determines whether to split according to the length of the SRL required by the user, and finally determines the number of the shift registers according to the splitting result, so as to finish the storage by series connection. Thus, resources can be saved.
Example four
As an alternative to the present inventionIn one embodiment, the required length of the static shift register is greater than 2nThe step of determining the number of shift registers based on the length of the static shift register may comprise:
step a: when the length of the required static shift register is more than 2nConverting the length of the static shift register into the sum of powers of 2;
step b: and counting the number of the powers of 2, and determining the number as the number of the shift registers.
For example, assuming that the length of a static SRL is 4998, the split can be made as follows:
4998＝4096(212)+512(29)+256(28)+128(27)+6
if the threshold depth of the BRAM is 512, two sub-SRLs of length 4096 and 512 can be implemented with 2 BRAMs, while two sub-SRLs of 256, 128 can be implemented with SPR.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (7)
1. A RAM-based shift register, comprising: a first adder, a second adder, a first flip-flop and a dual port RAM, the first and second adders including an address input port, a first input port and an output port, the first flip-flop including an input data port, a CLK port, an enable port and an output port, the dual port RAM including a write address logic port, a read address logic port, a data input port, an enable port and a CLK port, the data input port of the flip-flop being coupled to the output port of the second adder, the output port of the first flip-flop being coupled to the address input port of the first adder, the address input port of the second adder and the write address logic port of the dual port RAM, respectively, the output port of the first adder being coupled to the read address logic port of the RAM, the output port (D0) of the dual port RAM outputting data, clock signals are input into a CLK port of the first flip-flop and a CLK port of the dual-port RAM, enable signals are input into an enable port of the first flip-flop and an enable port of the dual-port RAM, and constant or dynamic data are input into an address input end of the first adder.
2. The shift register of claim 1, wherein the output port of the dual port RAM has a width of m and the address input of the first adder has a width of n.
3. A RAM-based shift register, comprising: the data input port of the second flip-flop is connected with the output port of the third adder, the output port of the second flip-flop is connected with the address input end of the third adder and the address input end of the single-port RAM, clock signals are input into the CLK ends of the second flip-flop and the single-port RAM, data are input into the data input end of the single-port RAM, and data are output from the output end of the single-port RAM.
4. The shift register of claim 3, wherein the single-port RAM is a synchronous-write, asynchronous-read shift register, and the single-port RAM is driven by a second flip-flop via its own output input signal to an address input port of the single-port RAM.
5. A storage method of a shift register based on a RAM (random access memory) is provided, and is characterized by comprising the following steps:
acquiring user requirements;
the shift register is used for storing data to be stored in user requirements;
wherein the shift register includes: a first adder, a second adder, a first flip-flop and a dual port RAM, the first and second adders including an address input port, a first input port and an output port, the first flip-flop including an input data port, a CLK port, an enable port and an output port, the dual port RAM including a write address logic port, a read address logic port, a data input port, an enable port and a CLK port, the data input port of the flip-flop being coupled to the output port of the second adder, the output port of the first flip-flop being coupled to the address input port of the first adder, the address input port of the second adder and the write address logic port of the dual port RAM, respectively, the output port of the first adder being coupled to the read address logic port of the RAM, the output port (D0) of the dual port RAM outputting data, clock signals are input into a CLK port of the first flip-flop and a CLK port of the dual-port RAM, enable signals are input into an enable port of the first flip-flop and an enable port of the dual-port RAM, and constant or dynamic data are input into an address input end of the first adder.
6. A storage method of a shift register based on a RAM (random access memory) is provided, and is characterized by comprising the following steps:
acquiring user requirements; the user requirements comprise data to be stored;
determining the length of a required static shift register based on the user requirement;
when the required length of the static shift register is 2nThen, the shift register is used for storing data;
when the length of the required static shift register is more than 2nDetermining the shift register based on the length of the static shift registerThe number of (2);
sequentially connecting a plurality of shift registers in series;
storing data by using a plurality of shift registers connected in series;
wherein, shift register includes: the data input port of the second flip-flop is connected with the output port of the third adder, the output port of the second flip-flop is connected with the address input end of the third adder and the address input end of the single-port RAM, clock signals are input into the CLK ends of the second flip-flop and the single-port RAM, data are input into the data input end of the single-port RAM, data are output from the output end of the single-port RAM, and n is the width of the address input port of the RAM.
7. The method of claim 6, wherein said current required static shift register length is greater than 2nThe step of determining the number of shift registers based on the length of the static shift register may comprise:
when the length of the required static shift register is more than 2nConverting the length of the static shift register into the sum of powers of 2;
and counting the number of the powers of 2, and determining the number as the number of the shift registers.
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