CN113205769A

CN113205769A - Array substrate, driving method thereof and display device

Info

Publication number: CN113205769A
Application number: CN202110482446.2A
Authority: CN
Inventors: 冯靖伊; 曹席磊; 袁长龙; 张振华; 徐映嵩
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-04-30
Filing date: 2021-04-30
Publication date: 2021-08-03
Anticipated expiration: 2041-04-30
Also published as: CN113205769B

Abstract

The embodiment of the application provides an array substrate, a driving method thereof and a display device, relates to the technical field of display, and is used for solving the problem that the display device is poor in display image quality under low frequency. An array substrate comprises a gate driving circuit and a plurality of sub-pixels. The grid driving circuit comprises a plurality of first shift register groups and second shift register groups; each first shift register group comprises a plurality of cascaded first shift registers, and each second shift register group comprises a plurality of cascaded second shift registers; the plurality of first shift register groups are used for time-sharing driving. A plurality of sub-pixels divided into a first sub-pixel group and a second sub-pixel group; the first sub-pixel group comprises red sub-pixels and blue sub-pixels which are alternately arranged; the second sub-pixel group comprises green sub-pixels; the first shift register is coupled with the first sub-pixel group; the second shift register is coupled with the second sub-pixel group; and at least one first sub-pixel group is arranged between the adjacent second sub-pixel groups.

Description

Array substrate, driving method thereof and display device

Technical Field

The invention relates to the technical field of display, in particular to an array substrate, a driving method of the array substrate and a display device.

Background

The array substrate line drive (GOA) technology is a technology for fabricating a gate driving circuit on a substrate of an array substrate. The Gate driving circuit is directly formed on the substrate, so that the use of a Gate driving chip (Gate IC) is saved, the frameless or narrow frame design of the display device can be realized, the yield of the product is improved, and the production cost is reduced.

Since the display device with low power consumption is more energy-saving and has more market value, the person skilled in the art can achieve the above purpose by adopting the low-frequency driving technology. Namely, the purpose of saving power consumption is achieved by reducing the driving frequency of the gate driving circuit. However, after the driving frequency of the gate driving circuit is reduced, the refresh frequency of the display image of the display device is reduced, so that the quality of the display image is reduced, and bright and dark stripes can be seen on the display image in severe cases, which seriously affects the visual perception of human eyes.

Disclosure of Invention

The embodiment of the invention provides an array substrate, a driving method thereof and a display device, which are used for solving the problem of poor display image quality of the display device under low-frequency driving.

In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:

in a first aspect, an array substrate is provided, including: a gate driving circuit including a plurality of first shift register groups and second shift register groups; each of the first shift register groups includes a plurality of cascaded first shift registers, and the second shift register group includes a plurality of cascaded second shift registers; the plurality of first shift register groups are used for time-sharing driving; a plurality of sub-pixels divided into a first sub-pixel group and a second sub-pixel group; the first sub-pixel group comprises red sub-pixels and blue sub-pixels which are alternately arranged; the second sub-pixel group comprises green sub-pixels; the first shift register is coupled with the first sub-pixel group; the second shift register is coupled with the second sub-pixel group; at least one first sub-pixel group is arranged between the adjacent second sub-pixel groups.

Optionally, a plurality of first sub-pixel groups are disposed between adjacent second sub-pixel groups, and different first sub-pixel groups located between adjacent second sub-pixel groups are coupled to the first shift registers in different first shift register groups.

Optionally, the relative position relationship between each first sub-pixel group coupled to the first shift register in the same first shift register group and the respective reference sub-pixel group is the same; wherein the reference sub-pixel group is the second sub-pixel group adjacent to the first sub-pixel group along a first direction; the first direction is a direction intersecting with a row direction of the sub-pixels.

Optionally, the plurality of first shift registers and the plurality of second shift registers in the plurality of first shift register groups are circularly and alternately arranged; the first shift register and the first sub-pixel group coupled with the first shift register are located on the same row, and the second shift register and the second sub-pixel group coupled with the second shift register are located on the same row.

Optionally, the arrangement rules of the red sub-pixels and the blue sub-pixels included in the plurality of first sub-pixel groups coupled to the first shift register in the same first shift register group are not completely the same.

Optionally, one first sub-pixel group is disposed between adjacent second sub-pixel groups, and adjacent first sub-pixel groups are coupled to the first shift registers in different first shift register groups.

Optionally, the arrangement rules of the red sub-pixels and the blue sub-pixels in the adjacent first sub-pixel groups are different.

Optionally, the red sub-pixel and the blue sub-pixel in the same first sub-pixel group are located in the same row;

optionally, the green sub-pixels in the same second sub-pixel group are located in the same row.

Optionally, each of the first shift register sets is coupled to a first start signal terminal, and the second shift register set is coupled to a second start signal terminal.

Optionally, the first output terminal of the first shift register of the previous stage in each first shift register group is coupled to the first input terminal of the first shift register of the next stage;

optionally, a second output terminal of the second shift register of the previous stage in the second shift register group is coupled to a second input terminal of the second shift register of the next stage.

In a second aspect, a display device includes the array substrate; the display device comprises a display area and a peripheral area positioned at the periphery of the display area, a gate driving circuit in the array substrate is positioned at the peripheral area, and sub-pixels in the array substrate are positioned in the display area.

In a third aspect, a driving method of an array substrate includes: the plurality of first shift register groups output first grid scanning signals to the first sub-pixel groups coupled with the first shift register groups in a time-sharing mode; while each of the first shift register groups outputs a first gate scan signal to a first subpixel group coupled thereto, the second shift register group outputs a second gate scan signal to a second subpixel group coupled thereto.

Optionally, the outputting the first gate scan signal to the first sub-pixel group coupled to the plurality of first shift register groups in a time-sharing manner includes: the plurality of first shift register groups alternately output first gate scan signals to first sub-pixel groups coupled thereto.

Optionally, the outputting the first gate scan signal to the first sub-pixel group coupled to the plurality of first shift register groups in a time-sharing manner includes: the plurality of first shift register groups sequentially output first grid scanning signals to the first sub-pixel groups coupled with the first shift register groups respectively.

In the invention, on one hand, the green sub-pixel is driven by the second shift register (d) with high frequency, and the red sub-pixel and the blue sub-pixel are driven by the first shift register (a), the first shift register (b) or the first shift register (c) with low frequency, so that the total power of the display device is reduced and the power consumption of the display device is reduced compared with the situation that the red sub-pixel, the blue sub-pixel and the green sub-pixel are driven by the first shift register with 60Hz in a normal driving mode. On the other hand, because the green sub-pixel is a sub-pixel which mainly contributes to the luminance, and the green sub-pixel is driven by the high-frequency second shift register (d), and the frequency is 60Hz higher than the frequency of the first shift register which drives the green sub-pixel in the normal driving mode, the structure and the driving method of the array substrate provided by the invention can shorten the time length of the light-emitting period in one frame of picture, so that the luminance attenuation quantity delta L of the light-emitting device in the light-emitting period in each frame can be reduced. Therefore, the brightness difference between the current frame image and the previous frame image is reduced, so that the possibility of the display screen of the display device having a flicker problem can be reduced, and the improvement of the display screen quality of the display device is facilitated.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a display module according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;

fig. 5 is a cross-sectional view of a pixel circuit and a light emitting device provided in an embodiment of the present application;

fig. 6A is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

fig. 6B is a timing diagram of a control pixel circuit according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;

FIG. 8 is a diagram illustrating a cascade of shift registers according to an embodiment of the present disclosure;

FIG. 9 is a graph illustrating brightness attenuation of images at different frequencies according to an embodiment of the present disclosure;

fig. 10A is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;

fig. 10B is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;

fig. 10C is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;

fig. 10D is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;

fig. 11A is a schematic structural diagram of a shift register according to an embodiment of the present application;

FIG. 11B is a timing diagram of a shift register control according to an embodiment of the present disclosure;

fig. 12A is a schematic view illustrating lighting of an array substrate according to an embodiment of the present disclosure;

fig. 12B is a timing diagram for controlling the array substrate to be lighted according to the embodiment of the present disclosure;

fig. 12C is a schematic view illustrating another array substrate provided in this embodiment of the present application being lighted;

fig. 12D is a schematic view illustrating another array substrate provided in the embodiment of the present application;

fig. 13 is a timing diagram illustrating another example of controlling the lighting of the array substrate according to the present disclosure;

fig. 14A is a schematic structural view of another array substrate according to an embodiment of the present disclosure;

fig. 14B is a schematic structural diagram of another array substrate according to the embodiment of the present application;

fig. 15A is a timing diagram illustrating another lighting control of the array substrate according to the embodiment of the present disclosure;

fig. 15B is a schematic view illustrating another array substrate provided in the embodiment of the present application;

fig. 15C is a schematic view illustrating lighting of another array substrate according to the embodiment of the present application.

Reference numerals:

1000-a display device; 100-a display module; 110-middle frame; 120-a housing; 130-a cover plate; 1-a display panel; 2-a backlight module; 3-an array substrate; 31-a substrate; 32-sub-pixels; 322-a first subpixel group; 323-a second subpixel group; 320-a light emitting device; 3201 a cathode; 3203-a light-emitting material layer; 3202-anode; c-capacitance; a D-pixel circuit; 33-gate drive circuit; AA-display area; q-periphery region.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.

Further, in the present application, directional terms such as "upper" and "lower" are defined with respect to a schematically-disposed orientation of components in the drawings, and it is to be understood that these directional terms are relative concepts that are used for descriptive and clarity purposes and that will vary accordingly with respect to the orientation in which the components are disposed in the drawings.

In this application, the term "coupled", unless expressly stated or limited otherwise, is to be construed broadly, e.g., as meaning either a direct contact coupling or an indirect coupling via an intermediary. "and/or" is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

The embodiment of the present application provides a display device, and the display device related to the embodiment of the present application may be, for example: tablet personal computers, mobile phones, electronic readers, remote controllers, Personal Computers (PCs), notebook computers, Personal Digital Assistants (PDAs), vehicle-mounted devices, network televisions, wearable devices, televisions, and the like.

In the embodiments of the present application, specific forms of the display device are not particularly limited, and for convenience of description, the display device is a mobile phone.

In some embodiments provided in the present application, as shown in fig. 1, the display device 1000 mainly includes a display module 100, a middle frame 110, a housing 120, and a cover plate 130, wherein the display module 100 and the middle frame 110 are disposed in the housing 120.

The middle frame 110 is located between the display module 100 and the housing 120, and a surface (a surface facing the housing 120) of the middle frame 110 away from the display module 100 is used for mounting internal components such as a battery, a circuit board, a camera (camera), and an antenna.

The cover plate 130 is located on a side of the display module 100 away from the middle frame 110, and the cover plate 130 may be, for example, Cover Glass (CG), which may have a certain toughness.

The display module 100 has a light-emitting side capable of viewing a display screen and a back side opposite to the light-emitting side, the middle frame 110 is disposed on the back side of the display module 100, and the cover plate 130 is disposed on the light-emitting side of the display module 100.

The display module 100 includes a Display Panel (DP).

For example, as shown in fig. 2, the display panel 1 may be a Liquid Crystal Display (LCD) panel. In this case, the display module 100 further includes a backlight unit (BLU) 2 disposed at a rear surface of the lcd panel for providing a light source to the lcd panel.

Alternatively, the display panel 1 is an Organic Light Emitting Diode (OLED) display panel or a quantum dot light emitting diode (QLED) display panel. In this case, the OLED display panel and the QLED display panel can realize self-luminescence, and thus the backlight module 2 is not required to be provided in the display module 100.

In this way, the display device may include only the display panel, or may include other components in addition to the display panel.

For convenience of explanation, the display panel 1 will be described as an example of an OLED display panel.

The OLED display panel may be a top emission type display panel, a bottom emission type display panel, or a double-sided emission type display panel. The OLED display panel provided in the embodiment of the present application is only an illustration, and is not limited at all.

Regarding the structure of the display panel 1, in some embodiments provided herein, as shown in fig. 3, the display panel 1 includes an array substrate 3 and an encapsulation film 4 which are stacked as viewed in a cross-sectional view. The encapsulation film 4 is used to encapsulate the array substrate 3.

As shown in fig. 4, the display panel 1 includes a display area (active area, AA) and a peripheral area Q located at the periphery of the display area. The display area AA of the display panel 1 serves as a display area of the display device 001, and the peripheral area of the display panel 1 serves as a peripheral area of the display device.

Accordingly, as shown in fig. 4, the array substrate 3 includes a substrate 31, a plurality of sub-pixels 32 disposed on the substrate 31, a gate driving circuit 33, a Multiplexer (MUX), a Display Driver Integrated Circuit (DDIC), and a Flexible Printed Circuit (FPC) disposed on the substrate 31.

The sub-pixels 32 are located in the display area AA of the display panel 1, and the gate driving circuit 33, the MUX, the DDIC, and the FPC are all located in the peripheral area Q of the display panel 1.

The gate driving circuit 33 is configured to transmit a gate scan signal to the sub-pixels 32 in the display panel 1, and the MUX is configured to electrically connect the data lines coupled to the data signal terminals of the sub-pixels 32 in the display area AA to the DDIC, so that the sub-pixels 32 receive the data signals transmitted by the DDIC through the data lines. The DDIC is used for receiving signals transmitted from a driving system terminal in the electronic device and controlling and transmitting the signals to the display panel 1 according to a specific timing. The FPC is used for connecting the driving system and the DDIC. With respect to substrate 11, in some embodiments, substrate 11 may be constructed of a flexible resin material. In this case, the display panel 1 is a flexible display panel.

Regarding the structure of the sub-pixel 32, in some embodiments provided herein, as shown in fig. 5, the sub-pixel 32 includes a light emitting device 320 and a pixel circuit D for transmitting a driving signal to the light emitting device 320 to drive the light emitting device 320 to emit light.

As for the pixel circuit D, as illustrated in fig. 5, the pixel circuit D is provided on the substrate 31.

The pixel circuit D (or called pixel driving circuit) generally includes electronic devices such as a Thin Film Transistor (TFT) and a capacitor (C). For example, the pixel circuit D may be a pixel circuit of a 2T1C structure including two thin film transistors (a switching TFT and a driving TFT) and a capacitor C, but the pixel circuit D may also include two or more thin film transistors (a plurality of switching TFTs and one or more driving TFTs) and at least one capacitor.

Among them, a plurality of switching TFTs included in the pixel circuit D may be formed in synchronization with the driving TFTs, and only the driving TFTs in the pixel circuit D are illustrated in fig. 5.

In some embodiments provided herein, as shown in fig. 6A, the pixel circuit D may include a capacitor C and a plurality of switching transistors (M1, M2, M3, M5, M6, M7) and one driving transistor M4.

Wherein the gates of a portion of the switching transistors (e.g., M1, M7) are configured to receive the first gating signal N-1 as shown in fig. 6B. The gates of the other part of the switching transistors (e.g., M2, M3) are used for receiving the second gating signal N as shown in fig. 6B. The gates of the further partial switching transistors (e.g. M5, M6) are arranged to receive a lighting control signal EM as shown in fig. 6B.

The transistor may be an N-type transistor or a P-type transistor. In the present invention, the type of the transistor is not limited, and the following description will be made only by taking the transistor as a P-type transistor as an example.

In some embodiments provided herein, the operation process of the pixel circuit D shown in fig. 6A includes three stages, a first stage, a second stage and a third stage, shown in fig. 6B. The detailed processes of the first, second, and third stages are explained below.

In the first stage, the switching transistor M1 and the switching transistor M7 are turned on in fig. 6A under the control of the first gate signal N-1. The initial voltage Vint is transmitted to the gate (g) of the driving transistor M4 and the anode (a) of the OLED through the switching transistor M1 and the switching transistor M7, respectively. The purpose of resetting the anode a of the OLED and the gate g of the driving transistor M4 is achieved. Simultaneously, the initial voltage Vint charges the capacitor C.

In the second stage, under the control of the second gate signal N, the switching transistor M3 and the switching transistor M2 are turned on, the gate g and the drain (d) of the driving transistor M4 are electrically connected, and the driving transistor M4 is in a diode-on state. At this time, the data signal Vdata is written to the source(s) of the driving transistor M4 through the switching transistor M2, and the threshold voltage Vth of the driving transistor M4 is compensated.

In the third stage, under the control of the emission control signal EM, the switching transistor M5 and the switching transistor M6 are turned on, the gate g of the driving transistor M4 is electrically connected to one end of the capacitor C, and the capacitor C discharges to turn on the driving transistor M4. At this time, a current path between the voltages ELVDD and ELVSS is turned on, and the driving current I generated by the driving transistor M4 is transmitted to the OLED through the current path to drive the OLED to emit light.

However, in the third phase of the operation of the pixel circuit D, as the time of the third phase is prolonged, the capacitor C is continuously discharged, and the storage amount of the capacitor C is continuously decreased, so that the voltage of the gate g of the driving transistor M4 electrically connected to one end of the capacitor C is continuously decreased. With the source electrode s of the driving transistor M4 connected to the fixed voltage ELVDD, the voltage Vgs across the driving transistor M4 (the voltage difference between the gate electrode g of the driving transistor M4 and the source electrode s of the driving transistor M4) will continuously decrease as the third period of time extends, and the driving current I generated across the driving transistor M4 will continuously decrease. In another possible case, since the gate g of the driving transistor M4 is also electrically connected to the sources or drains of the switching transistor M1 and the switching transistor M3, if the switching transistor M1 and the switching transistor M3 are not completely turned off and there is a leakage condition, the voltage at the gate g of the driving transistor M4 will be reduced, the voltage ELVDD at the source s of the driving transistor M4 will not be changed, the voltage Vgs at the driving transistor M4 will be continuously reduced along with the extension of the third-stage time, and the driving current I generated at the driving transistor M4 will be continuously reduced. The reason why the continuous decrease of the driving current I in the driving transistor M4 occurs as described above is attributed to the existence of the leakage current by those skilled in the art.

In this case, as shown in fig. 4, three kinds of gate driving circuits 33, namely, a gate driving circuit 33(a) for emitting the first gate signal N-1, a gate driving circuit 33(b) for emitting the second gate signal N, and a gate driving circuit 33(c) for emitting the emission control signal EM, are provided in the peripheral region Q of the array substrate 31.

Based on this, in the pixel circuit D of the same row of sub-pixels 32, the gates of the switching transistors M5, M6 may be coupled to the gate driving circuit 33 (c); the gates of the switching transistors M1 and M7 may be coupled to the gate driving circuit 33 (a); the gates of the switching transistors M2 and M3 may be coupled to the gate driving circuit 33 (b).

It is understood that the array substrate 3 further includes gate lines for supplying gate scan signals to the pixel circuits D, data lines for supplying data signals (Vdata), power lines for supplying power signals (ELVDD/ELVSS), and initial signal lines for supplying initial signals (Vint).

As for the structure of the light emitting device 320, for example, as shown in fig. 5, the light emitting device 320 is disposed on the side of the pixel circuit D away from the substrate 31.

The light emitting device 320 includes an anode 3201, a cathode 3202, and a light emitting material layer 3203 disposed between the anode 3201 and the cathode 3202, the light emitting material layer 3203 emitting light driven by a driving current between the anode 3201 and the cathode 3202.

As shown in fig. 5, the pixel circuit D is coupled to the anode 3201 of the light emitting device 320, and is used for transmitting a driving signal to the anode 3201 of the light emitting device 320, and the cathode 3202 of the light emitting device 320 receives a power signal, so that a driving current is formed between the anode 3201 and the cathode 3202 to drive the light emitting material layer 3203 to emit light.

The plurality of sub-pixels 32 are located in the display area AA and divided into a plurality of rows. In some embodiments provided herein, a plurality of sub-pixels 32 are arranged in an array on a substrate 31, as shown in FIG. 4.

As shown in fig. 4, the display panel 1 includes a first direction Y and a second direction X intersecting each other, the first direction being a column direction of the sub-pixels, and the second direction being a row direction of the sub-pixels. Alternatively, the first direction is an extending direction of the data lines in the display panel 1, and the second direction is an extending direction of the gate lines in the display panel 1. A row of sub-pixels arranged along the second direction X is referred to as a row of sub-pixels.

The plurality of light emitting devices 320 in the plurality of sub-pixels 32 may emit light of a plurality of colors, for example, including at least a first color, a second color, and a third color, the first color, the second color, and the third color being three primary colors (e.g., red, green, and blue). It is also understood that the plurality of sub-pixels 32 emit light of a plurality of colors, including, for example, at least a first color, a second color, and a third color, the first color, the second color, and the third color being three primary colors (e.g., red, green, and blue). The sub-pixel emitting red light is referred to as a red sub-pixel R, the sub-pixel emitting green light is referred to as a green sub-pixel G, and the sub-pixel emitting blue light is referred to as a blue sub-pixel B.

Regarding the gate driving circuit 33, in some embodiments provided herein, as shown in fig. 4, the gate driving circuit 33 is located in the peripheral region Q. The gate driving circuit 33 may be disposed on one side of the peripheral region Q along the second direction X on the array substrate 3, or may be disposed on both sides of the peripheral region Q along the second direction X on the array substrate 3.

The gate driving circuit 33 is used to provide a gate scanning signal to the pixel circuit D in the sub-pixel 32, and the refresh frequency of the sub-pixel 32 in the display panel can be adjusted by adjusting the output of the scanning signal of the gate driving circuit 33.

Based on this, the structure and driving process of the array substrate 3 provided in the embodiments of the present application are schematically described in detail below with three examples.

Example 1

The embodiment of the application provides an array substrate 3, as shown in fig. 7, the array substrate 3 includes a plurality of sub-pixels 32 and a gate driving circuit 33. The sub-pixels 32 are located in the display area AA, and the gate driving circuit 33 is located in the peripheral area Q.

As for the arrangement of the plurality of sub-pixels 32, as shown in fig. 7, for example, the plurality of sub-pixels 32 are divided into a plurality of rows, and a row of sub-pixels arranged along the second direction X is referred to as a row of sub-pixels. The plurality of rows of sub-pixels 32 are arranged, for example, in a row of red-blue sub-pixels including a plurality of red sub-pixels R and a plurality of blue sub-pixels B, a row of green sub-pixels including a plurality of green sub-pixels G, and a row of red-blue sub-pixels R and a plurality of blue sub-pixels B are alternately arranged.

It should be noted that, in some embodiments provided in the present application, the arrangement of the sub-pixels 32 is only illustrated as an example, and the arrangement of the sub-pixels 32 in the plurality of rows of sub-pixels 32 is not limited to this, and may also be arranged in a real (real) RGB manner. For example, from top to bottom, the first row of sub-pixels is a plurality of red sub-pixels R, the second row of sub-pixels is a plurality of green sub-pixels G, and the third row of sub-pixels is a plurality of blue sub-pixels B. Alternatively, the first row of sub-pixels may be a plurality of blue sub-pixels B, the second row of sub-pixels may be a plurality of green sub-pixels G, and the third row of sub-pixels may be a plurality of red sub-pixels R.

Regarding the gate driving circuit 33, as shown in fig. 7, the gate driving circuit 33 includes a first shift register SR1 (SR) group, and the first shift register SR1 includes a plurality of cascaded first shift registers SR 1. Such as the first stage first shift register SR1(1), the second stage first shift register SR1(2), the third stage first shift register SR1(3), the nth stage first shift register SR1(n), and the (n +1) th stage first shift register SR1(n + 1). In the multi-stage first shift register SR1, the nth stage first shift register SR1 is any one of the first shift registers SR 1; wherein n is an integer of 2 or more. The first-stage first shift register SR1(1), the second-stage first shift register SR1(2), the third-stage first shift register SR1(3), the nth-stage first shift register SR1(n), and the (n +1) -th-stage first shift register SR1(n +1) are sequentially arranged along the first direction Y.

Regarding the cascade relationship among the plurality of first shift registers SR1 IN the gate driving circuit 33, as shown IN fig. 8, the input terminal IN of the first stage first shift register SR1(1) is connected to the first start signal terminal STV 1. The input terminal IN of each stage of the first shift register SR1(n) is coupled to the OUTPUT terminal OUTPUT of the previous stage of the first shift register SR1(n-1) except for the first stage of the first shift register SR1 (1).

On the basis, as shown in fig. 8, each stage of the first shift register SR1 in the gate driving circuit 33 is coupled to a row of sub-pixels 32, that is, each stage of the first shift register SR1 can provide a gate scan signal to the row of sub-pixels 32 coupled thereto.

It is understood that the first shift register SR1 is coupled to a row of sub-pixels 32, and in essence, the first shift register SR1 is coupled to the TFTs in the pixel circuits D of a row of sub-pixels 32. For convenience of illustration, the first shift register SR1 is coupled to a row of sub-pixels 32, but it should be understood that the first shift register SR1 is substantially coupled to the TFTs in the pixel circuits D of a row of sub-pixels 32.

Based on this, as can be seen from the above description, the OUTPUT terminal OUTPUT of each stage of the first shift register SR1(n) is coupled to the input terminal IN of the next stage of the first shift register SR1(n +1), and is also coupled to the TFT IN the pixel circuit D of the row of sub-pixels 32 coupled to the stage of the first shift register SR1(n), for providing the gate scan signal to the gate of the TFT.

The first start signal terminal STV1 is used to OUTPUT a first start signal, and after the first stage first shift register SR1(1) of the gate driving circuit 33 receives the first start signal, the first stage first shift register SR1(1) provides a gate scan signal to the OUTPUT terminal OUTPUT of the row of sub-pixels 32 coupled thereto. Meanwhile, the first stage first shift register SR1(1) also provides a start signal to the input terminal IN of the second stage first shift register SR1(2) to enable the second stage first shift register SR1 (2).

Next, the second stage first shift register SR1(2) provides the gate scan signal to the OUTPUT terminal OUTPUT of the row of sub-pixels 32 coupled thereto. Meanwhile, the second-stage first shift register SR1(2) also supplies a start signal to the input terminal IN of the third-stage first shift register SR1(3) to enable the third-stage first shift register SR1 (3).

Next, the third stage first shift register SR1(3) provides the gate scan signal to the OUTPUT of the row of sub-pixels 32 coupled thereto. Meanwhile, the third-stage first shift register SR1(3) also supplies a start signal to the input terminal IN of the fourth-stage first shift register SR1(4) to which the third-stage first shift register SR1(3) is cascaded. Thus, the plurality of cascaded first shift registers SR1 can scan a plurality of rows of subpixels 32 arranged in sequence and coupled to the plurality of cascaded first shift registers SR1, respectively, row by row.

In the above description, the gate driving circuit 33 is exemplified in the case where each stage of the first shift register SR1 controls one row of the sub-pixels 32 to display. In other embodiments of the present application, each of the stages of the first shift register SR1 may further control at least two rows of sub-pixels 32 for displaying, and the internal structure of the first shift register SR1 is not limited in this embodiment of the present application. For convenience of description, the following embodiments are also described by taking as an example that each stage of the first shift register SR1 controls one row of the sub-pixels 32 in the gate driving circuit 33 to display.

Based on the above description, since the plurality of first shift registers SR1 in the gate driving circuit 33 are sequentially cascaded, each first shift register SR1 in the gate driving circuit 33 OUTPUTs the gate scan signal through its OUTPUT terminal OUTPUT one by one in an image frame. In this case, after the first row of sub-pixels 32 is scanned, the remaining rows of sub-pixels 32 are also scanned line by line, so that all the sub-pixels 32 in the entire display area AA display one frame of image together, and the power consumption of the display device is high.

In the field of display technology, the quality of the image displayed by the display device 1000 and the power consumption of the display device 1000 are important issues that are of interest to those skilled in the art. In order to reduce power consumption, those skilled in the art have introduced a low frequency driving technique, that is, a technique for realizing low frequency driving of the display device 1000 by reducing the driving frequency of the first shift register SR1 in the gate driving circuit 33.

For example, the driving frequency of the first shift register SR1 in the gate driving circuit 33 is 60HZ, which is called a normal driving mode, and the driving frequency of the first shift register SR1 in the gate driving circuit 33 is lower than 60HZ, which is called a low frequency driving mode.

However, after the low frequency driving technique is adopted, the display brightness of the display device 1000 may be changed in the low frequency driving mode, and the display brightness of the display device 1000 is also a key factor of the quality of the displayed image.

Next, the change of the display luminance during the display of one frame of image by the display device 1000 is illustrated by taking as an example that the driving frequency of the first shift register SR1 in the gate driving circuit 33 is 60HZ and 30HZ, respectively.

As shown in fig. 9, the time period for displaying one frame of image includes a refresh period and a light-emitting period, and in combination with the working processes of the first stage, the second stage and the third stage of the pixel circuit D, it can be understood that the refresh period for displaying one frame of image corresponds to the first stage and the second stage of the working of the pixel circuit D, and the light-emitting period corresponds to the third stage of the working of the pixel circuit D. It is also understood that the refresh period during which one frame of image is displayed is the first and second stages of the operation of the pixel circuit D, and the light emission period during which one frame of image is displayed is the third stage of the operation of the pixel circuit D.

As shown in fig. 9, in the low frequency driving mode, for example, when the driving frequency of the first shift register SR1 in the gate driving circuit 33 is 30Hz, the display apparatus 1000 displays one frame of image for a longer time period than when the driving frequency of the first shift register SR1 is 60 Hz. However, the refresh period duration for displaying one frame image is a fixed duration, the light emission period duration for displaying one frame image when the first shift register SR1 is driven at a frequency of 30Hz is longer than the light emission period duration for displaying one frame image when the first shift register SR1 is driven at a frequency of 60 Hz.

However, as can be seen from the third stage of the operation process of the pixel circuit D, as the third stage is extended, the driving current I on the driving transistor M4 is continuously decreased along with the extension of time due to the existence of the leakage current, the decrease of the driving current I on the driving transistor M4 causes the luminance of the light emitting device 320 to be attenuated, and the more the driving current I on the driving transistor M4 is decreased, the more the luminance of the light emitting device 320 is attenuated. The luminance of the light emitting device 320 is attenuated and its degree of attenuation corresponds to the degree of attenuation and the degree of attenuation of the display luminance of the display apparatus 1000.

Then, since the duration of the light emitting period at the driving frequency of the first shift register SR1 is longer than the duration of the light emitting period at the driving frequency of the first shift register SR1 of 60Hz, the luminance attenuation Δ L' of the light emitting device 320 during the light emitting period at the driving frequency of the first shift register SR1 of 30Hz is greater than the luminance attenuation Δ L of the light emitting device 320 during the light emitting period at the driving frequency of the first shift register SR1 of 60 Hz. After the display of one frame of image is completed, the luminance of the light emitting device 320 returns to a fixed value L again by the refresh period, and the refresh period and the light emitting period are one cycle unit (one frame of image). And circulating in this way, and finishing the display of a plurality of frames of images. Since the luminance attenuation Δ L' of the light emitting device 320 in the light emitting period is large when the driving frequency of the first shift register SR1 is 30Hz, when the driving frequency of the first shift register SR1 is 30Hz, a significant luminance difference, i.e., flicker, is more likely to occur between the current frame image and the previous frame image, which affects the visual perception of human eyes.

It should be noted that when the driving frequency of the first shift register SR1 is lower than 60Hz, a significant brightness difference, i.e. a flicker phenomenon, is more likely to occur between the previous frame image and the previous frame image, and when the driving frequency of the first shift register SR1 is lower than 60Hz, the driving frequency may be 30Hz, or a series of frequencies lower than 60Hz, such as 20Hz, 25Hz, 35Hz, 40Hz, 45Hz, 47Hz, 50Hz, and 55 Hz.

That is, in the low frequency driving mode, i.e., when the driving frequency of the first shift register SR1 in the gate driving circuit 33 is lower than 60Hz, although the power consumption of the display apparatus 1000 can be reduced, there is caused a problem of a reduction in the quality of a displayed image, such as flicker.

Example two

Example two differs from example one in that the arrangement of the plurality of sub-pixels 32 and the structure of the gate drive circuit 33 are different from those in example one.

In the present example, regarding the arrangement of the plurality of sub-pixels 32, as shown in fig. 10B, the plurality of sub-pixels 32 may be divided into a first sub-pixel group 322 and a second sub-pixel group 323.

In some embodiments provided herein, as shown in fig. 10B, the first sub-pixel group 322 includes red sub-pixels R and blue sub-pixels B alternately arranged; the second subpixel group 323 includes a green subpixel G.

The red sub-pixels R and the blue sub-pixels B in the first sub-pixel group 322 are alternately arranged, as shown in fig. 10B, for example, the red sub-pixels R and the blue sub-pixels B are alternately arranged one by one, or the red sub-pixels R and the blue sub-pixels B are understood to be alternately arranged in sequence by using the red sub-pixels R and the blue sub-pixels B as a repeating unit, or by using the blue sub-pixels B and the red sub-pixels R as a repeating unit. Therefore, the red sub-pixel R and the blue sub-pixel B are more uniformly arranged, and the display effect of the display panel is better.

As shown in fig. 10C, the red sub-pixel R and the blue sub-pixel B may be alternately arranged two by two in a regular manner, in which the red sub-pixel R, the blue sub-pixel B, and the blue sub-pixel B are a repeating unit, or the blue sub-pixel B, the red sub-pixel R, and the red sub-pixel R are a repeating unit.

As shown in fig. 10D, the red subpixel R and the blue subpixel B may be alternately arranged in a regular pattern of one and two, with the red subpixel R, the blue subpixel B, and the blue subpixel B as a repeating unit, or with the blue subpixel B, the red subpixel R, and the red subpixel R as a repeating unit.

Of course, the red sub-pixels R and the blue sub-pixels B may be arranged regularly or irregularly in other ways, as long as the red sub-pixels R and the blue sub-pixels B are not in the first half row, or the red sub-pixels R are not in the first half row and the blue sub-pixels B and the red sub-pixels R are in the second half row.

In some embodiments provided herein, as shown in fig. 10B-10D, the red sub-pixel R and the blue sub-pixel B in the same first sub-pixel group 322 are located in the same row.

That is, in the embodiment of the present application, the plurality of sub-pixels are divided into a plurality of rows, and a row of sub-pixels may include a red sub-pixel R and a blue sub-pixel B, and the row of sub-pixels is referred to as a first sub-pixel group 322.

Therefore, the grid lines for transmitting the grid scanning signals to the red sub-pixels R and the blue sub-pixels B in the same row are straight lines, the structure of the grid lines can be simplified, and the grid line layout difficulty and the preparation difficulty are reduced.

In other embodiments provided herein, the green sub-pixels G in the same second sub-pixel group 323 are located in the same row.

That is, in the embodiment of the present application, the plurality of sub-pixels are divided into a plurality of rows, and a row of sub-pixels may also include a green sub-pixel G, and the row of sub-pixels is referred to as a second sub-pixel group 323.

Therefore, the grid lines for transmitting the grid scanning signals to the green sub-pixels G in the same row are straight lines, the structure of the grid lines can be simplified, and the grid line layout difficulty and the preparation difficulty are reduced.

In some embodiments provided herein, a plurality of first sub-pixel groups 323 are disposed between adjacent second sub-pixel groups 323. That is, two, three, four, or five first sub-pixel groups 323 may be disposed between adjacent second sub-pixel groups 323.

Illustratively, as shown in fig. 10A, two first sub-pixel groups 322 are disposed between adjacent second sub-pixel groups 323. Two first sub-pixel groups 322 are disposed between the second sub-pixel group 323 of the third row and the second sub-pixel group 323 of the sixth row from top to bottom.

Alternatively, as illustrated in fig. 10B, three first sub-pixel groups 322 are disposed between adjacent second sub-pixel groups 323. Three first sub-pixel groups 322 are arranged between the second sub-pixel group 323 of the fourth row and the second sub-pixel group 323 of the eighth row from top to bottom.

In the following description, three first subpixel groups 322 are disposed between adjacent second subpixel groups 323 as an example.

Regarding the structure of the gate driving circuit 33, in some embodiments provided herein, the gate driving circuit 33 includes a plurality of first shift register groups SR1 and second shift register groups SR 2.

The shift register sets SR1 are used for time-sharing driving. That is, only one first shift register group SR1 among the plurality of first shift register groups SR1 is driven at the same time. In addition, the first shift register group SR1 is driven, and it can be understood that the first shift register group SR1 receives a signal and outputs a signal.

Each of the first shift register groups SR1 includes a plurality of cascaded first shift registers SR1, the first shift register SR1 is coupled to the pixel circuits D of the sub-pixels 32 (red sub-pixel R and blue sub-pixel B) in the first sub-pixel group 322, and the first shift register SR1 is configured to provide gate scan signals to the pixel circuits D of the sub-pixels 32 in the first sub-pixel group 322.

The second shift register group SR2 includes a plurality of cascaded second shift registers SR2, the second shift register SR2 is coupled to the pixel circuits D of the sub-pixels 32 (green sub-pixels G) in the second sub-pixel group 323, and the second shift register SR2 is used to output gate scan signals to the pixel circuits D of the sub-pixels 32 in the second sub-pixel group 323.

Based on this, it can be understood that the first shift register SR1 is coupled to the first sub-pixel group 322, and in fact, the first shift register SR1 is coupled to the pixel circuit D of the sub-pixel 32 in the first sub-pixel group 322. Similarly, the second shift register SR2 is coupled to the second sub-pixel group 323, and in this case, the second shift register SR2 is coupled to the pixel circuit D of the sub-pixel 32 in the second sub-pixel group 323.

In some embodiments provided herein, as shown in fig. 10B, the gate driving circuit 33 includes three first shift register groups SR1, such as a first shift register group SR1(a), a first shift register group SR1(B), and a first shift register group SR1 (c).

Wherein each first shift register group SR1 includes a plurality of cascaded first shift registers SR1, that is, the first shift register group SR1(a) includes cascaded first shift registers SR1(a-1), SR1(a-2) … … and SR1 (a-n). The first shift register group SR1(b) includes a cascade of a first shift register SR1(b-1), a first shift register SR1(b-2) … … and a first shift register SR1 (b-n). The first shift register group SR1(c) includes a cascade of a first shift register SR1(c-1), a first shift register SR1(c-2) … … and a first shift register SR1 (c-n).

The second shift register group SR2 includes a plurality of cascaded second shift registers SR2, that is, the second shift register group SR2(d) includes a plurality of cascaded second shift registers SR2(d-1), SR2(d-2) … … and SR2 (d-n).

In some embodiments provided herein, the arrangement rules of the red sub-pixel R and the blue sub-pixel B included in the plurality of first sub-pixel groups 322 coupled to the plurality of first shift registers SR1 of the same first shift register group SR1 are not identical.

For example, as shown in fig. 10B, in the first shift register group SR1(a), the arrangement rule of the red and blue sub-pixels R and B in the first sub-pixel group 322 coupled to the first stage first shift register SR1(a-1) is different from the arrangement rule of the red and blue sub-pixels R and B in the first sub-pixel group 322 coupled to the second stage first shift register SR1 (a-2). However, the arrangement rule of the red and blue sub-pixels R and B in the first sub-pixel group 322 coupled to the first stage first shift register SR1(a-1) is the same as that of the red and blue sub-pixels R and B in the first sub-pixel group 322 coupled to the third stage first shift register SR1 (a-3).

Thus, the arrangement rules of the red sub-pixels R and the blue sub-pixels B in the first sub-pixel groups 322 may be the same or different, and the arrangement modes of the red sub-pixels and the blue sub-pixels may be enriched to meet different requirements.

In some embodiments provided herein, three first sub-pixel groups 322 are disposed between adjacent second sub-pixel groups 323, and the three first sub-pixel groups 322 between the adjacent second sub-pixel groups 323 are coupled to the first shift registers SR1 in different first shift register groups SR 1.

Illustratively, as shown in fig. 10B, three different first sub-pixel groups 322 are disposed between the second sub-pixel group 323 located in the fourth row and the second sub-pixel group 323 located in the eighth row from top to bottom.

The pixel circuits D of the sub-pixels 32 in the first sub-pixel group 322 in the fifth row are coupled to the second-stage first shift register SR1(a-2) in the first shift register group SR1(a), the pixel circuits D of the sub-pixels 32 in the first sub-pixel group 322 in the sixth row are coupled to the second-stage first shift register SR1(b-2) in the first shift register group SR1(b), and the pixel circuits D of the sub-pixels 32 in the first sub-pixel group 322 in the seventh row are coupled to the second-stage first shift register SR1(c-2) in the first shift register group SR1 (c).

Thus, during the display driving process, one first sub-pixel group 322 is always lit up among three first sub-pixel groups 322 between adjacent second sub-pixel groups 323, and one first sub-pixel group 322 is always lit up between any adjacent second sub-pixel groups 323. That is, the first sub-pixel group 322 is illuminated to cover the whole display area AA, so as to ensure the display uniformity of the display panel 1 and improve the display effect. The situation that a continuous area of the first sub-pixel group 322 is turned on in a bundled manner and a continuous area of the first sub-pixel group 322 is turned off in a bundled manner in the display area AA due to the bundled arrangement of the first sub-pixel groups 322 coupled to the same first shift register group SR1 is avoided.

In some embodiments provided herein, the relative positions of each of the first sub-pixel groups 322 coupled to the first shift register SR1 of the same first shift register group SR1 and the respective reference sub-pixel groups are the same.

The reference subpixel group is a second subpixel group 323 adjacent to the first subpixel group 322 in the first direction Y.

For example, as shown in fig. 10B, the first row first sub-pixel group 322, the second row first sub-pixel group 322, the third row first sub-pixel group 322, and the fourth row second sub-pixel group 323 may form a first sub-pixel group repeating unit, and the fourth row second sub-pixel group 323 serves as a reference sub-pixel group in the first sub-pixel group repeating unit. The fifth row first subpixel group 322, the sixth row first subpixel group 322, the seventh row first subpixel group 322, and the eighth row second subpixel group 323 constitute a second subpixel group repeating unit, and the eighth row second subpixel group 323 serves as a reference subpixel group in the second subpixel group repeating unit.

In each subpixel group repeating unit, the first subpixel group 322 coupled to the first shift register SR1(a-n) of the first shift register group SR1(a) has the same relative positional relationship with the second subpixel group 323 of the subpixel group repeating unit.

That is, the first subpixel group 322 of the first subpixel group repeating unit coupled to the first shift register SR1(a-n) of the first shift register group SR1(a) and the second subpixel group 323 of the first subpixel group repeating unit are spaced apart by two first subpixel groups 322 coupled to the first shift register group SR1(b) and the first shift register group SR1(c), respectively.

Also spaced between the first subpixel group 322 of the second subpixel group repeating unit coupled to the first shift register SR1(a-n) of the first shift register group SR1(a) and the second subpixel group 323 of the second subpixel group repeating unit is the first subpixel group 322 coupled to the first shift register group SR1(b) and the first shift register group SR1 (c).

In each subpixel group repeating unit, the first subpixel group 322 coupled to the first shift register SR1(b-n) of the first shift register group SR1(b) has the same relative positional relationship with the second subpixel group 323 of the subpixel group repeating unit.

That is, the first subpixel group 322 of the first subpixel group repeating unit coupled to the first shift register SR1(b-n) of the first shift register group SR1(b) and the second subpixel group 323 of the first subpixel group repeating unit are separated by one first subpixel group 322 coupled to the first shift register group SR1 (c).

The first subpixel group 322 of the second subpixel group repeating unit coupled to the first shift register SR1(b-n) of the first shift register group SR1(b) is spaced apart from the second subpixel group 323 of the second subpixel group repeating unit by one first subpixel group 322 coupled to the first shift register group SR1 (c).

In each subpixel group repeating unit, the first subpixel group 322 coupled to the first shift register SR1(c-n) of the first shift register group SR1(c) has the same relative positional relationship with the second subpixel group 323 of the subpixel group repeating unit.

That is, the first subpixel group 322 of the first subpixel group repeating unit coupled to the first shift register SR1(c-n) of the first shift register group SR1(c) is adjacent to the second subpixel group 323 of the first subpixel group repeating unit.

The first subpixel group 322 of the second subpixel group repeating unit coupled to the first shift register SR1(c-n) of the first shift register group SR1(c) is adjacent to the second subpixel group 323 of the second subpixel group repeating unit.

In this way, the plurality of first sub-pixel groups 322 are regularly arranged on the substrate 31, and during the display driving process, the number of the non-lighting first sub-pixel groups 322 between any adjacent lighting row first sub-pixel groups 322 is the same, so that the sub-pixels 32 in the display panel 1 are more uniformly lighted during each scanning process, and the display effect of the display panel is further improved.

In some embodiments provided herein, the plurality of first shift registers SR1 in the plurality of first shift register sets SR1 and the second shift register SR2 in the second shift register set SR2 are cyclically alternated.

Illustratively, as shown in fig. 10B, the first shift register SR1(a-n) in the first shift register group SR1(a), the first shift register SR1(B-n) in the first shift register group SR1(B), the first shift register SR1(c-n) in the first shift register group SR1(c), and the second shift register SR2(d-n) in the second shift register group SR2(d) are cyclically and alternately arranged with the nth stage first shift register SR1(a-n), the nth stage first shift register SR1(B-n), the nth stage first shift register SR1(c-n), and the nth stage second shift register SR2(d-n) as a repeating unit.

For example, the first stage first shift register SR1(a-1), the first stage first shift register SR1(b-1), the first stage first shift register SR1(c-1), the first stage second shift register SR2(d-1), the second stage first shift register SR1(a-2), the second stage first shift register SR1(b-2), the second stage first shift register SR1(c-2), the second stage second shift register SR2(d-2), … … are circularly arranged.

The first shift register SR1 and the first sub-pixel group 322 coupled thereto are located in the same row, and the second shift register SR2 and the second sub-pixel group 323 coupled thereto are located in the same row.

It will also be appreciated that the first shift register SR1 is located in the same row as the subpixels 32 in the first subpixel group 322 coupled thereto, and the second shift register SR2 is located in the same row as the subpixels 32 in the second subpixel group 323 coupled thereto.

The first shift register SR1(a-n) and the first sub-pixel group 322 coupled thereto are located in the same row, that is, the red sub-pixel R and the blue sub-pixel B in the first shift register SR1(a-n) and the first sub-pixel group 322 coupled thereto are located in the same row.

The first shift register SR1(B-n) and the first sub-pixel group 322 coupled thereto are located on the same row, that is, the red sub-pixel R and the blue sub-pixel B in the first shift register SR1(B-n) and the first sub-pixel group 322 coupled thereto are located on the same row.

The first shift register SR1(c-n) and the first sub-pixel group 322 coupled thereto are located on the same row, that is, the red sub-pixel R and the blue sub-pixel B in the first shift register SR1(c-n) and the first sub-pixel group 322 coupled thereto are located on the same row.

The second shift register SR2(d-n) and the second sub-pixel group 323 coupled thereto are located on the same row, that is, the second shift register SR2(d-n) and the green sub-pixel G in the second sub-pixel group 323 coupled thereto are located on the same row.

Thus, the red sub-pixel R and the blue sub-pixel B in the first shift register SR1 and the first sub-pixel group 322 coupled thereto are located on the same row, and the green sub-pixel G in the second shift register SR2 is located on the same row. On one hand, the layout of the shift register SR can be simplified, and on the other hand, the number of connecting wires between the shift register SR and the sub-pixel group coupled with the shift register SR can be reduced, for example, the arrangement of gate lines can be simplified, thereby simplifying the process.

Regarding the structure of the shift registers SR, in some embodiments provided herein, the structure of the shift registers SR in each of the first shift register group SR1 and each of the second shift register group SR2 may be the same.

For example, as shown in fig. 11A, the shift register SR includes a plurality of transistors, such as T1, T2, T3, T4, T5, T6, T7, T8, and a plurality of capacitors C, such as C1 and C2.

The gate of the transistor T1 is coupled to the first clock signal terminal CK1, the first pole of the transistor T1 is coupled to the first start signal terminal STV1, and the second pole of the transistor T1 is coupled to the gate of the transistor T2 and the point N1, respectively.

The gate of the transistor T2 is coupled to the second pole of the transistor T1, the first pole of the transistor T2 is coupled to the first clock signal terminal CK1, the second pole of the transistor T2 is coupled to the second pole of the transistor T3, and the point N2, respectively.

The gate of the transistor T3 is coupled to the first clock signal terminal CK1, the first pole of the transistor T3 is coupled to the low level signal terminal VGL, the second pole of the transistor T3 is coupled to the second pole of the transistor T2 and the point N2, respectively.

The gate of the transistor T4 is coupled to the node N2 and the first terminal of the capacitor C2, respectively, the first pole of the transistor T4 is coupled to the high-level signal terminal VGH, and the second pole of the transistor T4 is coupled to the OUTPUT terminal OUTPUT.

A gate of the transistor T5 is coupled to the second pole of the transistor T8 and the first terminal of the capacitor C1, respectively, a first pole of the transistor T5 is coupled to the second clock signal terminal CK2, and a second pole of the transistor T5 is coupled to the OUTPUT terminal OUTPUT.

The gate of the transistor T6 is coupled to the point N2, the first pole of the transistor T6 is coupled to the high-level signal terminal VGH, and the second pole of the transistor T6 is coupled to the second pole of the transistor T7.

The gate of the transistor T7 is coupled to the second clock signal terminal CK2, the first pole of the transistor T7 is coupled to the point N1, and the second pole of the transistor T7 is coupled to the second pole of the transistor T6.

The gate of the transistor T8 is coupled to the low-level signal terminal VGL, the first pole of the transistor T8 is coupled to the point N1, and the second pole of the transistor T8 is coupled to the gate of the transistor T5 and the first terminal of the capacitor C1, respectively.

A first terminal of the capacitor C1 is coupled to the gate of the transistor T5, and a second terminal of the capacitor C1 is coupled to the OUTPUT terminal OUTPUT.

A first terminal of the capacitor C2 is coupled to the gate of the transistor T4, and a second terminal of the capacitor C2 is coupled to the high-level signal terminal VGH.

The transistor may be an N-type transistor or a P-type transistor. The first electrode of the transistor may be a source and the second electrode may be a drain, or the first electrode of the transistor may be a drain and the second electrode may be a source, which is not limited in the present invention.

Hereinafter, the driving process of the shift register SR shown in fig. 11A will be described in detail with reference to the signal timing chart shown in fig. 11B, taking the above transistors as examples of P-type transistors.

In stage P1 of a frame:

CK1 ═ 0, CK2 ═ 1, STV1 ═ 0; VGL is 0; VGH ═ 1; where "0" represents a low level and "1" represents a high level.

At this time, the first clock signal terminal CK1 outputs a low level signal, the transistor T1 is turned on, and the low level signal output from the first start signal terminal STV1 is output to the gate of the transistor T2 and the point N1. The low voltage signal terminal VGL outputs a low level signal, the transistor T8 is turned on, the low level signal outputted from the first start signal terminal STV1 can be outputted to the gate of the transistor T5, the transistor T5 is turned on, and the capacitor C1 is charged by the first start signal terminal STV 1. The high level signal OUTPUT from the second clock signal terminal CK2 is OUTPUT to the OUTPUT terminal OUTPUT through the transistor T5, and the OUTPUT signal of the OUTPUT terminal OUTPUT is a high level signal. Since the second clock signal terminal CK2 outputs a high level signal at this time, the transistor T7 is turned off.

In addition, the second pole of the transistor T1 is coupled to the gate of the transistor T2, the low-level signal outputted from the first start signal terminal STV1 can be outputted to the gate of the transistor T2, and the transistor T2 is turned on. The first clock signal CK1 outputs a low level signal to the point N2 through the transistor T2, and thus to the gate of the transistor T6, and the transistor T6 is turned on.

In addition, the first clock signal terminal CK1 outputs a low level signal, the transistor T3 is turned on, a low level signal output from the low voltage signal terminal VGL is output to the gate of the transistor T4, the transistor T4 is turned on, and the low voltage signal terminal VGL charges the capacitor C2. The high level signal OUTPUT from the high voltage signal terminal VGH is OUTPUT to the OUTPUT terminal OUTPUT through the transistor T4, and the OUTPUT signal of the OUTPUT terminal OUTPUT is a high level signal at this time.

In summary, the transistor T1 is turned on, the transistor T2 is turned on, the transistor T3 is turned on, the transistor T4 is turned on, the transistor T5 is turned on, the transistor T6 is turned on, the transistor T7 is turned off, the transistor T8 is turned on, and the OUTPUT terminal OUTPUT OUTPUTs a high level signal at the stage P1.

In stage P2 of a frame:

CK1 ═ 1, CK2 ═ 0, STV1 ═ 1; VGL is 0; VGH ═ 1; where "0" represents a low level and "1" represents a high level.

At this time, the first clock signal terminal CK1 outputs a high level signal, the transistor T1 is turned off, and the transistor T3 is turned off; the low voltage signal terminal VGL outputs a low level signal, and the transistor T8 is turned on. The capacitor C1 charges the N4 point with the low level stored in the P1 stage, so that the transistor T5 and the transistor T2 are turned on, the low level signal OUTPUT by the second clock signal terminal CK2 is OUTPUT to the OUTPUT terminal OUTPUT through the transistor T5, and the OUTPUT signal of the OUTPUT terminal OUTPUT is a low level signal, so that the low level signal of the second clock signal terminal CK2 is OUTPUT to the gate line connected to the OUTPUT terminal OUTPUT as the gate scan signal of the row of sub-pixels 32 coupled to the row of the first shift register SR 1.

In addition, the transistor T7 is turned on under the control of the second clock signal terminal CK 2; the high level signal output from the first clock signal terminal CK1 is output to the point N2 through the transistor T2, so that the transistor T4 and the transistor T6 are turned off.

In summary, the transistor T1 is turned off, the transistor T2 is turned on, the transistor T3 is turned off, the transistor T4 is turned off, the transistor T5 is turned on, the transistor T6 is turned off, the transistor T7 is turned on, the transistor T8 is turned on, and the OUTPUT terminal OUTPUT OUTPUTs a high level signal at the stage P1; the OUTPUT terminal OUTPUT OUTPUTs a low level signal at the stage P2 described above.

In stage P3 of a frame:

CK1 ═ 0, CK2 ═ 1, STV1 ═ 1; VGL is 0; VGH ═ 1; where "0" represents a low level and "1" represents a high level.

At this time, the first clock signal terminal CK1 outputs a low level signal, the transistor T1 is turned on, a high level signal output from the first start signal terminal STV1 is output to the gate of the transistor T2 and the point N1, and the transistor T2 is turned off; the low voltage signal terminal VGL outputs a low level signal, the transistor T8 is turned on, the high level signal output from the first start signal terminal STV1 is output to the gate of the transistor T5, and the transistor T5 is turned off.

In addition, the first clock signal terminal CK1 outputs a low level signal, the transistor T3 is turned on, the low voltage signal terminal VGL outputs a low level signal which can be output to the point N2 and the gate of the transistor T4, and the transistor T6 and the transistor T4 are turned on. The high level signal OUTPUT from the high voltage signal terminal VGH is OUTPUT to the OUTPUT terminal OUTPUT through the transistor T4, and the OUTPUT signal of the OUTPUT terminal OUTPUT is a high level signal at this time.

In addition, since the second clock signal terminal CK2 outputs a high level signal, the transistor T7 is turned off.

In summary, the transistor T1 is turned on, the transistor T2 is turned off, the transistor T3 is turned on, the transistor T4 is turned on, the transistor T5 is turned off, the transistor T6 is turned on, the transistor T7 is turned off, the transistor T8 is turned on, and the OUTPUT terminal OUTPUT OUTPUTs a high level signal at the stage P3.

It should be noted that, in the above embodiment, the on/off process of the transistors is described by taking all the transistors as P-type transistors as an example, and when all the transistors are N-type, the control signals in fig. 11B need to be inverted. In the embodiment of the present application, the OUTPUT signal of the OUTPUT terminal OUTPUT is a signal whose low level signal is active, and the OUTPUT signal of the OUTPUT terminal OUTPUT is a signal whose high level signal is inactive.

Based on the above-mentioned structure of the shift registers SR, the embodiments of the present application relate to a cascade connection manner of the plurality of first shift registers SR1 and the plurality of second shift registers SR2 in the first shift register group SR1 and the second shift register group SR2, and examples thereof include a cascade connection manner of the plurality of first shift registers SR1(a-n) in the first shift register group SR1(a), a cascade connection manner of the plurality of first shift registers SR1(b-n) in the first shift register group SR1(b), a cascade connection manner of the plurality of first shift registers SR1(c-n) in the first shift register group SR1(c), and a cascade connection manner of the plurality of second shift registers SR2(d-n) in the second shift register group SR2(d) are the same as the cascade connection manner of the plurality of first shift registers SR1(n) in the first shift register group SR1 in the example one, reference is made to the cascade connection of the first shift registers SR1 in the first shift register group SR1 in the first example.

As shown in FIG. 10B, each of the first shift register sets SR1 is coupled to a first start signal terminal STV1, and the second shift register set SR2 is coupled to a second start signal terminal STV 2.

That is, the first shift register set SR1(a) is coupled to the first start signal terminal STV1(a), the first shift register set SR1(b) is coupled to the first start signal terminal STV1(b), the first shift register set SR1(c) is coupled to the first start signal terminal STV1(c), and the second shift register set SR2(d) is coupled to the second start signal terminal STV 2.

It can also be understood that the input terminal IN of the first stage first shift register SR1(a-1) IN the first shift register group SR1(a) is connected to the first start signal terminal STV1(a), the input terminal IN of the first stage first shift register SR1(b-1) IN the first shift register group SR1(b) is connected to the first start signal terminal STV1(b), the input terminal IN of the first stage first shift register SR1(c-1) IN the first shift register group SR1(c) is connected to the first start signal terminal STV1(c), and the input terminal IN of the first stage second shift register SR2(d-1) IN the second shift register group SR2(d) is connected to the second start signal terminal STV 2.

The first start signal terminal STV1(a) outputs a first start signal to the first stage first shift register SR1(a-1) of the first shift register set SR1(a) to control the first stage first shift register SR1(a-1) to be turned on. The first start signal terminal STV1(b) outputs a first start signal to the first stage first shift register SR1(b-1) of the first shift register set SR1(b) to control the first stage first shift register SR1(b-1) to be turned on. The first start signal terminal STV1(c) outputs a first start signal to the first stage first shift register SR1(c-1) of the first shift register set SR1(c) to control the first stage first shift register SR1(c-1) to be turned on. The second start signal terminal STV2 outputs a second start signal to the first stage SR2(d-1) of the second shift register set SR2(d) to control the first stage SR2(d-1) to turn on.

Referring to the cascade connection of the plurality of first shift registers SR1 IN the first shift register set SR1, IN some embodiments, as shown IN FIG. 10B, the input IN of the first stage first shift register SR1(a-1) IN the first shift register set SR1(a) is connected to the first start signal terminal STV1 (a). The input terminal IN of each stage of the first shift register SR1(a-n) is coupled to the output terminal OUTPUT (a) of the previous stage of the first shift register SR1(a-n-1) except for the first stage of the first shift register SR1 (a-1).

The input terminal IN of the first stage of the first shift register SR1(b-1) IN the first shift register set SR1(b) is connected to the first start signal terminal STV1 (b). The input terminal IN of each stage of the first shift register SR1(b-n) is coupled to the output terminal OUTPUT (b) of the previous stage of the first shift register SR1(b-n-1) except for the first stage of the first shift register SR1 (b-1).

The input IN of the first shift register SR1(c-1) of the first shift register set SR1(c) is connected to the first start signal terminal STV1 (c). The input terminal IN of each stage of the first shift register SR1(c-n) is coupled to the output terminal OUTPUT (c) of the previous stage of the first shift register SR1(c-n-1) except for the first stage of the first shift register SR1 (c-1).

The input IN of the first stage SR2(d-1) of the second shift register set SR2(d) is connected to the second start signal terminal STV 2. The input terminal IN of each of the second shift registers SR2(d-n) is coupled to the output terminal OUTPUT (d) of the previous second shift register SR2(d-n-1) except for the first second shift register SR2 (d-1).

Then, the first start signal terminal STV1(a) outputs a first start signal, and after the first stage first shift register SR1(a-1) receives the first start signal, the first stage first shift register SR1(a-1) provides a first gate scan signal to the gate of the TFT coupled to the output terminal output (a) of the first stage first shift register SR1(a-1) in the row of sub-pixels 32 coupled thereto. Meanwhile, the first stage first shift register SR1(a-1) also provides a start signal to the input IN of the second stage first shift register SR1(a-2) to enable the second stage first shift register SR1 (a-2). The output terminal output (a) of the second stage first shift register SR1(a-2) may output a start signal to the third stage first shift register SR1(a-3) to enable the third stage first shift register SR1(a-3), such that the multiple stages of first shift registers SR1(a-n) may be sequentially enabled.

Based on this, with the plurality of cascaded first shift registers SR1(a-n), the plurality of rows of first subpixel groups 322, which are sequentially arranged in the first direction Y and are respectively coupled to the plurality of cascaded first shift registers SR1(a-n), can be scanned line by line.

Similarly, the first start signal terminal STV1(b) outputs a first start signal, and after the first stage first shift register SR1(b-1) receives the first start signal, the first stage first shift register SR1(b-1) provides a first gate scan signal to the gate of the TFT coupled to the output terminal output (b) of the first stage first shift register SR1(b-1) in the row of sub-pixels 32 coupled thereto. Meanwhile, the first stage first shift register SR1(b-1) also provides a start signal to the input IN of the second stage first shift register SR1(b-2) to enable the second stage first shift register SR1 (b-2). The output terminal output (b) of the second stage first shift register SR1(b-2) may output a start signal to the third stage first shift register SR1(b-3) to enable the third stage first shift register SR1(b-3), such that the multiple stages of first shift registers SR1(b-n) may be sequentially enabled.

Based on this, by the plurality of cascaded first shift registers SR1(b), the plurality of rows of first subpixel groups 322 sequentially arranged in the first direction Y and respectively coupled to the plurality of cascaded first shift registers SR1(b) can be scanned line by line.

Similarly, the first start signal terminal STV1(c) outputs a first start signal, and after the first stage first shift register SR1(c-1) receives the first start signal, the first stage first shift register SR1(c-1) provides a first gate scan signal to the gate of the TFT coupled to the output terminal output (c) of the first stage first shift register SR1(c-1) in the row of sub-pixels 32 coupled thereto. Meanwhile, the first stage first shift register SR1(c-1) also provides a start signal to the input IN of the second stage first shift register SR1(c-2) to enable the second stage first shift register SR1 (c-2). The output terminal output (c) of the second stage first shift register SR1(c-2) may output a start signal to the third stage first shift register SR1(c-3) to enable the third stage first shift register SR1(c-3), such that the multiple stages of first shift registers SR1(c-n) may be sequentially enabled.

Based on this, by the plurality of cascaded first shift registers SR1(c), the plurality of rows of first subpixel groups 322 sequentially arranged in the first direction Y and respectively coupled to the plurality of cascaded first shift registers SR1(c) can be scanned line by line.

Similarly, the second start signal terminal STV2 outputs a second start signal, and after the first stage second shift register SR2(d-1) receives the second start signal, the first stage second shift register SR2(d-1) provides a second gate scan signal to the gate of the TFT coupled to the output terminal output (d) of the first stage second shift register SR2(d-1) in the row of sub-pixels 32 coupled thereto. Meanwhile, the first stage second shift register SR2(d-1) also provides a start signal to the input IN of the second stage second shift register SR2(d-2) to enable the second stage second shift register SR2 (d-2). The output terminal output (d) of the second stage second shift register SR2(d-2) may output a start signal to the third stage second shift register SR2(d-3) to enable the third stage second shift register SR2(d-3), so that the multiple stages of the second shift registers SR2(d-n) may be sequentially enabled.

Based on this, by the plurality of cascaded second shift registers SR2(d), the plurality of rows of second subpixel groups 323 sequentially arranged in the first direction Y and respectively coupled to the plurality of cascaded second shift registers SR2(d) can be scanned line by line.

Regarding the driving method of the array substrate 3, in some embodiments provided herein, the driving method of the array substrate 3 includes:

the plurality of first shift register sets SR1 time-share and output the first gate scan signal to the first sub-pixel set 322 coupled thereto.

While each first shift register group SR1 outputs the first gate scan signal to the first subpixel group 322 coupled thereto, the second shift register group SR2 outputs the second gate scan signal to the second subpixel group 323 coupled thereto.

The time-sharing output of the first gate scan signals to the first sub-pixel groups 322 coupled to the first shift register groups SR1 can be achieved by alternately outputting the first gate scan signals to the first sub-pixel groups 322 coupled to the first shift register groups SR 1. The plurality of first shift register sets SR1 may also be the first shift register set SR1, which sequentially outputs the first gate scan signals to the first sub-pixel set 322 coupled thereto. Then, the driving method with respect to the array substrate 3 may also be divided into the first driving method and the second driving method accordingly.

Regarding the first driving method of the array substrate 3, in some embodiments provided herein, the plurality of first shift register sets SR1 alternately output the first gate scan signals to the first subpixel sets 322 coupled thereto; while each first shift register group SR1 outputs the first gate scan signal to the first subpixel group 322 coupled thereto, the second shift register group SR2 outputs the second gate scan signal to the second subpixel group 323 coupled thereto.

Illustratively, as shown in fig. 12A and 12B, at the stage P1 of the first frame image, the first start signal terminal STV1(a) of the first shift register group SR1(a) outputs a low level signal, so that the first-stage first shift register SR1(a-1) in the first shift register group SR1(a) is activated and the plurality of cascaded first shift registers SR1(a-n) are sequentially activated. Meanwhile, the second start signal terminal STV2 of the second shift register group SR2(d) outputs a low level signal, so that the first-stage second shift register SR2(d-1) in the second shift register group SR2(d) is activated, and the plurality of cascaded second shift registers SR2(d-n) are sequentially activated.

In addition, under the control of the first clock signal CK1 and the second clock signal CK2, the output terminal output (a) of each first shift register SR1(a-n) sequentially outputs a high level signal at stage P1, and the output terminal output (d) of each second shift register SR2(d-n) sequentially outputs a high level signal.

It should be noted that, in the stage P1 of the first frame image, the first start signal terminal STV1(b) of the first shift register group SR1(b) outputs a high level signal, the first-stage first shift register SR1(b-1) in the first shift register group SR1(b) is not activated, and the plurality of cascaded first shift registers SR1(b-n) are not activated. Similarly, the first start signal terminal STV1(c) of the first shift register set SR1(c) outputs a high level signal, the first stage SR1(c-1) of the first shift register set SR1(c) is deactivated, and the plurality of cascaded first shift registers SR1(c-n) is deactivated.

At the stage P2 of the first frame image, the output terminal output (a) of each first shift register SR1(a-n) sequentially outputs a low level signal under the control of the first clock signal CK1 and the second clock signal CK2, so that the output terminal output (a) of each first shift register SR1(a-n) sequentially outputs the first gate scan signal to the sub-pixels 32 in each row of the first sub-pixel group 322 coupled thereto. Meanwhile, the output terminal output (d) of each of the second shift registers SR2(d-n) sequentially outputs a low level signal, so that the output terminal output (d) of each of the second shift registers SR2(d-n) sequentially outputs the second gate scan signal to the sub-pixels 32 in the second sub-pixel group 323 of each row coupled thereto.

At the stage P3 of the first frame image, under the control of the first clock signal CK1 and the second clock signal CK2, the output terminal output (a) of each first shift register SR1(a-n) sequentially outputs a high level signal, and the output terminal output (a) of each first shift register SR1(a-n) sequentially stops outputting the first gate scan signal to the sub-pixels 32 in each row of the first sub-pixel group 322 coupled thereto. Meanwhile, the output terminal output (d) of each second shift register SR2(d-n) sequentially outputs a high level signal, and the output terminal output (d) of each second shift register SR2(d-n) is controlled to sequentially stop outputting the second gate scan signal to the sub-pixels 32 in the second sub-pixel group 323 of each row coupled thereto.

As can be seen from the above description, the first gate scan signal is output to the first subpixel group 322 coupled thereto through the first shift register group SR1 (a). At the same time, the second shift register group SR2(d) outputs the second gate scan signal to the second subpixel group 323 coupled thereto, thereby completing the display of the first frame image as shown in fig. 12A.

Illustratively, as shown in fig. 12B and 12C, at the stage P1 of the second frame image, the first start signal terminal STV1(B) of the first shift register group SR1(B) outputs a low level signal, so that the first-stage first shift register SR1(B-1) in the first shift register group SR1(B) is activated, and the plurality of cascaded first shift registers SR1(B-n) are sequentially activated; meanwhile, the second start signal terminal STV2 of the second shift register group SR2(d) outputs a low level signal, so that the first-stage second shift register SR2(d-1) in the second shift register group SR2(d) is activated, and the plurality of cascaded second shift registers SR2(d-n) are sequentially activated.

In addition, under the control of the first clock signal CK1 and the second clock signal CK2, the output terminal output (b) of each first shift register SR1(b-n) sequentially outputs a high level signal at stage P1, and the output terminal output (d) of each second shift register SR2(d-n) sequentially outputs a high level signal.

It should be noted that, in the stage P1 of the second frame image, the first start signal terminal STV1(a) of the first shift register SR1(a) group outputs a high level signal, the first-stage first shift register SR1(a-1) in the first shift register SR1(a) group is not activated, and the plurality of cascaded first shift registers SR1(a-n) are not activated; the first start signal terminal STV1(c) of the first shift register SR1(c) group outputs a high level signal, the first stage first shift register SR1(c-1) of the first shift register SR1(c) group is deactivated, and the plurality of cascaded first shift registers SR1(c-n) are deactivated.

In a stage P2 of the second frame image, the output terminal output (b) of each first shift register SR1(b-n) sequentially outputs a low level signal under the control of the first clock signal CK1 and the second clock signal CK2, so that the output terminal output (b) of each first shift register SR1(b-n) sequentially outputs the first gate scan signal to the sub-pixels 32 in each row of the first sub-pixel group 322 coupled thereto. Meanwhile, the output terminal output (d) of each of the second shift registers SR2(d-n) sequentially outputs a low level signal, so that the output terminal output (d) of each of the second shift registers SR2(d-n) sequentially outputs the second gate scan signal to the sub-pixels 32 in the second sub-pixel group 323 of each row coupled thereto.

In the stage P3 of the second frame image, under the control of the first clock signal CK1 and the second clock signal CK2, the output terminal output (b) of each first shift register SR1(b-n) sequentially outputs a high level signal, and the output terminal output (b) of each first shift register SR1(b-n) sequentially stops outputting the first gate scan signal to the sub-pixels 32 in each row of the first sub-pixel group 322 coupled thereto. Meanwhile, the output terminal output (d) of each second shift register SR2(d-n) sequentially outputs a high level signal, and the output terminal output (d) of each second shift register SR2(d-n) is controlled to sequentially stop outputting the second gate scan signal to the sub-pixels 32 in the second sub-pixel group 323 of each row coupled thereto.

As can be seen from the above description, the first gate scan signal is output to the first subpixel group 322 coupled thereto through the first shift register group SR1 (b). At the same time, the second shift register group SR2(d) outputs the second gate scan signal to the second subpixel group 323 coupled thereto, thereby completing the display of the second frame image as shown in fig. 12C.

Illustratively, as shown in fig. 12B and 12D, at the stage P1 of the third frame image, the first start signal terminal STV1(c) of the first shift register group SR1(c) outputs a low level signal, so that the first-stage first shift register SR1(c-1) in the first shift register group SR1(c) is activated and the plurality of cascaded first shift registers SR1(c-n) are sequentially activated. Meanwhile, the second start signal terminal STV2 of the second shift register group SR2(d) outputs a low level signal, so that the first-stage second shift register SR2(d-1) in the second shift register group SR2(d) is activated, and the plurality of cascaded second shift registers SR2(d-n) are sequentially activated.

In addition, under the control of the first clock signal CK1 and the second clock signal CK2, the output terminal output (c) of each first shift register SR1(c-n) sequentially outputs a high level signal at stage P1, and the output terminal output (d) of each second shift register SR2(d-n) sequentially outputs a high level signal.

In the stage P1 of the third frame image, the first start signal terminal STV1(a) of the first shift register group SR1(a) outputs a high level signal, the first-stage first shift register SR1(a-1) in the first shift register group SR1(a) is deactivated, and the plurality of cascaded first shift registers SR1(a-n) are deactivated; the first start signal terminal STV1(b) of the first shift register group SR1(b) outputs a high level signal, the first stage first shift register SR1(b-1) of the first shift register group SR1(b) is deactivated, and the plurality of cascaded first shift registers SR1(b-n) are deactivated.

At the stage P2 of the second frame image, the output terminal output (c) of each first shift register SR1(c-n) sequentially outputs a low level signal under the control of the first clock signal CK1 and the second clock signal CK2, so that the output terminal output (c) of each first shift register SR1(c-n) sequentially outputs the first gate scan signal to the sub-pixels 32 in each row of the first sub-pixel group 322 coupled thereto. Meanwhile, the output terminal output (d) of each of the second shift registers SR2(d-n) sequentially outputs a low level signal, so that the output terminal output (d) of each of the second shift registers SR2(d-n) sequentially outputs the second gate scan signal to the sub-pixels 32 in the second sub-pixel group 323 of each row coupled thereto.

At stage P3 of the third frame image, under the control of the first clock signal CK1 and the second clock signal CK2, the output terminal output (c) of each first shift register SR1(c-n) sequentially outputs a high level signal, and the output terminal output (c) of each first shift register SR1(c-n) sequentially stops outputting the first gate scan signal to the sub-pixels 32 in each row of the first sub-pixel group 322 coupled thereto. Meanwhile, the output terminal output (d) of each second shift register SR2(d-n) sequentially outputs a high level signal, and the output terminal output (d) of each second shift register SR2(d-n) is controlled to sequentially stop outputting the second gate scan signal to the sub-pixels 32 in the second sub-pixel group 323 of each row coupled thereto.

As can be seen from the above description, the first gate scan signal is output to the first subpixel group 322 coupled thereto through the first shift register group SR1 (c). Meanwhile, the second shift register group SR2(D) outputs the second gate scan signal to the second subpixel group 323 coupled thereto, thereby completing the display of the third frame image as shown in fig. 12D.

In summary, when the first, second and third frame images are displayed, the first shift register set SR1(a), the first shift register set SR1(b) and the first shift register set SR1(c) alternately output the first gate scan signal to the first sub-pixel set 322 coupled thereto. The first shift register group SR1(a), the first shift register group SR1(b), and the first shift register group SR1(c) are in an alternate cycle, and the first shift register group SR1(a), the first shift register group SR1(b), and the first shift register group SR1(c) complete an alternate cycle every three frames of images. Meanwhile, in each frame, the second shift register set SR2(d) outputs the second gate scan signal to the second subpixel group 323 coupled thereto.

That is, when the fourth, fifth, and sixth frame images are displayed, the first shift register group SR1(a), the first shift register group SR1(b), and the first shift register group SR1(c) output the first gate scan signal to the first subpixel group 322 coupled thereto in the above-described alternating manner. Meanwhile, in each frame, the second shift register set SR2(d) outputs the second gate scan signal to the second subpixel group 323 coupled thereto.

Then, when the image of the 3N +1 th frame is displayed, only the first shift register group SR1(a) and the second shift register group SR2(d) output the first gate scan signal and the second gate scan signal to the first subpixel group 322 and the second subpixel group 323 coupled corresponding thereto, respectively, that is, one third of the first subpixel group 322 and all the second subpixel groups 323 are lit, resulting in the display image shown in fig. 12A.

When the image of frame 3N +2 is displayed, only the first shift register group SR1(b) and the second shift register group SR2(d) output the first gate scan signal and the second gate scan signal to the first subpixel group 322 and the second subpixel group 323 coupled corresponding thereto, respectively, that is, the other third of the first subpixel group 322 and all the second subpixel groups 323 are lighted up, resulting in the display image shown in fig. 12C.

When the image of the 3N +3 th frame is displayed, only the first shift register group SR1(c) and the second shift register group SR2(D) output the first gate scan signal and the second gate scan signal to the first subpixel group 322 and the second subpixel group 323 coupled corresponding thereto, respectively, that is, the last third of the first subpixel group 322 and all the second subpixel groups 323 are lit up, resulting in the display image shown in fig. 12D.

The above case can also be understood that the second subpixel group 323 coupled to the second shift register group SR2(d) is lighted three times as many as the first subpixel group 322 correspondingly coupled to the first shift register group SR1(a), the first shift register group SR1(b) and the first shift register group SR1(c), respectively. It can also be understood that the driving frequency of the second shift register SR2(d) in the second shift register group SR2(d) is three times the driving frequency of the first shift register SR1(a) in the first shift register group SR1(a), the driving frequency of the second shift register SR2(d) in the second shift register group SR2(d) is three times the driving frequency of the first shift register SR1(b) in the first shift register group SR1(b), and the driving frequency of the second shift register SR2(d) in the second shift register group SR2(d) is three times the driving frequency of the first shift register SR1(c) in the first shift register group SR1 (c).

Based on this, in some embodiments provided herein, if the driving frequency of the second shift register SR2(d) in the second shift register group SR2(d) is 60Hz, the driving frequencies of the first shift register SR1(a), the first shift register SR1(b), and the first shift register SR1(a), the first shift register SR1(b), and the first shift register SR1(c) in the first shift register group SR1(c) are all 20 Hz. That is, the red and blue subpixels R and B in the first subpixel group 322 are driven by the first shift register SR1(a), SR1(B), or SR1(c) of a low frequency (20Hz), and the green subpixel G in the second subpixel group 323 is driven by the second shift register SR2(d) of a normal frequency (60 Hz).

Thus, on the one hand, since the green sub-pixel G is driven by the second shift register SR2(d) of the normal frequency (60Hz), and the red sub-pixel R and the blue sub-pixel B are driven by the first shift register SR1(a), the first shift register SR1(B), or the first shift register SR1(c) of the low frequency (e.g., 20Hz), the total power of the display device 1000 is reduced, so that the power consumption of the display device 1000 is reduced, compared to the case where the red sub-pixel R, the blue sub-pixel B, and the green sub-pixel G are all driven by the first shift register SR1 of 60Hz in the normal driving mode. On the other hand, because the green sub-pixel G is the sub-pixel 32 that mainly contributes to the luminance, and the green sub-pixel G is driven by the second shift register SR2(d) with the normal frequency (60Hz), which is the same as the frequency 60Hz of the first shift register SR1 that drives the green sub-pixel G in the normal driving mode, the structure and the driving method of the array substrate 3 according to the embodiment of the present application can prevent the duration of the light-emitting period in one frame from being extended, so that the luminance attenuation Δ L of the light-emitting device 320 in the light-emitting period in each frame will not be increased. Thus, a significant luminance difference is not likely to occur between the current frame image and the previous frame image, and the possibility of a flicker problem occurring on the display screen of the display device 1000 is not increased.

Alternatively, in other embodiments provided herein, if the driving frequency of the second shift register SR2(d) in the second shift register group SR2(d) is 90Hz, the driving frequencies of the first shift register group SR1(a), the first shift register group SR1(b), and the first shift register SR1(a), the first shift register SR1(b), and the first shift register SR1(c) in the first shift register group SR1(c) are all 30 Hz. That is, the red and blue subpixels R and B in the first subpixel group 322 are driven by the first shift register SR1(a), SR1(B), or SR1(c) of a low frequency (30Hz), and the green subpixel G in the second subpixel group 323 is driven by the second shift register SR2(d) of a high frequency (90 Hz).

Thus, on the one hand, since the green sub-pixel G is driven by the second shift register SR2(d) having a high frequency (e.g., 90Hz), and the red sub-pixel R and the blue sub-pixel B are driven by the first shift register SR1(a), the first shift register SR1(B), or the first shift register SR1(c) having a low frequency (e.g., 30Hz), the total power of the display device 1000 is reduced, so that the power consumption of the display device 1000 is reduced, compared to the case where the red sub-pixel R, the blue sub-pixel B, and the green sub-pixel G are all driven by the first shift register SR1 having 60Hz in the normal driving mode. On the other hand, since the green sub-pixel G is the sub-pixel 32 that mainly contributes to the luminance, and the green sub-pixel G is driven by the second shift register SR2(d) with a high frequency (e.g., 90Hz), which is higher than the frequency of 60Hz of the first shift register SR1 that drives the green sub-pixel G in the normal driving mode, the structure and the driving method of the array substrate 3 according to the embodiment of the present application can shorten the duration of the light-emitting period in one frame, so that the luminance attenuation Δ L of the light-emitting device 320 in the light-emitting period in each frame can be reduced. Thus, the brightness difference between the current frame image and the previous frame image is reduced, so that the possibility of the display screen of the display device 1000 having a flicker problem can be reduced, which is beneficial to the improvement of the display screen quality of the display device 1000.

In some embodiments, the plurality of first shift register sets SR1 sequentially output the first gate scan signals to the first sub-pixel sets 322 coupled thereto; while each first shift register group SR1 outputs the first gate scan signal to the first subpixel group 322 coupled thereto, the second shift register group SR2 outputs the second gate scan signal to the second subpixel group 323 coupled thereto.

For example, the display process of the first frame image is the same as that of the first driving method of the array substrate 3, and reference may be made to the description related to the first driving method for displaying the first frame image, that is, the first gate scan signal is output to the first subpixel group 322 coupled thereto only through the first shift register group SR1 (a). At the same time, the second shift register group SR2(d) outputs the second gate scan signal to the second subpixel group 323 coupled thereto, thereby completing the display of the first frame image as shown in fig. 12A.

Unlike the first driving method, the second frame image is still displayed by only outputting the first gate scan signal to the first subpixel group 322 coupled thereto through the first shift register group SR1 (a). Meanwhile, the second shift register group SR2(d) outputs the second gate scan signal to the second subpixel group 323 coupled thereto, thereby completing the display of the second frame image as shown in fig. 12A. And then sequentially repeated, for example, the display of the images of the previous thirty frames may be sequentially repeated according to the timing chart shown in fig. 13. That is, each of the first thirty frames of images is displayed by outputting the first gate scan signal to the first subpixel group 322 coupled thereto only through the first shift register group SR1 (a). Meanwhile, the second shift register group SR2(d) outputs the second gate scan signal to the second subpixel group 323 coupled thereto, thereby completing the display of each frame of image as shown in fig. 12A.

Next, from the thirty-first frame image to the sixteenth frame image, the display process of each frame image is the same as the display process of the second frame image in the first driving method of the array substrate 3, and reference may be made to the related description in the first driving method. That is, the thirty-first through sixteenth frame images are displayed such that the first gate scan signal is output to the first subpixel group 322 coupled thereto only through the first shift register group SR1 (b). Meanwhile, the second shift register group SR2(d) outputs the second gate scan signal to the second subpixel group 323 coupled thereto, thereby completing the display of each frame image as shown in fig. 12C.

Finally, the display process of each frame of image is the same as the display process of the third frame of image in the first driving method of the array substrate 3, and reference may be made to the related description in the first driving method. That is, the sixteenth through ninety frames of images are displayed such that the first gate scan signal is outputted only through the first shift register group SR1(c) to the first subpixel group 322 coupled thereto. Meanwhile, the second shift register group SR2(D) outputs the second gate scan signal to the second subpixel group 323 coupled thereto, thereby completing the display of each frame of image as shown in fig. 12D.

In summary, when displaying the first thirty frame images, the middle thirty frame images and the last thirty frame images, the first shift register set SR1(a), the first shift register set SR1(b) and the first shift register set SR1(c) sequentially output the first gate scan signal to the first subpixel group 322 correspondingly coupled thereto. Meanwhile, the second shift register group SR2(d) outputs a second gate scan signal to the second subpixel group 323 coupled thereto.

Then, in the process of displaying the 3N-frame image, only the first shift register group SR1(a) and the second shift register group SR2(d) output the first gate scan signal and the second gate scan signal to the first sub-pixel group 322 and the second sub-pixel group 323 coupled corresponding thereto, respectively, that is, one third of the first sub-pixel group 322 and all the second sub-pixel groups 323 are lighted up, so as to obtain the display image shown in fig. 12A.

The display of the middle N-frame image is such that only the first shift register group SR1(b) and the second shift register group SR2(d) output the first gate scan signal and the second gate scan signal to the first subpixel group 322 and the second subpixel group 323 coupled thereto, respectively, that is, the other third of the first subpixel group 322 and all the second subpixel groups 323 are lit up, resulting in the display image shown in fig. 12C.

The next N-frame image is displayed by only the first shift register group SR1(c) and the second shift register group SR2(D) outputting the first gate scan signal and the second gate scan signal to the first subpixel group 322 and the second subpixel group 323 coupled thereto, respectively, that is, the last third of the first subpixel group 322 and all the second subpixel groups 323 are lighted up, resulting in the display image shown in fig. 12D. Also, this case can be understood as the second subpixel group 323 coupled to the second shift register group SR2(d) is lighted three times as many as the first subpixel group 322 correspondingly coupled to the first shift register group SR1(a), the first shift register group SR1(b), and the first shift register group SR1(c), respectively.

Then, in the second driving method of the array substrate 3, it is still possible to realize that the driving frequency of the second shift register SR2(d) in the second shift register group SR2(d) is three times the driving frequency of the first shift register SR1(a) in the first shift register group SR1(a), the driving frequency of the second shift register SR2(d) in the second shift register group SR2(d) is three times the driving frequency of the first shift register SR1(b) in the first shift register group SR1(b), and the driving frequency of the second shift register SR2(d) in the second shift register group SR2(d) is three times the driving frequency of the first shift register SR1(c) in the first shift register group SR1(c), as in the first driving method.

Based on this, in other embodiments provided herein, if the driving frequency of the second shift register SR2(d) in the second shift register group SR2(d) is 90Hz, the driving frequencies of the first shift register SR1(a), the first shift register SR1(b), and the first shift register SR1(a), the first shift register SR1(b), and the first shift register SR1(c) in the first shift register group SR1(c) are all 30 Hz. That is, the red and blue subpixels R and B in the first subpixel group 322 are driven by the first shift register SR1(a), SR1(B), or SR1(c) of a low frequency (30Hz), and the green subpixel G in the second subpixel group 323 is driven by the second shift register SR2(d) of a high frequency (90 Hz). Thus, on the one hand, since the green sub-pixel G is driven by the second shift register SR2(d) having a high frequency (e.g., 90Hz), and the red sub-pixel R and the blue sub-pixel B are driven by the first shift register SR1(a), the first shift register SR1(B), or the first shift register SR1(c) having a low frequency (e.g., 30Hz), the total power of the display device 1000 is reduced, so that the power consumption of the display device 1000 is reduced, compared to the case where the red sub-pixel R, the blue sub-pixel B, and the green sub-pixel G are all driven by the first shift register SR1 having 60Hz in the normal driving mode. On the other hand, since the green sub-pixel G is the sub-pixel 32 that mainly contributes to the luminance, and the green sub-pixel G is driven by the second shift register SR2(d) with a high frequency (e.g., 90Hz), which is higher than the frequency of 60Hz of the first shift register SR1 that drives the green sub-pixel G in the normal driving mode, the structure and the driving method of the array substrate 3 according to the embodiment of the present application can shorten the duration of the light-emitting period in one frame, so that the luminance attenuation Δ L of the light-emitting device 320 in the light-emitting period in each frame can be reduced. Thus, the brightness difference between the current frame image and the previous frame image is reduced, so that the possibility of the display screen of the display device 1000 having a flicker problem can be reduced, which is beneficial to the improvement of the display screen quality of the display device 1000.

Also, it can be understood that, in the case where two rows of the first subpixel groups 322 are disposed between the adjacent second subpixel groups 323:

in the first driving method of the array substrate 3, during the first frame image and the second frame image, the first shift register sets SR1(a) and SR1(b) alternately output the first gate scan signals to the first sub-pixel set 322 coupled thereto. The first shift register group SR1(a) and the first shift register group SR1(b) are an alternate cycle, and every two frames of images, the first shift register group SR1(a) and the first shift register group SR1(b) complete an alternate cycle. Meanwhile, in each frame, the second shift register set SR2(d) outputs the second gate scan signal to the second subpixel group 323 coupled thereto.

In the second driving method of the array substrate 3, during the 2N-frame image display, only the first shift register set SR1(a) and the second shift register set SR2(d) output the first gate scan signal and the second gate scan signal to the first subpixel set 322 and the second subpixel set 323 coupled thereto, respectively, that is, one half of the first subpixel set 322 and all the second subpixel sets 323 are turned on.

The next N-frame image is displayed such that only the first shift register group SR1(b) and the second shift register group SR2(d) output the first gate scan signal and the second gate scan signal to the first subpixel group 322 and the second subpixel group 323 coupled thereto, respectively, i.e., the other half of the first subpixel group 322 and all the second subpixel groups 323 are lit.

Based on this, in the case where two rows of the first subpixel groups 322 are disposed between the adjacent second subpixel groups 323, the driving frequency of the second shift register SR2(d) in the second shift register group SR2(d) is twice the driving frequency of the first shift register SR1(a) in the first shift register group SR1(a), and the driving frequency of the second shift register SR2(d) in the second shift register group SR2(d) is twice the driving frequency of the first shift register SR1(b) in the first shift register group SR1 (b).

Likewise, it can be understood that, in the case where M rows of the first subpixel groups 322 are disposed between the adjacent second subpixel groups 323: the driving frequency of the second shift register SR2(d) in the second shift register set SR2(d) is M times the driving frequency of the first shift register in each first shift register set SR 1.

Example three

The difference between the third example and the second example is that one first sub-pixel group 322 is disposed between adjacent second sub-pixel groups 323 on the array substrate 3 in the third example. Regarding the plurality of sub-pixels 32, in the present example, as shown in fig. 14A, the plurality of sub-pixels 32 may be also divided into a first sub-pixel group 322 and a second sub-pixel group 323.

In some embodiments provided herein, as shown in fig. 14A, the first sub-pixel group 322 includes red sub-pixels R and blue sub-pixels B alternately arranged; the second subpixel group 323 includes a green subpixel G.

It should be noted that, regarding the way in which the red sub-pixel R and the blue sub-pixel B are alternately arranged, the same in this example as in the second example can refer to the related description in the second example, and the description is not repeated here.

In some embodiments provided herein, as shown in fig. 14A, the red sub-pixel R and the blue sub-pixel B in the same first sub-pixel group 322 are located in the same row. That is, in the embodiment of the present application, the plurality of sub-pixels are divided into a plurality of rows, and a row of sub-pixels may include a red sub-pixel R and a blue sub-pixel B, and the row of sub-pixels is referred to as a first sub-pixel group 322. As in example two, reference may be made to the associated description in example two.

In other embodiments provided herein, the green sub-pixels G in the same second sub-pixel group 323 are located in the same row. That is, in the embodiment of the present application, the plurality of sub-pixels are divided into a plurality of rows, and a row of sub-pixels may also include a green sub-pixel G, and the row of sub-pixels is referred to as a second sub-pixel group 323. As in example two, reference may be made to the associated description in example two.

In this example, one first subpixel group 322 is disposed between adjacent second subpixel groups 323.

Illustratively, as shown in fig. 14A, one first sub-pixel group 322 is disposed between the adjacent second sub-pixel groups 323, and the corresponding gate driving circuit 33 includes two first shift register groups SR1(a first shift register group SR1(a), a first shift register group SR1(b)) and a second shift register group SR 2.

Illustratively, as shown in fig. 14B, one first sub-pixel group 322 is disposed between the adjacent second sub-pixel groups 323, and the corresponding gate driving circuit 33 includes three first shift register groups SR1(a first shift register group SR1(a), a first shift register group SR1(B), a first shift register group SR1(c)) and a second shift register group SR 2.

Each of the first shift register sets SR1 includes a plurality of cascaded first shift registers SR1, the first shift register SR1 is coupled to the pixel circuits D of the sub-pixels 32 (red sub-pixel R and blue sub-pixel B) in the first sub-pixel set 322, and the first shift register SR1 is configured to provide gate scan signals to the pixel circuits D of the sub-pixels 32 in the first sub-pixel set 322.

It is understood that the first shift register SR1 is coupled to the first sub-pixel group 322, and in fact the first shift register SR1 is coupled to the pixel circuit D of the sub-pixel 32 in the first sub-pixel group 322. Similarly, the second shift register SR2 is coupled to the second sub-pixel group 323, and in this case, the second shift register SR2 is coupled to the pixel circuit D of the sub-pixel 32 in the second sub-pixel group 323.

In other embodiments provided herein, as shown in FIG. 14A, the first shift register SR1 and the first subpixel group 322 coupled thereto may be located in the same row, and the second shift register SR2 and the second subpixel group 323 coupled thereto may be located in the same row. It will also be appreciated that the first shift register SR1 is located in the same row as the subpixels 32 in the first subpixel group 322 coupled thereto, and the second shift register SR2 is located in the same row as the subpixels 32 in the second subpixel group 323 coupled thereto.

Regarding the structure of the shift register SR, the structure of the shift register SR in this example is the same as that of the shift register SR in the second example, and reference may be made to the related description in the second example, which is not repeated herein.

In some embodiments provided herein, as shown in fig. 14B, the gate driving circuit 33 includes three first shift register groups SR1 and three second shift register groups SR2, which may be, for example, a first shift register group SR1(a), a first shift register group SR1(B), a first shift register group SR1(c), and a second shift register group SR2 (d).

In other embodiments provided herein, as shown in fig. 14A, the gate driving circuit 33 includes two first shift register groups SR1 and two second shift register groups SR2, which may be, for example, a first shift register group SR1(a), a first shift register group SR1(b), and a second shift register group SR 2.

In this example, the gate driving circuit 33 includes two first shift register groups SR1 and two second shift register groups SR 2.

Wherein each first shift register group SR1 includes a plurality of cascaded first shift registers SR1, that is, the first shift register group SR1(a) includes a plurality of cascaded first shift registers SR1(a-1), SR1(a-2) … … and SR1 (a-n). The first shift register group SR1(b) includes a first shift register SR1(b-1), a first shift register SR1(b-2) … …, a first shift register SR1 (b-n).

The second shift register group SR2 includes a plurality of cascaded second shift registers SR2, that is, the second shift register group SR2(d) includes a plurality of cascaded second shift registers SR2(d-1), SR2(d-2) … … and SR2 (d-n). In addition, the cascade connection manner of the plurality of first shift registers SR1(a-n) in the first shift register group SR1(a), the cascade connection manner of the plurality of first shift registers SR1(b-n) in the first shift register group SR1(b), and the cascade connection manner of the plurality of second shift registers SR2(d-n) in the second shift register group SR2(d) are the same as those in the second example, and reference may be made to the description in the second example for description, which is not repeated herein.

In some embodiments provided herein, one first sub-pixel group 323 is disposed between adjacent second sub-pixel groups 323. The adjacent first sub-pixel group 323 is coupled to the first shift register SR1 of the different first shift register group SR 1.

Illustratively, as shown in fig. 14A, one first sub-pixel group 322 is disposed between the second sub-pixel group 323 of the second row and the second sub-pixel group 323 of the fourth row from top to bottom. Another first sub-pixel group 322 is disposed between the second sub-pixel group 323 of the fourth row and the second sub-pixel group 323 of the sixth row.

The pixel circuits D of the sub-pixels 32 in the first sub-pixel group 322 in the third row are coupled to the first-stage first shift register SR1(b-1) in the first shift register group SR1(b), and the pixel circuits D of the sub-pixels 32 in the first sub-pixel group 322 in the fifth row are coupled to the second-stage first shift register SR1(a-2) in the first shift register group SR1 (a).

That is, the first sub-pixel groups 322 coupled to the first shift register SR1 of the first shift register group SR1(a) and the first sub-pixel groups 322 coupled to the first shift register SR1 of the first shift register group SR1(b) are arranged on the array substrate 3 in a one-to-one alternating cyclic manner, and when one of the first sub-pixel groups 322 is lit during the display driving process, the lit first sub-pixel groups 322 and the unlit first sub-pixel groups 322 can be alternately arranged. Thus, the entire display area AA can be uniformly covered by the lighted first sub-pixel group 322 in each frame of the display panel, and the display panel 1 is not half lighted. Therefore, the brightness displayed by the display device 1000 is uniform in different time periods, which is beneficial to improving the display image quality of the display device 1000.

In some embodiments provided herein, as shown in fig. 14A, the arrangement rule of the red sub-pixel R and the blue sub-pixel B in the adjacent first sub-pixel group 322 may be different. From top to bottom, in the first sub-pixel group 322 of the third row, a blue sub-pixel B is arranged first, and then a red sub-pixel R is arranged, and the arrangement is cyclically and alternately. In the first subpixel group 322 of the fifth row, one blue subpixel B is arranged first, and then one red subpixel R and one red subpixel R are arranged, and are sequentially and cyclically arranged alternately.

Regarding the driving method of the array substrate 3, the same as the driving method of the array substrate 3 in the second example can refer to the related description in the second example, and the description thereof is omitted here.

In some embodiments provided herein, the gate driving circuit 33 includes a first shift register set SR1(a), a first shift register set SR1(b), and a second shift register set SR2(d), and the relationship between the multiple of the driving frequency of the second shift register SR2(d) in the second shift register set SR2(d) and the driving frequency of the first shift register SR1(a) in the first shift register set SR1(a), and the multiple of the driving frequency of the second shift register SR2(d) in the second shift register set SR2(d) and the driving frequency of the first shift register SR1(b) in the first shift register set SR1(b) during the display driving process has an effect. The above-mentioned multiple relationship between the driving frequencies is not related to whether the array substrate 3 adopts the first driving method or the array substrate 3 adopts the second driving method. For convenience of explanation, the change of the multiple relationship between the driving frequencies is explained by taking the first driving method as an example of the array substrate 3.

In some embodiments provided herein, in conjunction with the timing diagram of fig. 15A, when the 2N +1 th frame image is displayed, only the first shift register set SR1(a) and the second shift register set SR2(d) output the first gate scan signal and the second gate scan signal to the first sub-pixel set 322 and the second sub-pixel set 323 respectively coupled thereto, that is, one half of the first sub-pixel set 322 and all the second sub-pixel sets 323 are lighted, so as to obtain the display image shown in fig. 15B. When the 2N +2 th frame image is displayed, only the first shift register group SR1(b) and the second shift register group SR2(d) output the first gate scan signal and the second gate scan signal to the first subpixel group 322 and the second subpixel group 323 coupled corresponding thereto, respectively, that is, the other half of the first subpixel group 322 and all of the second subpixel groups 323 which are not lit in the previous frame image are lit, resulting in the display image shown in fig. 15C. The above case can also be understood as the second subpixel group 323 coupled to the second shift register group SR2(d) is lighted twice as many times as the first subpixel group 322 correspondingly coupled to the first shift register group SR1(a) and the first shift register group SR1(b), respectively. It can also be understood that the driving frequency of the second shift register SR2(d) in the second shift register group SR2(d) is twice the driving frequency of the first shift register SR1(a) in the first shift register group SR1(a), and the driving frequency of the second shift register SR2(d) in the second shift register group SR2(d) is twice the driving frequency of the first shift register SR1(b) in the first shift register group SR1 (b).

Based on this, in some embodiments provided herein, if the driving frequency of the second shift register SR2(d) in the second shift register group SR2(d) is 60Hz, the driving frequencies of the first shift register SR1(a) and the first shift register SR1(b) in the first shift register group SR1(a) and the first shift register group SR1(b) are both 30 Hz. That is, the red subpixel R and the blue subpixel B in the first subpixel group 322 are driven by the first shift register SR1(a) or the first shift register SR1(B) of a low frequency (30Hz), and the green subpixel G in the second subpixel group 323 is driven by the second shift register SR2(d) of a normal frequency (60 Hz).

Thus, on the one hand, since the green sub-pixel G is driven by the second shift register SR2(d) of the normal frequency (60Hz), and the red sub-pixel R and the blue sub-pixel B are driven by the first shift register SR1(a) or the first shift register SR1(B) of the low frequency (e.g., 30Hz), the total power of the display device 1000 is reduced, so that the power consumption of the display device 1000 is reduced, compared to the case where the red sub-pixel R, the blue sub-pixel B, and the green sub-pixel G are all driven by the first shift register SR1 of 60Hz in the normal driving mode. On the other hand, because the green sub-pixel G is the sub-pixel 32 that mainly contributes to the luminance, and the green sub-pixel G is driven by the second shift register SR2(d) with the normal frequency (60Hz), which is the same as the frequency 60Hz of the first shift register SR1 that drives the green sub-pixel G in the normal driving mode, the structure and the driving method of the array substrate 3 according to the embodiment of the present application can prevent the duration of the light-emitting period in one frame from being extended, so that the luminance attenuation Δ L of the light-emitting device 320 in the light-emitting period in each frame will not be increased. Thus, a significant luminance difference is not likely to occur between the current frame image and the previous frame image, and the possibility of a flicker problem occurring on the display screen of the display device 1000 is not increased.

Alternatively, in other embodiments provided herein, if the driving frequency of the second shift register SR2(d) in the second shift register group SR2(d) is 80Hz, the driving frequencies of the first shift register group SR1(a) and the first shift register group SR1(b) and the first shift register group SR1(a) and the first shift register group SR1(b) in the first shift register group SR1(c) are both 40 Hz. That is, the red subpixel R and the blue subpixel B in the first subpixel group 322 are driven by the first shift register SR1(a) or the first shift register SR1(B) of a low frequency (40Hz), and the green subpixel G in the second subpixel group 323 is driven by the second shift register SR2(d) of a high frequency (80 Hz).

Thus, on the one hand, since the green sub-pixel G is driven by the second shift register SR2(d) having a high frequency (e.g., 80Hz), and the red sub-pixel R and the blue sub-pixel B are driven by the first shift register SR1(a) or the first shift register SR1(B) having a low frequency (e.g., 40Hz), the total power of the display device 1000 is reduced, so that the power consumption of the display device 1000 is reduced, compared to the case where the red sub-pixel R, the blue sub-pixel B, and the green sub-pixel G are all driven by the first shift register SR1 having 60Hz in the normal driving mode. On the other hand, since the green sub-pixel G is the sub-pixel 32 that mainly contributes to the luminance, and the green sub-pixel G is driven by the second shift register SR2(d) with a high frequency (e.g., 80Hz), which is higher than the frequency of 60Hz of the first shift register SR1 that drives the green sub-pixel G in the normal driving mode, the structure and the driving method of the array substrate 3 according to the embodiment of the present application can shorten the duration of the light-emitting period in one frame, so that the luminance attenuation Δ L of the light-emitting device 320 in the light-emitting period in each frame can be reduced. Thus, the brightness difference between the current frame image and the previous frame image is reduced, so that the possibility of the display screen of the display device 1000 having a flicker problem can be reduced, which is beneficial to the improvement of the display screen quality of the display device 1000.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. An array substrate, comprising:

a gate driving circuit including a plurality of first shift register groups and second shift register groups; each of the first shift register groups includes a plurality of cascaded first shift registers, and the second shift register group includes a plurality of cascaded second shift registers; the plurality of first shift register groups are used for time-sharing driving;

a plurality of sub-pixels divided into a first sub-pixel group and a second sub-pixel group; the first sub-pixel group comprises red sub-pixels and blue sub-pixels which are alternately arranged; the second sub-pixel group comprises green sub-pixels;

the first shift register is coupled with the first sub-pixel group; the second shift register is coupled with the second sub-pixel group;

at least one first sub-pixel group is arranged between the adjacent second sub-pixel groups.

2. The array substrate of claim 1, wherein a plurality of first sub-pixel groups are disposed between adjacent second sub-pixel groups, and different first sub-pixel groups between adjacent second sub-pixel groups are coupled to the first shift registers in different first shift register groups.

3. The array substrate of claim 2, wherein the relative position relationship between each of the first sub-pixel groups coupled to the first shift register in the same first shift register group and the respective reference sub-pixel groups is the same;

wherein the reference sub-pixel group is the second sub-pixel group adjacent to the first sub-pixel group along a first direction; the first direction is a direction intersecting with a row direction of the sub-pixels.

4. The array substrate of claim 3, wherein the first shift registers and the second shift registers of the first shift register groups are cyclically and alternately arranged;

the first shift register and the first sub-pixel group coupled with the first shift register are located on the same row, and the second shift register and the second sub-pixel group coupled with the second shift register are located on the same row.

5. The array substrate of claim 3, wherein the first sub-pixel groups coupled to the first shift register in the same first shift register group include red sub-pixels and blue sub-pixels that are not arranged in the same order.

6. The array substrate of claim 1, wherein one of the first sub-pixel groups is disposed between adjacent second sub-pixel groups, and adjacent first sub-pixel groups are coupled to the first shift registers of different first shift register groups.

7. The array substrate of claim 6, wherein the red sub-pixels and the blue sub-pixels in adjacent first sub-pixel groups are arranged in different patterns.

8. The array substrate of any one of claims 1-7, wherein the red sub-pixels and the blue sub-pixels in the same first sub-pixel group are located in the same row;

and/or the presence of a gas in the gas,

the green sub-pixels in the same second sub-pixel group are located in the same row.

9. The array substrate of any of claims 1-7, wherein each of the first shift register sets is coupled to a first start signal terminal, and the second shift register sets is coupled to a second start signal terminal.

10. The array substrate of claim 9, wherein the first output terminal of the first shift register of the previous stage in each of the first shift register sets is coupled to the first input terminal of the first shift register of the next stage;

and/or the presence of a gas in the gas,

the second output end of the second shift register of the previous stage in the second shift register group is coupled with the second input end of the second shift register of the next stage.

11. A display device comprising the array substrate according to any one of claims 1 to 10;

the display device comprises a display area and a peripheral area positioned at the periphery of the display area, a gate driving circuit in the array substrate is positioned at the peripheral area, and sub-pixels in the array substrate are positioned in the display area.

12. A driving method of the array substrate according to any one of claims 1 to 10, comprising:

the plurality of first shift register groups output first grid scanning signals to the first sub-pixel groups coupled with the first shift register groups in a time-sharing mode;

while each of the first shift register groups outputs a first gate scan signal to a first subpixel group coupled thereto, the second shift register group outputs a second gate scan signal to a second subpixel group coupled thereto.

13. The method of claim 12, wherein the outputting the first gate scan signal to the first sub-pixel group coupled to the first shift register group in a time-sharing manner comprises:

the plurality of first shift register groups alternately output first grid scanning signals to first sub-pixel groups coupled with the first shift register groups;

or,

the plurality of first shift register groups sequentially output first grid scanning signals to the first sub-pixel groups coupled with the first shift register groups respectively.