CN113189845A - Target pattern mask optimization method based on artificial expectation - Google Patents

Target pattern mask optimization method based on artificial expectation Download PDF

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CN113189845A
CN113189845A CN202110103267.3A CN202110103267A CN113189845A CN 113189845 A CN113189845 A CN 113189845A CN 202110103267 A CN202110103267 A CN 202110103267A CN 113189845 A CN113189845 A CN 113189845A
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pattern
target pattern
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彭飞
宋毅
桂成群
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Wuhan University WHU
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/70508—Data handling in all parts of the microlithographic apparatus, e.g. handling pattern data for addressable masks or data transfer to or from different components within the exposure apparatus
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G03F7/70441—Optical proximity correction [OPC]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T11/00—2D [Two Dimensional] image generation
    • G06T11/60—Editing figures and text; Combining figures or text
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/10—Segmentation; Edge detection
    • G06T7/13—Edge detection
    • G—PHYSICS
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    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30108—Industrial image inspection
    • G06T2207/30148—Semiconductor; IC; Wafer

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Abstract

The invention provides a target pattern mask optimization method based on artificial expectation, which comprises the following steps: converting the target pattern into a pixelized pattern, extracting a high-frequency region and a high-frequency point of the pixelized pattern, and further constructing an expected target pattern based on artificial expectation; taking the numerical value of the expected target pattern as a pixelized numerical value of the wafer circuit board image to construct a cost function and a constraint condition; and updating the mask value of the expected target pattern according to the constraint condition. The invention reduces the high-frequency signal of the target pattern to a range which can be compensated without changing the main characteristics of the circuit, and then compensates the new target pattern, so that the high-frequency signal of the pattern is recovered, the image fidelity is improved, and the pattern error and the edge placement error of the wafer pattern are further reduced; meanwhile, the manufacturability of the process is greatly improved, so that the pattern error and the edge placement error of the wafer pattern are further reduced.

Description

Target pattern mask optimization method based on artificial expectation
Technical Field
The invention belongs to the technical field of optical proximity correction in the photoetching resolution enhancement technology, and particularly relates to a target pattern mask optimization method based on artificial expectation.
Background
As a key step of Integrated Circuits (ICs), the projection lithography technique is suitable for manufacturing ultra-large integrated circuits with micro-nano line width.
The projection lithography system mainly comprises: illumination source, mask, projection objective, pupil, transmission medium and photoresist-coated silicon wafer. Polarized waves emitted by the light source penetrate through the mask to generate a mask near field, and the mask pattern is transferred to the surface of the silicon wafer through projection of the projection objective, low-pass filtering of the pupil, the action of the transmission medium and etching of the photoresist. However, the low-pass filtering causes the high-frequency signal of the pattern to be seriously lost during the transfer process, and the shape of the pattern is distorted.
With the continued shrinkage of Critical Dimensions (CD), projection lithography systems face unprecedented challenges. The reduction of the wavelength λ of the illumination light source and the improvement of the Numerical Aperture (NA) are both upgrading of the lithography model, so that the improvement of the manufacturability of the process by using Resolution Enhancement Techniques (RETs) is the most effective means based on the existing model or equipment. Optical Proximity Correction (OPC) is mainly performed by simulating the light source and the mask and calculating to compensate for the Optical Proximity Effect (OPE) caused by low-pass filtering. In addition, OPC can also be used in the photolithography process for engineering applications such as Organic Light Emitting Diodes (OLEDs), micro-electro-mechanical systems (MEMS), and Printed Circuit Boards (PCBs).
Mask Optimization (MO) is a model-based Inverse Lithography Technology (ILT) proposed in recent years, and its compensation process has the advantage of disregarding the circuit topology and related design rules, and in addition, the ILT can theoretically find out the optimal pattern design to compensate OPE, which is one of the most potential OPC technologies below 22nm node. The MO calculation strategy is to perform pixelization processing on the mask, change the intensity value of the mask pixel by constructing a cost function and calculating related variables, and search out an optimal intensity value to improve the urban imaging performance. However, increasingly dense circuit layout designs and CD proximity to the exposure limit place higher demands on OPC technology.
Most of the conventional MO methods are based on convex optimization algorithm of target pattern, and the high frequency signal and high frequency point of the target pattern are more, and the optical compensation of these high frequency signals is still strictly limited by low pass filtering, that is: the compensated image still loses the high frequency signal and the compensation effect is only effective in the low frequency region.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a target pattern mask optimization method based on artificial expectation, which is used for reducing the high-frequency signal of a target pattern to a range capable of being compensated on the premise of not changing the main characteristics of a circuit, then compensating a new target pattern, recovering the high-frequency signal of the pattern, improving the image fidelity and further reducing the pattern error and the edge placement error of a wafer pattern.
In order to solve the technical problems, the invention adopts the following technical scheme:
a target pattern mask optimization method based on artificial expectations, comprising the steps of:
step S1, converting the target pattern into a pixelized pattern, extracting high-frequency regions and high-frequency points of the pixelized pattern, and further constructing an expected target pattern based on artificial expectation;
step S2, taking the numerical value of the expected target pattern as the pixilated numerical value of the wafer circuit board image to construct a cost function and constraint conditions;
and step S3, updating the mask value of the expected target pattern according to the constraint condition.
Further, the step S1 includes:
step S11, performing pixelization processing on the mask graph of the target pattern to obtain a mask layout matrix before preprocessing, and obtaining a pattern edge through Gaussian convolution to obtain a high-frequency signal;
step S12, obtaining the corner of the pattern by solving partial differential of the pattern edge to obtain a high frequency point;
step S13, generating an auxiliary pattern according to the obtained high-frequency signal and the high-frequency point and based on a preset rule;
step S14, superimposing the generated auxiliary pattern on the target circuit board diagram to obtain the desired target pattern expected by human;
and step S15, performing smoothing processing on the expected target pattern expected in the construction period of the people.
Further, the step S2 includes:
according to the imaging performance of an actual projection lithography system and pattern errors and edge placement errors in the reverse compensation process, evaluating and calculating, and constructing a cost function and constraint conditions based on a pattern form student adult period expectation layout, namely:
Figure BDA0002916804020000021
s.t.M(θ)＝(1+cosθ)/2
wherein, IARIs an artificial expectation layout; Ψ {. denotes the mapping of DUV imaging for calculating wafer pattern Iwafer(ii) a A cost function of
Figure BDA0002916804020000031
And it is defined as a Pattern Error (PE); the constraint is M (θ) ═ 1+ cos θ)/2.
Further, the step S3 includes:
step S31, initializing the light source J and the mask M as numerical matrixes, and setting iteration times;
step S32, constructing a deep ultraviolet photoetching projection matrix;
step S33, constructing MO frame according to the expected target pattern expected by human;
step S34, carrying out derivation on the cost function to obtain a corresponding gradient;
and step S35, updating the mask value according to the steepest gradient descent method.
Further, in the step S13, an additional auxiliary region is added at the high frequency signal of the circuit board diagram to reduce the high frequency signal of the target layout.
Further, the auxiliary region has a circular structure with values gradually decreasing from the center to both sides.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, through the pretreatment of the target pattern, the auxiliary area is added at the high-frequency point of the target pattern and smooth treatment is carried out, so that the high-frequency signal is effectively reduced to an optimized range, and the high-frequency signal is recovered; meanwhile, the manufacturability of the process is greatly improved, so that the pattern error and the edge placement error of the wafer pattern are further reduced.
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FIG. 1 is a flowchart of a mask optimization method based on an artificial expected layout according to an embodiment of the present invention;
FIG. 2 is a block diagram of an artificial expected version generation module according to an embodiment of the present invention;
FIG. 3 is a high frequency information extraction module of a target layout according to an embodiment of the present invention;
FIG. 4 is a block diagram of a calculation module for an artificial expected layout according to an embodiment of the present invention;
FIG. 5 is a comparison of the present method and conventional method of embodiments of the present invention;
FIG. 6 is a comparison of a flow chart of a method of an embodiment of the present invention and a flow chart of a conventional method;
FIG. 7 shows an unoptimized mask I according to an embodiment of the present invention01Projection imaging and EPE;
FIG. 8 shows the results of MO using a conventional method according to an embodiment of the present invention;
FIG. 9 shows the results of MO using a pre-treatment method according to an embodiment of the present invention;
FIG. 10 shows an unoptimized mask I according to an embodiment of the present invention02Projection imaging and EPE;
FIG. 11 shows the results of MO using a conventional method according to an embodiment of the present invention;
fig. 12 shows the result of MO using the pretreatment method according to the embodiment of the present invention.
Detailed Description
The invention will be further described with reference to examples of embodiments shown in the drawings.
As shown in fig. 1 to fig. 1, the present embodiment provides a target pattern mask optimization method based on artificial expectation, which is a preprocessing method for a target circuit board diagram and a Mask Optimization (MO) based on an artificial target pattern, and can recover a high frequency signal of a pattern and improve image fidelity, and the method specifically includes the following steps:
step S1, converting the target pattern into a pixelized pattern and extracting high frequency regions and high frequency points of the pixelized pattern, and further constructing a desired target pattern based on artificial expectation. The specific process of step S1 includes:
and step S11, performing pixelization processing on the mask graph of the target pattern to obtain a mask layout matrix before preprocessing, and obtaining a pattern edge through Gaussian convolution to obtain a high-frequency signal.
The specific method comprises the following steps: performing pixelization processing on the mask graph to obtain M, and obtaining a pattern edge I through Gaussian convolutioneI.e., high frequency signals, the following expression:
Figure BDA0002916804020000041
wherein, IeRepresenting the pattern edges, M is the pixelized mask,
Figure BDA0002916804020000042
is a kernel of a gaussian convolution with the result that,
Figure BDA0002916804020000043
representing a convolution.
And step S12, obtaining the corners of the pattern by solving partial differential of the pattern edges to obtain high frequency points. The specific method comprises the following steps: by the pair IeObtaining patterns by solving partial differentialsCorner, i.e. high frequency point IpsThe following expression:
Figure BDA0002916804020000044
wherein, IpsWhich represents the corners of the pattern,
Figure BDA0002916804020000045
the differential is indicated.
Step S13, generating an auxiliary pattern according to the obtained high-frequency signal and high-frequency point and based on a preset rule, and specifically obtaining the following expression:
Ias＝Γ(Ips)
wherein, Γ (-) represents an auxiliary pattern generation method corresponding to different circuit layout features, IasIs an auxiliary pattern;
in addition, in step S13, an additional auxiliary region is added at the high-frequency signal of the circuit board diagram to lower the target layout high-frequency signal, and the structure of the auxiliary region is a circular region with values gradually decreasing from the center to both sides.
Step S14, superimposing the generated auxiliary pattern on the target circuit board diagram to obtain an artificially expected target pattern, specifically obtaining the following expression:
IAR＝Ias+M
wherein, IARIs an artificially desired target pattern.
Step S15, performing smoothing processing on the artificially expected target pattern, specifically obtaining the following expression:
Figure BDA0002916804020000051
as shown in fig. 2(a) -2 (d), a schematic diagram of the solution is calculated for the expected layout for a construction period. (a) The target pattern, (b) the extracted high-frequency region, (c) the extracted high-frequency point, and (d) the calculated artificial expected layout. The generation scheme is divided into four steps, which are defined as a high-frequency information extraction module and a layout calculation module, and respectively correspond to fig. 3 and fig. 4.
As shown in fig. 3(a) -3 (c), a high frequency information extraction module. The target pattern (a) is convolved to obtain a high-frequency region (b), and the partial differentiation is performed to the high-frequency region (b) to obtain a high-frequency bin (c).
As shown in fig. 4(a) -4 (d), a layout calculation module is provided. And (b) and (c) are superposed to obtain a preliminary artificial expected layout (d), and the numerical value of (d) is constrained to achieve the purpose of smoothing the pattern edge.
And step S2, taking the numerical value of the expected target pattern as the pixilated numerical value of the wafer circuit board image to construct a cost function and a constraint condition.
In step S2, a cost function and constraint conditions are constructed according to the imaging performance of the actual projection lithography system and the pattern error (PE for short) and edge placement error (EPE for short) in the reverse compensation process, and based on the expected layout of the pattern morphology student in the adult period, that is:
Figure BDA0002916804020000053
s.t.M(θ)＝(1+cosθ)/2
wherein, IarIs an artificial expectation layout; Ψ {. denotes the mapping of DUV imaging for calculating wafer pattern Iwafer(ii) a Cost function
Figure BDA0002916804020000052
Defined as Pattern Error (PE), ensuring optimization to proceed in the direction of decreasing pattern error PE; the constraint M (θ) — (1+ cos θ)/2 guarantees the generation of the binary mask.
Step S3, updating the mask value of the desired target pattern according to the constraint condition. The specific process of step S3 includes:
step S31, initializing the light source J and the mask M as a numerical matrix, and setting the number of iterations.
Step S32, constructing a Deep ultraviolet lithography (DUV) projection matrix, which includes the following specific expression:
I＝Ψ(J，M(θ))＝Sig(Iwsfer(θ))
where Ψ {. denotes the mapping of DUV imaging, Iwafer(. DEG) is the projected image intensity of the silicon wafer surface, Sig is the etch function, describing the chemical etch effect, expressed as
Figure BDA0002916804020000061
And the etching amplitude a is 85, and the etching threshold t isr＝0.25。
Step S33, constructing MO frame according to the expected target pattern expected by human; in this step, the preprocessed circuit board diagram (artificially expected target pattern) is used as a target pattern, and the MO is configured as follows:
Figure BDA0002916804020000062
s.t.M(θ)＝(1+cosθ)/2
wherein the content of the first and second substances,
Figure BDA0002916804020000063
is the square of the L-2 norm, J represents the pixelated illuminant, M represents the numerical intensity of the pixelated mask, M is constrained between 0 and 1 during the optimization process, and the optimized mask value satisfies M e {0, 1 }.
Step S34, cost function
Figure BDA0002916804020000064
The derivation is performed to obtain the corresponding gradient as follows:
Figure BDA0002916804020000065
wherein the content of the first and second substances,
Figure BDA0002916804020000066
representing the derivative of the cost function on theta before the kth iteration, according to the abbe imaging principle,
Figure BDA0002916804020000067
is the sum of the intensities of the light sources of the partially coherent light,
Figure BDA0002916804020000068
corresponds to (alpha)s，βs) The intensity of the point light source is measured,
Figure BDA0002916804020000069
is corresponding to
Figure BDA00029168040200000610
The mask near field approximation term of (c), the upper right-hand corner represents the conjugate,
Figure BDA00029168040200000611
is corresponding to
Figure BDA00029168040200000612
The upper right-hand omicron of (a) represents ninety degrees from the conjugate and rotation matrix,
Figure BDA00029168040200000613
d1＝(I-IAR)⊙I⊙(1-I),
Figure BDA00029168040200000614
an element indicating a convolution, an indication of a corresponding position, is multiplied.
Step S35, updating the mask value θ according to a Steepest Gradient (SGD) method:
Figure BDA00029168040200000615
and (5) carrying out mask optimization by continuously repeating the steps S31 to S35 until the iteration is finished.
In the embodiment, through the processing of the target pattern, the auxiliary region is added at the high-frequency point of the target pattern and smooth processing is performed, so that the high-frequency signal is effectively reduced to an optimized range, and the high-frequency signal is recovered; meanwhile, the manufacturability of the process is greatly improved, so that the pattern error (PE for short) and the edge placement error (EPE for short) of the wafer pattern are further reduced.
On the other hand, the generated I is processed by the target expected layout processing method of the embodimentarComparing with the original target expected layout I0The high-frequency signals are less, the pattern edge is smoother, the compensability is higher, the topological structures of the two groups of circuit layouts have no obvious difference, and the optimizing performance is further improved.
The method is illustrated below by specific test data:
in the test process, firstly, a light source J and a target expected layout I are respectively arranged0Rasterization processing to Ns×NsAnd an NxN region, constructing an artificial expected layout by a high-frequency signal extraction and corresponding generation method, specifically comprising:
step S11 for I0Performing edge extraction to obtain a high-frequency signal, namely an outermost layer edge of image distortion, wherein the calculation mode is as follows:
Figure BDA0002916804020000071
step S12 for IeInflection point extraction is carried out to obtain high frequency points with higher frequency, namely, areas which are difficult to compensate by using the existing method are calculated in the following way:
Figure BDA0002916804020000072
step S13, at IpsNearby generation of auxiliary region f { IpsAnd overlaying on the target expected layout:
IAR＝Ias+M
step S14, restraining the person' S construction period expectation layout to make the edge thereof smoother:
Figure BDA0002916804020000073
further, the target expected layout is replaced by the artificial expected layout.
Then, the mask pattern M is initialized to be a matrix of N × N, and its value range is constrained by a cosine function:
Figure BDA0002916804020000074
wherein (i, j) represents the ith row and the jth column element of the matrix,
Figure BDA0002916804020000075
constrained to the interval 0,1]In (1).
Then, an adaptive DUV projection imaging matrix I ═ Ψ (J, M (θ)) ═ Sig (I) is constructedwafer(θ)), calculating a cost function, calculating PE, EPE, calculating a derivative and updating a correlation variable; the derivatives are calculated and the relevant variables are updated until the number of updates reaches an upper limit.
FIG. 5 shows a comparison of the flooding optimization results of the new and conventional methods. Wherein (a) is a target expected layout, (b) is a human-time expected layout, and (c) is a wafer pattern, and the matching error F between (a) and (c) is continuously obtained by a convex optimization algorithm in the conventional MO method0Reducing, while MO method based on artificial expected layout by continuously reducing matching error F between (a) and (c)ARIs reduced to achieve a reduction of F0The purpose of (1).
FIGS. 6(a) -6 (b) show a comparison of the new process flow diagram and the conventional process flow diagram. The method comprises the following steps that (a) a traditional MO method and (b) an MO method based on an artificial expected layout, a target layout is subjected to preprocessing operation before optimization is carried out by the MO method based on the artificial expected layout, and then the artificial expected layout is used as input to carry out traditional optimization.
FIG. 7(a) -FIG. 7(c) show the unoptimized mask I01Projection imaging and EPE. (a) The pre-optimization mask pattern is also the pattern of the target desired layout, (b) is the image in the resist at the best focal plane at the nominal exposure dose with pattern error PE 6507, (c) is the edge where edge placement error EPE exists and EPE 1926. Where black represents a non-light emitting region, i.e., the light intensity is 0, and white represents a non-light emitting region, i.e., the light intensity is 1. In this embodiment the illumination system has a wavelength of 193nm, the annular illumination source has an angle of incidence of between 0.6 and 0.9, the system has a numerical aperture of 1.35, the size of each grid of the image is 4nm, and the steepness and threshold of the photoresist function are 85 and 0.25, respectively.
Fig. 8(a) -8 (b) show the results of MO using the conventional method. (a) The pattern error PE is 786 for a schematic image in the resist at the best focal plane at the nominal exposure dose. (b) Is the edge where the edge placement error EPE exists and EPE 172.
Fig. 9(a) -9 (b) show the results of MO based on an artificially desired layout. (a) The pattern error PE is 784 for a schematic image in the resist at the best focal plane at the nominal exposure dose. (b) Is the edge where the edge placement error EPE exists and EPE 142.
FIG. 10(a) -FIG. 10(c) show the unoptimized mask I02Projection imaging and EPE. (a) The pre-optimization mask pattern is also the pattern of the target desired layout, (b) is the image in the resist at the best focal plane at the nominal exposure dose with pattern error PE 3735, (c) is the edge where edge placement error EPE exists and EPE 1070.
Fig. 11(a) -11 (b) show the results of MO using the conventional method. (a) The pattern error PE of the pattern in the resist at the best focal plane at the nominal exposure dose is 464. (b) Is the edge where the edge placement error EPE exists and EPE 219.
Fig. 12(a) -12 (b) show the results of MO based on an artificially desired layout. (a) The pattern error PE 426 is shown for the image in the resist at the best focal plane at the nominal exposure dose. (b) Is the edge where the edge placement error EPE exists and EPE 20.
As described above, comparing fig. 7(a) to fig. 7(c), fig. 8(a) to fig. 8(b), fig. 9(a) to fig. 9(b), fig. 10(a) to fig. 10(c), fig. 11(a) to fig. 11(b), and fig. 12(a) to fig. 12(b), it can be seen that: compared with the traditional MO algorithm, the MO method has higher image fidelity under the condition that the target patterns are the same and the observation points are the same; under the condition that the algorithm operation time is close, the imaging performance of the optimized photoetching system is better.
The protective scope of the present invention is not limited to the above-described embodiments, and it is apparent that various modifications and variations can be made to the present invention by those skilled in the art without departing from the scope and spirit of the present invention. It is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims (6)

1. A target pattern mask optimization method based on artificial expectation is characterized by comprising the following steps:
step S1, converting the target pattern into a pixelized pattern, extracting high-frequency regions and high-frequency points of the pixelized pattern, and further constructing an expected target pattern based on artificial expectation;
step S2, taking the numerical value of the expected target pattern as the pixilated numerical value of the wafer circuit board image to construct a cost function and constraint conditions;
and step S3, updating the mask value of the expected target pattern according to the constraint condition.
2. The method of claim 1, wherein the target pattern mask optimization method based on artificial expectations is characterized by:
the step S1 includes:
step S11, performing pixelization processing on the mask graph of the target pattern to obtain a mask layout matrix before preprocessing, and obtaining a pattern edge through Gaussian convolution to obtain a high-frequency signal;
step S12, obtaining the corner of the pattern by solving partial differential of the pattern edge to obtain a high frequency point;
step S13, generating an auxiliary pattern according to the obtained high-frequency signal and the high-frequency point and based on a preset rule;
step S14, superimposing the generated auxiliary pattern on the target circuit board diagram to obtain the desired target pattern expected by human;
and step S15, performing smoothing processing on the expected target pattern expected in the construction period of the people.
3. The method of claim 1, wherein the target pattern mask optimization method based on artificial expectations is characterized by:
the step S2 includes:
according to the imaging performance of an actual projection lithography system and pattern errors and edge placement errors in the reverse compensation process, evaluating and calculating, and constructing a cost function and constraint conditions based on a pattern form student adult period expectation layout, namely:
Figure FDA0002916804010000011
s.t.M(θ)＝(1+cosθ)/2
wherein, IarIs an artificial expectation layout; Ψ {. denotes the mapping of DUV imaging for calculating wafer pattern Iwafer(ii) a A cost function of
Figure FDA0002916804010000012
And it is defined as a Pattern Error (PE); the constraint is M (θ) ═ 1+ cos θ)/2.
4. The method of claim 1, wherein the target pattern mask optimization method based on artificial expectations is characterized by:
the step S3 includes:
step S31, initializing the light source J and the mask M as numerical matrixes, and setting iteration times;
step S32, constructing a deep ultraviolet photoetching projection matrix;
step S33, constructing MO frame according to the expected target pattern expected by human;
step S34, carrying out derivation on the cost function to obtain a corresponding gradient;
and step S35, updating the mask value according to the steepest gradient descent method.
5. The method of claim 2, wherein the target pattern mask optimization method based on artificial expectations is characterized by:
in step S13, an additional auxiliary region is added at the high frequency signal of the circuit board diagram to reduce the high frequency signal of the target layout.
6. The method of claim 5, wherein the target pattern mask optimization method based on artificial expectations is characterized by:
the auxiliary area is a circular area with the numerical value gradually reduced from the center to two sides.
CN202110103267.3A 2021-01-26 2021-01-26 Target pattern mask optimization method based on artificial expectation Pending CN113189845A (en)

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