CN113178217B

CN113178217B - Main word line driver and semiconductor memory device thereof

Info

Publication number: CN113178217B
Application number: CN202110595170.9A
Authority: CN
Inventors: 孙会娟; 李智勋
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-05-28
Filing date: 2021-05-28
Publication date: 2022-05-20
Anticipated expiration: 2041-05-28
Also published as: CN113178217A

Abstract

A main word line driver includes an output module and a control module. The output module includes: a first PMOS output region; the second PMOS output area is arranged adjacent to the first PMOS output area along the first direction and is not contacted with the first PMOS output area; the first NMOS output area is arranged adjacent to the second PMOS output area along the first direction and is not contacted with the second PMOS output area; the second NMOS output area is arranged adjacent to the first NMOS output area along the first direction and is not contacted with the first NMOS output area; the first PMOS output area, the second PMOS output area, the first NMOS output area and the second NMOS output area are mutually parallel along a second direction; the control module is arranged at the bottom of the first PMOS output area, the second PMOS output area, the first NMOS output area and the second NMOS output area along the second direction. The performance of the main word line driver and the semiconductor memory thereof can be improved.

Description

Main word line driver and semiconductor memory device thereof

Technical Field

The present invention relates to semiconductor memory technology, and more particularly, to a main word line driver and a semiconductor memory device using the same.

Background

Metal-insulator-semiconductor (MOS) transistors are a common device and are widely used in semiconductor memory devices. For example, a Main word line driver (MWD) provided in a semiconductor memory device includes MOS transistors.

Specifically, the main word line driver comprises a control module and an output module (including a MOS tube), wherein the control module comprises a controller for analyzing a signal input to the main word line driver, and further comprises an inverter and a keeper. The controller analyzes the signal input to the main word line driver and then generates a driving signal to the module where the inverter and the keeper are located. The module where the inverter and the retainer are located processes the driving signal to generate another driving signal to the output module, and the output module processes the driving signal to output a main word line selection signal to the main word line. That is, the master word line is directly connected to the output block.

In the design of the semiconductor memory device, the position arrangement of the control module and the output module, or the space utilization rate of the main word line driver directly affects the performance of the main word line driver, and further affects the performance of the semiconductor memory manufactured based on the main word line driver. Therefore, how to reasonably design the arrangement of the control module and the output region in the main word line driver so as to improve the performance of the main word line driver and the semiconductor memory thereof has become a focus of research.

Disclosure of Invention

The application provides a main word line driver and a semiconductor memory device thereof, which are used for reasonably designing and arranging a control module and an output area in the main word line driver so as to improve the performance of the main word line driver and the semiconductor memory thereof.

In one aspect, the present application provides a master wordline driver comprising an output module and a control module, wherein:

the output module includes:

a first PMOS output region;

the second PMOS output area is arranged adjacent to the first PMOS output area along the first direction and is not contacted with the first PMOS output area;

the first NMOS output area is arranged adjacent to and not in contact with the second PMOS output area along the first direction;

a second NMOS output region disposed adjacent to and not in contact with the first NMOS output region along the first direction;

the first PMOS output region, the second PMOS output region, the first NMOS output region and the second NMOS output region are parallel to each other along a second direction, and the first direction is perpendicular to the second direction;

the control module is arranged at the bottom of the first PMOS output area, the second PMOS output area, the first NMOS output area and the second NMOS output area along the second direction and is respectively connected with the first PMOS output area, the second PMOS output area, the first NMOS output area and the second NMOS output area.

In one embodiment, the first PMOS output region comprises a first N-type substrate and a first P-channel, the second PMOS output region comprises a second N-type substrate and a second P-channel, the first NMOS output region comprises a first P-type substrate and a first N-channel, and the second NMOS output region comprises a second P-type substrate and a second N-channel;

the areas of the first N-type substrate and the second N-type substrate are equal, and the areas of the first P-type substrate and the second P-type substrate are equal;

the first P channel and the second P channel are equal in number, and the first N channel and the second N channel are equal in number.

In one embodiment, the first N-type substrate, the second N-type substrate, the first P-type substrate, and the second P-type substrate are equal in height along the second direction.

In one embodiment, the first PMOS output region, the second PMOS output region, the first NMOS output region, and the second NMOS output region include an equal number of gates therein.

In one embodiment, the sum of the lengths of the first PMOS output region, the second PMOS output region, the first NMOS output region, and the second NMOS output region along the first direction is less than or equal to the length of the control module along the first direction.

In one embodiment, the control module comprises:

the controller is used for receiving an input signal and generating a driving signal according to the input signal;

the inverter is connected with the controller and is used for carrying out inversion processing on the driving signal;

a holder connected with the controller.

In one embodiment, the output end of one of the inverters is connected with one of the output modules.

In another aspect, the present application also provides a semiconductor memory device, including the main word line driver according to the first aspect, further including:

a main word line extending from the output module consisting of the first PMOS output region, the second PMOS output region, the first NMOS output region, and the second NMOS output region;

a sub word line driver connected to the main word line driver through the main word line;

a sub word line extending from the sub word line driver;

and the memory cell array is connected with the sub word line driver through the sub word line.

In one embodiment, the method further comprises the following steps:

and the decoder is connected with the main word line driver.

In one embodiment, the decoder includes:

a main word line decoder configured to decode predetermined upper bits of a received target memory cell row address to generate a main word line selection signal, the main word line selection signal being received by the main word line driver to cause the main word line driver to select the main word line according to the main word line selection signal;

a sub word line decoder configured to decode a predetermined lower bit of the target memory cell row address to generate a sub word line selection signal, the sub word line selection signal being received by the sub word line driver to cause the sub word line driver to select the sub word line according to the sub word line selection signal.

In one embodiment, the predetermined lower bits of the target memory cell row address are lower than the predetermined upper bits of the target memory cell row address.

In one embodiment, the method further comprises the following steps:

a row address interpreter configured to interpret a target memory cell address encoding to generate the target memory cell row address.

In one embodiment, a keeper transistor is further disposed between two adjacent sub-word lines extending from one of the sub-word line drivers.

In one embodiment, a sub-word line inverter is further disposed in the sub-word line driver, and an output signal line of the sub-word line inverter is the sub-word line.

In one embodiment, the sub word lines extending from different sub word line drivers are alternately arranged.

Compared with a traditional main word line driver, the main word line driver provided by the application divides a PMOS output area and an NMOS output area into two output areas respectively, arranges the obtained four output areas in parallel along one direction in sequence, and places a control module at the bottoms of the four output areas. Therefore, the space occupied by the PMOS output area and the NMOS output area is compressed, and meanwhile, the space between the control module and the output module is compressed, so that more space can be reserved in the main word line driver for arranging other wiring. Therefore, the main word line driver greatly optimizes the internal use space of the main word line driver under the condition that the area of the semiconductor memory is not changed, so that the use performance of the main word line driver and the semiconductor memory thereof is improved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

Fig. 1 is a schematic structural diagram of a main word line driver in the prior art provided in this application.

Fig. 2 is a schematic structural diagram of a main word line driver according to an embodiment of the present application.

FIG. 3 is a comparison graph of performance tests of the main word line driver according to an embodiment of the present application.

Fig. 4 is a schematic structural diagram of a semiconductor memory device according to a second embodiment of the present application.

Fig. 5 is another schematic structural diagram of a semiconductor memory device according to a second embodiment of the present application.

Fig. 6 is a schematic partial structure diagram of a semiconductor memory device according to a second embodiment of the present application.

Fig. 7 is a schematic partial structural diagram of a semiconductor memory device according to a second embodiment of the present application.

Fig. 8 is a schematic view of a part of a conventional semiconductor memory device according to the present application.

Fig. 9 is a schematic view of a part of a conventional semiconductor memory device according to the present application. The reference numbers illustrate:

main word line driver 10

Output module 100

First PMOS output region 110

First N-type substrate 111

First P channel 112

First PMOS gate 113

Second PMOS output region 120

Second N-type substrate 121

Second P-channel 122

Second PMOS Gate 123

First NMOS output region 130

A first P-type substrate 131

First N-channel 132

First NMOS gate 133

Second NMOS output region 140

Second P-type substrate 141

Second N-channel 142

Second NMOS gate 143

Control module 200

Controller 210

Inverter 220

Retainer 230

Semiconductor memory device 20

Main word line 21

Sub word line driver 22

Sub word line 23

Memory cell array 24

Sub word line inverter 25

Decoder 26

Main word line decoder 27

Sub word line decoder 28

Row address interpreter 29

Keeper transistor 30

With the foregoing drawings in mind, certain embodiments of the disclosure have been shown and described in more detail below. The drawings and written description are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate the disclosed concepts to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

Metal-insulator-semiconductor (MOS) transistors are a common component and are widely used in semiconductor memory devices. For example, a Main word line driver (MWD) provided in a semiconductor memory device includes MOS transistors.

Specifically, referring to fig. 1, the master wordline driver includes a control module and an output module, wherein the control module includes a controller, an inverter and a keeper, and the output module includes a PMOS output region and an NMOS output region. Wherein, PMOS refers to N-type substrate, P-channel, metal-oxide-semiconductor that carries current by the flow of holes, and NMOS refers to P-type substrate, N-channel, metal-oxide-semiconductor that carries current by the flow of electrons.

Specifically, the controller is configured to analyze a signal input to the main word line driver, and the inverter is configured to perform secondary processing on a signal output by the controller. That is, the controller analyzes a signal input to the main word line driver and generates a driving signal to a module in which the inverter and the keeper are located. The module where the inverter and the retainer are located processes the driving signal to generate another driving signal to the output module, and the output module processes the driving signal to output a main word line selection signal to the main word line. That is, the master word line is directly connected to the output block.

In the design of a semiconductor memory device, the arrangement of the controller, the inverter, the keeper, the PMOS output region and the NMOS output region directly affects the space utilization of the master word line driver, and thus affects the performance of the master word line driver and the performance of a semiconductor memory fabricated based on the master word line driver. In other words, the larger the space utilization of the main word line driver, the better the performance of the main word line driver and the semiconductor memory.

Based on this, the present application provides a main word line driver and a semiconductor memory device thereof, which change the position arrangement of a PMOS output region, an NMOS output region and a control module in a conventional main word line driver, so that the arrangement of the output module and the control module in the main word line driver is tighter. In addition, the change of the position arrangement can also reduce the occupied volume of a connecting line between the output module and the control module, and further improve the space utilization rate of the main word line driver.

Referring to fig. 2, the present application provides a main word line driver 10, which includes an output block 100 and a control block 200.

The output module 100 further includes a first PMOS output region 110, a second PMOS output region 120, a first NMOS output region 130, and a second NMOS output region 140.

The second PMOS output region 120 is disposed adjacent to and not in contact with the first PMOS output region 110 along the first direction, the first NMOS output region 130 is disposed adjacent to and not in contact with the second PMOS output region 120 along the first direction, and the second NMOS output region 140 is disposed adjacent to and not in contact with the first NMOS output region 130 along the first direction. Furthermore, the first PMOS output region 110, the second PMOS output region 120, the first NMOS output region 130 and the second NMOS output region 140 are parallel to each other along a second direction.

The first direction and the second direction may be perpendicular or not, and may be specifically selected according to actual needs, which is not limited in the present application. Preferably, the first direction is perpendicular to the second direction, which is beneficial to the closer arrangement among the first PMOS output region 110, the second PMOS output region 120, the first NMOS output region 130 and the second NMOS output region 140, and reduces the unused area in the main word line driver module.

As described above, the PMOS refers to an N-type substrate, a P-channel, and a metal-oxide-semiconductor that carries current by the flow of holes, and the NMOS refers to a P-type substrate, an N-channel, and a metal-oxide-semiconductor that carries current by the flow of electrons. Then, the first PMOS output region 110 includes a first N-type substrate 111 and a first P-channel 112, and the second PMOS output region 120 includes a second N-type substrate 121 and a second P-channel 122. The first NMOS output region 130 includes a first P-type substrate 131 and a first N-channel 132, and the second NMOS output region 140 includes a second P-type substrate 141 and a second N-channel 142. The first PMOS output region 110 includes a first PMOS gate 113, the second PMOS output region 120 includes a second PMOS gate 123, the first NMOS output region 130 includes a first NMOS gate 133, and the second NMOS output region 140 includes a second NMOS gate 143.

As shown in fig. 2, the first P-channel 112 is disposed on both sides of the first PMOS gate 113, and the second P-channel 122 is disposed on both sides of the second PMOS gate 123. The first N channel 132 is disposed on both sides of the first NMOS gate 133, and the second N channel 142 is disposed on both sides of the second NMOS gate 143. Preferably, the number of the first P-channels 112 and the number of the second P-channels 122 are equal, and the number of the first N-channels 132 and the number of the second N-channels 142 are equal.

Preferably, the first N-type substrate 111 and the second N-type substrate 121 have the same area, and the first P-type substrate 131 and the second P-type substrate 141 have the same area. For example, the first N-type substrate 111 and the second N-type substrate 121 have the same length and width, and the first P-type substrate 131 and the second P-type substrate 141 have the same length and width. Wherein long may be understood as the length in the first direction, wide may be understood as the length in the second direction, and wide may also be understood as the height in the second direction.

Optionally, the first N-type substrate 111, the second N-type substrate 121, the first P-type substrate 131, and the second P-type substrate 141 have the same height along the second direction. At this time, the first N-type substrate 111 and the second N-type substrate 121 have the same length in the first direction, and the first P-type substrate 131 and the second P-type substrate 141 have the same length in the first direction. The lengths of the first and second N-

type substrates

111 and 121 in the first direction may be less than, or greater than, or equal to the lengths of the first and second P-

type substrates

131 and 141 in the first direction.

Alternatively, the areas of the first N-type substrate 111, the second N-type substrate 121, the first P-type substrate 131, and the second P-type substrate 141 may be equal, and the heights of the first N-type substrate 111, the second N-type substrate 121, the first P-type substrate 131, and the second P-type substrate 141 along the second direction are equal. Then, the lengths of the first N-type substrate 111, the second N-type substrate 121, the first P-type substrate 131, and the second P-type substrate 141 in the first direction are equal.

Optionally, the first PMOS output region 110, the second PMOS output region 120, the first NMOS output region 130 and the second NMOS output region 140 include an equal number of gates. That is, the number of the first PMOS gates 113, the second PMOS gates 123, the first NMOS gates 133 and the second NMOS gates 143 is equal.

The control module 200 is disposed at the bottom of the first PMOS output region 110, the second PMOS output region 120, the first NMOS output region 130, and the second NMOS output region 140 along the second direction, and is connected to the first PMOS output region 110, the second PMOS output region 120, the first NMOS output region 130, and the second NMOS output region 140 respectively. Thus, the layout position of the control module 200 can reduce the length and the occupied area of the circuit logic lines, the connecting lines or other wiring between the control module 200 and the output module 100.

Optionally, the sum of the lengths of the first PMOS output region 110, the second PMOS output region 120, the first NMOS output region 130, and the second NMOS output region 140 along the first direction is less than or equal to the length of the control module 200 along the first direction. That is, the length of the output module 100 along the first direction is less than or equal to the length of the control module 200 along the first direction. In this way, the circuit logic lines, connecting lines or other wiring between the control block 200 and the output block 100 can be completely routed between the control block 200 and the output block 100, so that the wiring in the main word line driver 10 is more standardized and localized. That is, the positional relationship between the control module 200 and the output module 100 makes the layout normalized and regionalized, which is more beneficial to the layout of other circuit modules in the main word line driver 10, and increases the space utilization of the main word line driver 10.

Optionally, the control module 200 may include a controller 210, an inverter 220, and a keeper 230.

The controller 210 is configured to receive an input signal and generate a driving signal according to the input signal. The controller 210 may be directly connected to a decoder in the semiconductor memory, which supplies the generated main word line selection signal to the controller 210, for example, a main word line selection signal for driving the main word line 21.

The inverter 220 is connected to the controller 210 for inverting the driving signal.

The keeper 230 is also connected to the controller 210, and the keeper 230 is equivalent to an analog signal memory for storing the signal output from the controller 210.

The specification, model, etc. of the inverter 220 and the keeper 230 can be selected according to actual needs, and the present application is not limited thereto.

Optionally, the output of one of the inverters 220 is connected to one of the output modules 100. Based on the above-described positional layout relationship between the control module 200 and the output module 100, if the control module 200 includes a plurality of inverters 220, the plurality of inverters 220 may be respectively disposed at the bottom of one output module 100 along the second direction. The distance between adjacent inverters 220 of the plurality of inverters 220 may be selected according to the area size, position, etc. of the output module 100. For example, for uniform wiring, each of the inverters 220 may be disposed on a central axis of the corresponding output module 100 extending along the second direction.

In summary, the main word line driver 10 provided in this embodiment replaces a PMOS output region and an NMOS output region originally provided in the output module 100 with the first PMOS output region 110, the second PMOS output region 120, the first NMOS output region 130 and the second NMOS output region 140. The first PMOS output region 110, the second PMOS output region 120, the first NMOS output region 130, and the second NMOS output region 140 are disposed in parallel at intervals along a first direction, the control module 200 is disposed at the bottom of the output module 100 along a second direction, and the first direction and the second direction may be perpendicular. Therefore, compared with the existing main word line driver, the main word line driver 10 provided by the present embodiment has a more normalized and regionalized layout, so that the space utilization of the main word line driver 10 is increased, and more circuit modules can be placed in the main word line driver 10 to enhance the performance of the main word line driver 10.

Referring to fig. 3, fig. 3 is a graph comparing the performance of a conventional main word line driver and a main word line driver provided in the present application. In fig. 3, the horizontal axis T represents time and the vertical axis V represents voltage, where V0 represents the voltage value that the master wordline driver is intended to have. As can be seen from FIG. 3, the main wordline driver provided by the present application has a shorter time (T0) when it is desired to reach the V0 voltage, while the existing main wordline driver requires more time (T1). Namely, the main word line driver provided by the application has stronger feedback capability and better performance.

Referring to fig. 4, a second embodiment of the present application provides a semiconductor memory device 20, where the semiconductor memory device 20 includes the Main word line driver 10 as described in the first embodiment, and further includes a Main Word Line (MWL) 21, a Sub word line driver (SWD) 22, a Sub Word Line (SWL) 23, and a memory cell array 24.

The main word line 21 extends from the output module 100 composed of the first PMOS output region 110, the second PMOS output region 120, the first NMOS output region 130, and the second NMOS output region 140, and extends to the sub word line driver 22. The sub word line driver 22 is connected to the main word line driver 10 through the main word line 21. During actual reading and writing of the semiconductor memory device 20, the main word line driver 10 receives a main word line selection signal and selectively drives the plurality of main word lines 21 according to the main word line selection signal, and the sub word line driver 22 receives a sub word line selection signal and selectively drives the plurality of sub word lines 23 according to the sub word line selection signal. Optionally, a sub-word line inverter 25 is further disposed in the sub-word line driver 22, and an output signal line of the sub-word line inverter 25 is the sub-word line 23.

The sub-word lines 23 extend from the sub-word line driver 22 to the memory cell array 24, that is, the memory cell array 24 is connected to the sub-word line driver 22 through the sub-word lines 23. After the sub-word line 23 is driven, the connected target read-write memory cell can also be driven, and the target read-write memory cell can be in a read or write state in combination with a signal input by a bit line of the target read-write memory cell. The state in which the target read-write memory cell is reading or writing depends on the signals input from the word lines and bit lines of the target read-write memory cell.

Optionally, the semiconductor memory device 20 may further include a decoder 26, and the decoder 26 is connected to the main word line driver 10. Specifically, the decoder 26 is configured to decode the received target memory row address to generate a main wordline select signal and a sub wordline select signal.

Optionally, the decoder 26 includes a main word line decoder 27 and a sub word line decoder 28.

The main word line decoder 27 is configured to decode predetermined upper bits of a target memory cell row address to generate a main word line selection signal. The main word line select signal is received by the main word line driver 10, so that the main word line driver 10 selects the main word line 21 according to the main word line select signal. Specifically, as described above, the main word line selection signal is received by the controller 210 in the main word line driver 10, the controller 210 processes the main word line selection signal and outputs the processed signal to the inverter 220, and the inverter 220 outputs the processed signal to the output region.

The sub word line decoder 28 is configured to decode predetermined lower bits of the target memory cell row address to generate a sub word line selection signal. The sub word line select signal is received by the sub word line driver 22 so that the sub word line driver 22 selects the sub word line 23 according to the sub word line select signal.

Optionally, the predetermined lower bits of the target memory cell row address are lower than the predetermined upper bits of the target memory cell row address.

Optionally, the semiconductor memory device 20 may further include a row address interpreter 29, and the row address interpreter 29 is configured to interpret a target memory cell address code to generate the target memory cell row address.

Alternatively, referring to fig. 5, fig. 6, fig. 7, fig. 8 and fig. 9, in the present embodiment, a group of the main word line drivers 10 can be commonly used by at least two different memory cell arrays 24. Fig. 8 and 9 are schematic layout views of the decoder 26 and the main word line driver 10 in the conventional semiconductor memory. In the conventional semiconductor memory, one decoder is connected to at least one group of main word line drivers 10, and each group of main word line drivers 10 is used by one memory cell array 24. That is, each memory cell array 24 uses a plurality of sets of sub word line drivers 22, and the plurality of sets of word line driver modules uses a set of main word line drivers 10. As shown in fig. 5 to 7, unlike the conventional semiconductor memory, a group of the main word line drivers 10 provided in this embodiment is commonly used by at least two different memory cell arrays 24, or a group of the main word line drivers 10 is commonly used by at least two groups of the sub word line drivers 22. Wherein a group of the main word line drivers 10 includes at least one main word line driver 10.

Thus, compared to the conventional semiconductor memory, the number of main word line drivers 10 in the semiconductor memory device 20 provided in the present embodiment is reduced by at least half, and the number of circuits for controlling the main word line drivers 10 in the decoder 26 is also reduced. This results in a large reduction in the area of the decoder 26, thereby making the entire semiconductor memory device 20 smaller in area.

Optionally, referring to fig. 4 or fig. 5, a keeper transistor 30 is further disposed between two adjacent sub-word lines 23 extending from one sub-word line driver 22. The prior art keeper transistor is designed such that one keeper transistor is connected with one sub-word line 23. In the present embodiment, the keeper transistor 30 may be designed such that two sub-word lines 23 share one keeper transistor 30 with each other. In this manner, the area of the keeper transistor 30 can be reduced to one-half of the area of the prior art keeper transistor, which reduces the area of the semiconductor memory device 20.

Alternatively, the sub word lines 23 extending from different sub word line drivers 22 are alternately arranged, so that the occupied area of the sub word lines 23 can be reduced, thereby reducing the area of the semiconductor memory device 20.

The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application, or which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A master wordline driver comprising an output module and a control module, wherein:

the output module includes:

a first PMOS output region;

2. The master word line driver of claim 1, wherein the first PMOS output region comprises a first N-type substrate and a first P-channel, the second PMOS output region comprises a second N-type substrate and a second P-channel, the first NMOS output region comprises a first P-type substrate and a first N-channel, the second NMOS output region comprises a second P-type substrate and a second N-channel;

3. The master word line driver of claim 2, wherein the first N-type substrate, the second N-type substrate, the first P-type substrate, and the second P-type substrate are equal in height along the second direction.

4. The master word line driver of claim 1, wherein an equal number of gates are included in the first PMOS output region, the second PMOS output region, the first NMOS output region, and the second NMOS output region.

5. The master word line driver of claim 1, wherein a sum of lengths of the first PMOS output region, the second PMOS output region, the first NMOS output region, and the second NMOS output region along the first direction is less than or equal to a length of the control module along the first direction.

6. The master word line driver of claim 2, wherein the control module comprises:

a holder connected with the controller.

7. The master wordline driver of claim 6, wherein an output of one of the inverters is connected to one of the output modules.

8. A semiconductor memory device comprising the main word line driver as claimed in any one of claims 1 to 7, further comprising:

a sub word line extending from the sub word line driver;

9. The semiconductor storage device according to claim 8, further comprising:

and the decoder is connected with the main word line driver.

10. The semiconductor memory device according to claim 9, wherein the decoder includes:

11. The semiconductor memory device according to claim 10, wherein predetermined low bits in the target memory cell row address are lower than predetermined high bits in the target memory cell row address.

12. The semiconductor memory device according to claim 10, further comprising:

a row address interpreter configured to interpret a target memory cell address code to generate the target memory cell row address.

13. The semiconductor memory device according to claim 8, wherein a keeper transistor is further provided between two adjacent sub word lines extending from one of the sub word line drivers.

14. The semiconductor memory device according to claim 8, wherein a sub word line inverter is further provided in the sub word line driver, and an output signal line of the sub word line inverter is the sub word line.

15. The semiconductor memory device according to claim 8, wherein the sub word lines extending from different ones of the sub word line drivers are alternately arranged.