CN113169153B - Packaging structure of chip - Google Patents
Packaging structure of chip Download PDFInfo
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- CN113169153B CN113169153B CN201880099876.2A CN201880099876A CN113169153B CN 113169153 B CN113169153 B CN 113169153B CN 201880099876 A CN201880099876 A CN 201880099876A CN 113169153 B CN113169153 B CN 113169153B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
A package structure includes a wiring board (22), and two chips (10, 20) attached to both upper and lower surfaces of the wiring board (22). Since the upper and lower chips (10, 20) are directly attached to the wiring board (22), the thickness of the chip is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a packaging structure of a chip.
Background
Chips, already a stock device in electronic equipment. By integrating the functional circuits required in the operation of the electronic equipment into a small chip, on one hand, the functional devices of the electronic equipment can be modularized, so that the design and manufacturing cost of the electronic equipment is reduced; on the other hand, by integrating a large amount of circuits in a chip, the volume of the electronic equipment can be reduced, and the electronic equipment has great significance to the electronic equipment (such as a mobile phone) in the consumer field.
Smartphones are currently the most popular consumer electronic devices. As a consumer-oriented media terminal device, whether to carry and operate is an important index for measuring the quality of a smart phone. In order to easily put the smart phone into the trousers pocket or allow the consumer to operate with one hand, the planar area of the smart phone cannot be too large, and the planar area of the smart phone can be reduced by reducing the planar area occupied by the chip.
In order to reduce the planar area occupied by the chip, there is a packaging technology called POP (Package on Package ) in the chip area. POP packages are commonly used for packaging smart phone chips. It is often necessary to equip smartphones with various types of chips, such as processor chips, memory chips, etc. POP packages are proposed to stack packages of multiple types of chips together up and down to form a new chip entity. For example, the package structure shown in fig. 1 includes a memory chip package and a processor chip package. The memory chip package is disposed over the processor chip package. The memory chip 2 is fixed on the substrate 6. The processor Chip 1, also called a System On Chip (SOC) for short, is fixed on a substrate 7. The substrates 6 and 7 are provided therein with metal wirings, and the memory chip 2 and the processor chip 1 are communicatively connected to the respective substrates through jumpers (Wired Bonding) or pads (Pad) provided at the bottom thereof. A re-wiring layer 3 is also provided between the processor chip 1 and the memory chip 2. The upper and lower surfaces of the redistribution layer 3 are respectively provided with a pad (not shown), and the inside of the redistribution layer 3 is provided with a metal wiring. The substrate 6 is connected to the rewiring layer 3 via solder balls 8, and the rewiring layer 3 is connected to the substrate 7 via solder balls 4. In the POP package structure shown in fig. 1, when the processor chip 1 is to read data from the memory chip 2, the read data is transferred into the processor chip 1 sequentially through the substrate 6, the solder balls 8, the rewiring layer 3, the solder balls 4, and the substrate 7.
POP packages are not only used for this combination of processor chips and memory chips, but various chips in electronic devices can be stacked and packaged into a chip entity in this manner of POP packages. The use of POP packages is equivalent to the use of space in the thickness direction to reduce the occupation of chip space on the electronic device. In the field of smartphones, one of the most intuitive results of using POP packaging is that the planar size of the smartphones becomes small, and even high-performance smartphones mounted with multi-functional chips become handy.
However, the POP package has a significant disadvantage in that it brings about an increase in thickness of the electronic device. In the field of smart phones, the increase in thickness can affect aesthetics, which is also very detrimental to sales. Therefore, how to further reduce the thickness of POP packages is also an important point in the industry.
Disclosure of Invention
In order to solve the problems in the prior art, the embodiment of the invention provides a packaging structure. In the packaging structure, at least two chips are packaged together in a stacked manner. The package structure includes a first chip and a second chip. The second chip is disposed on top of a second wiring board, and the corresponding first chip is fixed on the bottom of the second wiring board. In the package structure provided by the embodiment of the invention, the first chip is directly fixed at the bottom of the wiring board of the second chip, and the solder balls are additionally arranged between the first chip and the second chip, so that the space of the package structure in the thickness direction is saved.
In an alternative embodiment, the first chip may be fixed to the bottom of the second wiring board through a chip adhesive film.
In an alternative embodiment, the package structure further includes a first wiring board. The first chip is disposed on the first wiring board. Metal wiring is arranged in each of the first wiring board and the second wiring board, and interfaces which are communicated with the metal wiring inside each of the first wiring board and the second wiring board are arranged on the surfaces of the first wiring board and the second wiring board and are used for electrically connecting the metal wiring with the first chip or the second chip or other circuit devices.
The interface of the surfaces of the first wiring board and the second wiring board may have various forms, such as a pad, and may be a length of metal wiring exposed to the surfaces of the first wiring board and the second wiring board.
In alternative embodiments, the first chip may be electrically connected to the interface of the first wiring board surface in various manners. For example, the first chip may be electrically connected to a pad on the top surface of the first wiring board through a jumper (Wired Bonding); for another example, the first chip may be in direct contact with the metal wiring exposed to the top surface of the first wiring board through a pad at the bottom. Similar to the manner of electrically connecting the first chip and the first wiring board, the second chip may also be electrically connected to the metal wiring in the second wiring board by various methods.
In an alternative embodiment, an interconnection structure may be provided between the first wiring board and the second wiring board for communicating metal wirings within the first wiring board and the second wiring board. The interconnection structure may be a metal post provided between the first wiring board and the second wiring board; alternatively, metal-plated through holes penetrating the molding material between the first wiring board and the second wiring board may be used. Correspondingly, the top of the first wiring board and the bottom of the second wiring board are provided with interfaces corresponding to the interconnection structures. The interface may be a pad, or a metal wire exposed on the surface, which communicates with the interconnect structure by soldering or direct contact.
From the viewpoint of process cost, the processing cost of adopting the metal column as the interconnection structure is lower.
Since the first chip is attached to the bottom surface of the second wiring board, the interconnection structure is required to be disposed so as to avoid the first chip. Then, if the interconnection structure is realized by metal pillars, the metal pillars are arranged in a ring shape around the first chip. The stability of the packaging structure can be increased by the arrangement, so that the stress distribution of the packaging structure in the thickness direction is more uniform, and cracking is avoided. The ring shape is not limited to a circular ring, and may be a triangular ring, a rectangular ring, or the like, or may even be an irregular shape surrounding the first chip. In a preferred embodiment, the ring may be a regular pattern centered on the first chip.
In the package structure provided by the embodiment of the invention, the second chip and the first chip are in an up-down stacked structure. The second chip above the first chip needs to communicate signals with the first chip and also needs to communicate signals with the outside of the package structure. Accordingly, metal posts for communicating the first wiring board and the second wiring board can be classified into two types: a first metal pillar and a second metal pillar. Correspondingly, the metal wirings in the first wiring board are also classified into three types: a first metal wiring, a second metal wiring, and a third metal wiring. Wherein the second metal wiring is connected to the second metal post, the second metal wiring is further in communication with the one chip, and the second metal wiring and the second metal post constitute a part of a signal path between the first chip and the second chip; the third metal wiring is connected with the first metal column, the third metal wiring is also connected with a connecting pad at the bottom of the first wiring board, and the third metal wiring and the first metal column form a part of a signal path of the second chip communicated with the outside of the packaging structure; the first metal wiring is not connected to the metal post, and is used for connecting the first chip and the connection pad at the bottom of the first wiring board, so that the first metal wiring forms a part of a signal path of the first chip communicated with the outside of the package structure.
In an electronic device, the package structure provided by the embodiment of the invention is used as a chip entity obtained after package and is mounted on a carrier plate of the electronic device. The carrier board is typically a printed circuit board. When the packaging structure is installed in the electronic equipment, the connecting pad at the bottom of the first wiring board is fixedly connected with the circuit device on the carrier board through the solder balls.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a POP package in the prior art;
FIG. 2 is a schematic diagram of a package structure according to an embodiment of the present invention;
FIG. 3 is a schematic view of a package structure according to another embodiment of the present invention;
FIGS. 4a to 4g are process flow diagrams of the package structure according to the embodiment of the present invention;
fig. 5 is a schematic diagram of an electronic device loaded with a package structure according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
The embodiment of the invention provides a packaging structure. In the package structure, two or more chips are packaged together. And, these chips are packaged in a stacked manner, i.e., at least one chip is packaged over another chip.
In embodiments of the present invention, descriptions concerning "top" and "bottom" are referred to. It should be noted that the top and bottom are determined according to where the chip is located in the package structure.
In the embodiment of the invention, the chip refers to an entity obtained by packaging a Die (Die).
Referring to fig. 2, a package structure provided in an embodiment of the present invention includes a first chip 10 and a second chip 20. The first chip 10 is disposed on a first wiring board 12. The second chip 20 is disposed on a second wiring board 22. The second wiring board 22 is provided on top of the first chip 10. Thus, the first chip 10, the second chip 20, the first wiring board 12, and the second wiring board 22 constitute a structure stacked up and down.
The first wiring board 12 and the second wiring board 22 may have a multilayer structure mainly composed of an insulating medium. Conductive sheets made of metal are arranged on the surfaces of the first wiring board 12 and the second wiring board 22, or on one or more layers. The different layers of the first wiring board 12 and the second wiring board 22 are provided with perforations (Via) which pass through the different layers, even the surfaces, of the first wiring board 12 and the second wiring board 22. The perforations are filled or coated with metal. The metal in the perforations communicates with the conductive sheet on the layer. In the embodiment of the present invention, the metal in the through hole and the conductive sheet on the layer are collectively called metal wiring. The metal wiring constitutes a signal path in the first wiring board 12 and the second wiring board 22.
The metal posts, metal sheets, conductive sheets, and metal wirings involved in the embodiments of the present invention may be made of various metals such as metallic copper.
From the standpoint of process implementation, the first wiring board 12 and the second wiring board 22 may be substrates (substrates) or redistribution boards (ReDistribution Layer, RDL for short). The substrate and the rewiring board are both multilayer structures, but in comparison, the substrate contains glass fibers in which the line width and line spacing of the metal wiring are 10um or more (including horizontal distance and vertical distance); the re-wiring board is free of glass fiber, and the line width and the line distance of the metal wiring can be 5um. Therefore, if the thickness of the whole chip is saved, the first wiring board 12 and the second wiring board 22 can be selected at the same time.
However, from the viewpoint of industrial cost, the chip-stacked package structure is generally used in the field of mobile phone chips. In the mobile phone chip, the second chip 20 above is typically a memory chip, and for the manufacturer of the mobile phone chip, there is a situation that the memory chip is purchased from a third party, and the purchased memory chip is usually already packaged with the substrate into a Package entity, which is also referred to as a qualified device Package (KGP) in the industry. Since the KGP has a substrate for the memory chip and a pad is reserved at the bottom of the substrate to serve as a signal interface, if the package is removed at this time and the substrate is replaced with a rewiring board, a lot of additional costs are incurred. Thus, from a cost-saving standpoint, the second wiring board 22 may be a substrate, while the first wiring board 12 is a rewiring board. Of course, various process combinations may be employed for the first wiring board 12 and the second wiring board 22 in the future in response to various demands in the semiconductor process, for example, even the use of a semiconductor substrate (Interposer) may be considered, which should not constitute a limitation of the implementation of the present invention.
With continued reference to fig. 2, the first chip 10 and the second chip 20 are coupled to metal wiring in the first wiring board 12 and the second wiring board 22, respectively, by respective bottom pads (Pad) 14 and 24. Metal posts 25 are also disposed between the first wiring board 12 and the second wiring board 22. Both ends of the metal posts 25 are coupled to signal paths in the first wiring board 12 and the second wiring board 22, respectively.
The bottom of the first wiring board 12 is provided with a plurality of pads 125, and the pads 125 are used as external interfaces of the package structure provided by the embodiment of the invention. Specifically, in the package structure provided by the embodiment of the invention is installed in an electronic device, the connection pad 125 is fixedly connected to a PCB (Printed Circuit Board ) of the electronic device through a solder ball.
Alternatively, in the embodiment of the present invention, the metal wirings in the first wiring board 12 include a first metal wiring 122, a second metal wiring 124, and a third metal wiring 126. The metal posts 25 include a first metal post 252 and a second metal post 254. The first metal wiring 122 is connected to the pad 14 at the bottom of the first chip 10 and the pad 125 at the bottom of the first wiring board 125, so as to implement signal communication between the first chip 10 and a circuit outside the package structure provided by the embodiment of the invention. The second metal wiring 124 communicates the second metal pillar 254 with the bonding pad 14 at the bottom of the first chip 10, so as to implement signal communication between the first chip 10 and the second chip 10. The third metal wire 126 communicates the first metal post 252 with a pad at the bottom of the first wiring board 12, so as to realize signal communication between the second chip 20 and a circuit outside the package structure.
In an alternative embodiment, the metal pillars 25 are arranged in a ring around the first chip 10, with the first metal pillars 252 and the second metal pillars 254 being on different rings. In alternative embodiments, the metal posts 25 may be arranged in a circular ring, a rectangular ring, or even an irregularly patterned ring. In the embodiment of the present invention, the first chip 10 is to be attached to the bottom of the second wiring board 22, and therefore, the pads or pins on the bottom of the second wiring board 22 must be arranged to leave space for the first chip 10, so that the metal pillars 25 corresponding to the pads or pins on the bottom of the second wiring board 22 also need to be arranged around the first chip 10. Of course, since the arrangement space of the metal wirings in the first wiring board 12 needs to be considered, the second metal posts 254 communicating with the first chip 10 are required, and can be arranged closer to the first chip than the first metal posts 252 only communicating with the pads at the bottom of the first wiring board 12. For example, in an alternative embodiment, the first metal pillar 252 and the second metal pillar 254 are arranged in two rings of different sizes, and the ring formed by the first metal pillar 252 is arranged to surround the ring formed by the first chip 10 and the second metal pillar 254.
In the package structure in fig. 2, the first chip 10 and the second chip 20 are each coupled with a metal wiring in a wiring board through a pad provided at the bottom. In alternative embodiments, however, the chip may be coupled to metal wiring on the wiring board by wire jumpers (Wired Bonding) on the top or sides. As shown in fig. 3, a pad 24 is disposed on top of the second chip 20, and a jumper 23 is connected to the pad 24. The jumper wire 23 is connected to the first metal post 252 or the second metal post 254 through a metal wiring on the second wiring board 22.
Generally, the second chip 20 is connected to the metal wiring in the second wiring board 22 by jumper wires, which increases the space requirement above the second chip 20, that is, increases the chip thickness. But as described above, since the second chip 20 may be a purchased KGP. If the purchased KGP is connected by a jumper, if the connection method between the second chip and the second wiring board 22 is changed after the KGP is disassembled, this will bring additional process and design cost, so the connection method of the chip in the KGP may not be changed.
In the package structures of fig. 2 and 3 provided in the embodiments of the present invention, the first chip 10 is directly mounted on the bottom of the second wiring board 20, and no solder ball is further disposed between the first chip 10 and the second chip 20, or an additional wiring board is mounted, which has reduced the thickness of the entire package structure no matter how the chip connection is performed in KGP.
Alternatively, the first chip 10 may be fixed to the bottom of the second wiring board 20 by an adhesive. The adhesive here may be a Die Attach Film (DAF) commonly used to Attach dies in a chip.
In the package structure provided in fig. 2 and 3, communication is performed between the first wiring board 12 and the second wiring board 22 through the metal posts 25. In an actual product, there is a possibility that the space between the first wiring board 12 and the second wiring board 22 is filled with an insulating medium (such as silica or the like). In this regard, in an alternative embodiment, instead of using the metal posts 25, through holes (Via) that communicate the first wiring board 12 and the second wiring board 22 may be formed in the insulating medium, and the signal paths between the first wiring board 12 and the second wiring board 22 may be configured by plating or filling metal in the through holes. However, if a metal column is used, the process is simpler and the cost is low. In specific, reference is made to the method for generating the package structure according to the embodiment of the present invention provided in fig. 4a to 4 h.
The packaging method provided by the embodiment of the invention comprises the following steps:
step a: referring to fig. 4a, KGP is fixed on the carrier 30 by an adhesive.
KGP is the purchased package entity containing the second chip 20 and the second wiring board 22. The second chip 20 and the second wiring board 22 are filled with a plastic sealing material around them. The KGP is turned over, the top of the KGP is in contact with the surface of the carrier, and the side of the second wiring board 22 is directed upward.
Step b: referring to fig. 4b, the first chip 10 is fixed on the second wiring board 22.
The top of the first chip 10 is adhered to the second wiring board 22 by an adhesive such as DAF. The bottom of the first chip 10, i.e. the side with the connection pad 14, faces upwards, or away from the second chip 20.
Step c: referring to fig. 4c, a metal pillar array is fabricated;
the metal pillar array includes a substrate 29, and a plurality of metal pillars protruding from one side of the substrate. The metal array can be formed by integrally forming the same metal, such as copper. The metal pillar array may be prepared by various methods, but if cost is considered, it is considered that the metal pillars are etched on a single metal plate by etching using existing equipment and processes in a packaging factory, for example, an etching process may be used. It will be readily appreciated that the array of metal posts may be prefabricated or purchased from a third party without being fabricated at the current time.
Step d: referring to fig. 4d, the metal pillar array is fastened on the KGP.
The metal array is snapped onto the KGP, the metal posts 25 center the first chip around, and the base 29 bridges over the first chip 10. So that the metal posts 25 are aligned with the metal wirings exposed to the surface of the second wiring board 22. Specifically, the surface of the second wiring board 22 may be made to also form a metal structure similar to a pad, and the metal posts 25 and the metal wirings are fixedly coupled by solder balls. In the embodiment of the present invention, the metal pillars 25 are shown in a form of being located at both sides of the first chip 10. In actual products, however, a plurality of metal posts 25 may be arranged in a ring shape to surround the first chip 10 at the center.
Step e: referring to fig. 4e, the plastic package is performed.
A molding compound 35 fills the gap between the array of metal pillars and the first chip 10.
Step f: referring to fig. 4f, the structure shown in fig. 4e is polished to expose pads on the bottom of the first chip 10.
In the embodiment of the present invention, the substrate 29 of the metal pillar array, the molding material between the substrate 29 and the first chip 10, and the metal pillars 25 above the bottom surface of the first chip 10 are polished until the pads 14 at the bottom of the first chip 10 are exposed.
Step g: referring to fig. 4g, the first wiring board 12 is prepared.
The second wiring board 12 generally includes metal wiring, and an insulating material (for example) surrounding the metal wiring. The insulating material may be formed layer by layer on the surface of the first chip 10 and the surface of the plastic sealing material surrounding the first chip 10 by coating or growing. And, perforating a plurality of layers of the insulating material, filling or plating metal in the perforations to form metal wiring connecting the different layers.
According to the above provided packaging method, it can be seen that each metal pillar 25 is integrally formed, and the front part thereof is a preformed metal pillar array, so that the metal pillars can be simply fixed in the packaging structure through the grinding process, and two chips are connected and supported. Compared with the signal line which is produced by the electrochemical method, the process cost is lower and the structure is firmer.
In the embodiment of the invention, the whole packaging structure is divided into two layers: the first layer includes the first chip and a first wiring board; the second layer includes the second chip and a second wiring board. In the above description, only the case where the first layer includes a first chip and the second layer includes a second chip is taken as an example. In an actual product, the first layer may further include a plurality of first chips, where the plurality of first chips may be disposed on the first wiring board in parallel, or may be stacked, where one or more first chips are stacked on another one or more first chips. The plurality of first chips may communicate directly with each other or through the first wiring board. Similarly, the second layer may include a plurality of second chips, and the plurality of second chips may be disposed on the second wiring board in parallel, or may be stacked. The plurality of second chips may be directly connected to each other or connected to each other through a second wiring board.
Fig. 5 is a schematic diagram of a package structure according to an embodiment of the present invention assembled on a carrier board in an electronic device. As shown, the pads 125 at the bottom of the first wiring board 12 are fixedly connected to a carrier board of the electronic device by solder balls, and perform data communication with other chips or devices on the carrier board by circuits on the carrier board. The carrier board is most commonly a printed circuit board (Printed Circuit Board).
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (12)
1. A package structure characterized by comprising a first chip, a second chip, a first wiring board, a second wiring board and a metal pillar, wherein the second chip is arranged on the second wiring board, the first chip is attached to the bottom of the second wiring board, the first wiring board is arranged below the second wiring board, the first chip is arranged on the first wiring board, metal wirings are arranged in the first wiring board and the second wiring board, two ends of the metal pillar are respectively connected to the second wiring board and the first wiring board, and two ends of the metal pillar are respectively communicated with the metal wirings in the first wiring board and the second wiring board;
the packaging structure is packaged by the following method:
fixing a packaging entity on a carrier plate, wherein the packaging entity comprises the second chip and the second wiring board, the top of the packaging entity is contacted with the surface of the carrier plate, and the side of the second wiring board is upward;
fixing the first chip on the second wiring board;
manufacturing a metal column array, wherein the metal column array comprises a substrate and a plurality of metal columns protruding out of one side of the substrate;
the array of metal posts is buckled on the packaging entity, the metal posts encircle the first chip at the center, the substrate is bridged over the first chip, and the metal posts are aligned with metal wires exposed on the surface of the second wiring board;
filling a gap between the metal column array and the first chip with a plastic packaging material;
grinding a substrate of the metal column array, a plastic packaging material between the substrate and the first chip, and the metal columns which are higher than the bottom surface of the first chip until the pads at the bottom of the first chip are exposed;
and preparing the first wiring board, wherein the first wiring board is positioned on the surface of the first chip and the surface of the plastic packaging material wrapping the first chip.
2. The package structure of claim 1, wherein,
the first chip communicates with the metal wiring in the first wiring board, and the second chip communicates with the metal wiring in the second wiring board.
3. The package structure of claim 2, wherein the bottom of the second wiring board is provided with a pad communicating with a metal wiring in the second wiring board, and the metal post is fixedly connected with the pad of the second wiring board.
4. The package structure of claim 3, wherein the metal posts are fixedly connected to pads of the second wiring board by solder.
5. The package structure according to any one of claims 2 to 4, wherein a portion of the metal wiring in the first wiring board is exposed to a surface of the first wiring board, and the metal post is in contact with the metal wiring exposed to the surface of the first wiring board.
6. The package structure of claim 2, wherein the metal posts are arranged in a ring around the first chip.
7. The package structure according to claim 2, wherein the first wiring board includes therein a first metal wiring, a second metal wiring and a third metal wiring, the bottom of the first wiring board is provided with a pad, the metal posts include a first metal post and a second metal post, the first metal wiring communicates with the first chip and the pad at the bottom of the first wiring board, the second metal wiring communicates with the second metal post and the first chip, and the third metal wiring communicates with the first metal post and the pad at the bottom of the first wiring board.
8. The package structure of claim 7, wherein the first metal pillars and the second metal pillars are each arranged in two rings of different sizes around the first die, and the rings in which the first metal pillars are arranged surround the rings in which the first metal pillars are arranged.
9. The package structure according to claim 2, wherein an interconnection structure is provided between the second wiring board and the first wiring board, the interconnection structure communicating the second wiring board and the first wiring board.
10. The package structure of claim 1, wherein the first chip is fixed to a bottom of the second wiring board by a chip adhesive film.
11. An electronic device comprising a carrier plate, and the package structure of any one of claims 1-10 carried on the carrier plate.
12. The electronic device of claim 11, wherein the package structure is secured to the carrier by solder balls, and the package structure communicates with circuitry or devices on the carrier through the solder balls.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2018/123686 WO2020132909A1 (en) | 2018-12-26 | 2018-12-26 | Chip packaging structure |
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| Publication Number | Publication Date |
|---|---|
| CN113169153A CN113169153A (en) | 2021-07-23 |
| CN113169153B true CN113169153B (en) | 2023-09-29 |
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| CN201880099876.2A Active CN113169153B (en) | 2018-12-26 | 2018-12-26 | Packaging structure of chip |
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| CN (1) | CN113169153B (en) |
| WO (1) | WO2020132909A1 (en) |
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| US11410902B2 (en) * | 2019-09-16 | 2022-08-09 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
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| CN106876363A (en) * | 2017-03-13 | 2017-06-20 | 江苏长电科技股份有限公司 | The fan-out package structure and its process of 3D connections |
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| WO2020132909A1 (en) | 2020-07-02 |
| CN113169153A (en) | 2021-07-23 |
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