CN113162713B - Variable symbol rate timing recovery method and system based on Gardner algorithm - Google Patents
Variable symbol rate timing recovery method and system based on Gardner algorithm Download PDFInfo
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Abstract
The invention provides a variable symbol rate timing recovery method based on a Gardner algorithm, which is characterized in that variable symbol rate timing recovery is realized based on a timing recovery system, an interpolation estimator is arranged in the timing recovery system, and down-conversion and filtering processing are carried out on an intermediate frequency signal received by a signal receiver to obtain baseband I and Q signals; interpolating the baseband I and Q signals by using a sampling judgment condition generated by an interpolation estimator; under the triggering of the peak value moment and the transition value moment generated by the interpolation estimator, a timing error is obtained by using a Gardner algorithm module; and performing loop filtering on the timing error, and updating a sampling judgment condition and peak value time and transition value time generated by the interpolation estimator by using the interpolation estimator. The invention improves on the basis of the traditional Gardner timing error detection, solves the problem that the symbol rate and the sampling rate of a receiving end are not matched in communication, and realizes the timing recovery of acquiring an accurate sampling clock for signals with any symbol rate under the condition of unchanging the sampling rate.
Description
Technical Field
The invention belongs to the technical field of signal demodulation, and particularly relates to a timing recovery scheme which is based on the improvement of a Gardner error detection algorithm and can acquire an accurate sampling clock under the condition of any symbol rate.
Background
Modern communication has been fully developed in the digital era, and digital communication systems, which are systems for transmitting information using digital signals, have been developed rapidly. The general model of the digital communication system is that a signal source sends information, a modulator moves a transmitted signal spectrum to a high frequency position through an encoder to form a band-pass signal suitable for transmission in a channel, the band-pass signal is transmitted out through the channel, a demodulator is needed at a receiving end to demodulate a modulated signal, and the modulated signal reaches a signal sink part needing to receive the information through a decoder.
Timing recovery is the process of deriving a periodic timing signal from a received digital signal based on the periodicity of the digital time slots, with the objective of generating a local clock that matches the symbol rate to obtain the optimum sampling point. Timing synchronization generally includes two methods, one is an external synchronization method, in which a transmitting end transmits special synchronization information (i.e., pilot frequency), and then a receiving end extracts the pilot frequency as a synchronization signal. The method has a narrow application range, needs to pay certain frequency band and signal power, and is not ideal in the aspects of economy, anti-interference performance and the like; the other method is a self-synchronizing method, which has the advantages that it does not need to estimate the relative delay between the transmitted and received signals, overcomes the disadvantages of the external synchronizing method, does not occupy extra transmission power and channel bandwidth, and adopts a digital signal processing mode to extract a clock signal from the received data signal. On the other hand, the self-synchronization method allocates all the transmission power and transmission frequency band to data transmission, which improves the system utilization rate, so the self-synchronization method is the first choice for communication system design in general. In an actual application scenario, the crystal oscillator frequencies used by the transmitting end and the receiving end cannot be guaranteed to be completely the same, and the doppler effect caused in the moving process of the mobile station may cause carrier frequency offset between the transmitting end and the receiving end.
The Gardner algorithm is a classical timing error detection algorithm that only requires sampling at twice the symbol rate, i.e. 2 samples per symbol to extract timing error information. The Gardner algorithm is easy to implement, is not affected by the carrier phase, and is widely used in symbol timing recovery. However, in digital communication, the symbol rate and the sampling rate cannot be in integral multiple relation each time, and in an actual working system, the sampling rate is not easy to change, but the symbol rate is changed frequently, and the traditional Gardner timing error detection algorithm is difficult to meet the requirement.
The present invention is based on the Gardner algorithm, utilizes the timing error generated by the Gardner algorithm to adjust the timing pulse and output the correct value, and takes QPSK as an example to illustrate the improved Gardner timing recovery algorithm for realizing variable symbol rate. However, the invention is not limited to QPSK demodulation, but can be used in the timing synchronization process of digital demodulation of other related ASK, PSK, BSK.
Disclosure of Invention
The invention aims to realize a variable symbol rate Gardner timing recovery improvement scheme on the basis of the traditional Gardner timing error detection.
In order to achieve the above object, the present invention provides a variable symbol rate timing recovery method based on Gardner algorithm, which is based on a timing recovery system to realize variable symbol rate timing recovery, wherein the timing recovery system comprises a signal receiver, a cubic interpolator, a Gardner timing error detection module and a loop filter, which are connected in sequence, an interpolation estimator is arranged in the timing recovery system, the execution comprises the following steps,
step 4, performing loop filtering on the timing error generated by the Gardner algorithm module, and filtering noise interference to obtain a more effective timing error;
and step 5, the interpolation estimator updates the sampling judgment condition and the peak time and the transition value time generated by the interpolation estimator according to the timing error output by the loop filter, updates the sampling judgment condition and the peak time and the transition value time generated by the interpolation estimator by using the interpolation estimator, and repeats the steps 2-5.
And the sampling decision condition generated by the interpolation estimator is timing error Decimal out, and baseband I and Q signals are respectively interpolated according to the timing error Decimal out output by the interpolation estimator as the interpolation time.
Furthermore, the interpolation estimator is a modulo-1 phase decrementer, assuming a symbol period interval of the input signal of TiThen the interpolated estimator is used to generate an average period of TiTo make a sampling decision on the input signal.
Moreover, assuming that the content of the phase register at the mth clock time of the interpolation estimator is η (m), the control word of the interpolation estimator is ω (m), and the difference formula of the decreasing phase is:
η(m+1)＝(η(m)-ω(m))mod(1)
ω (m) is adjusted by the error signal generated by the Gardner timing error detection module, as follows,
wherein the sampling interval is TsSymbol period interval of input signal is TiAnd e (m) is the value of the timing error after loop filtering, which is used to adjust ω (m) to update the sampling decision condition and the peak time sys _ clk and transition time tran _ clk generated by the interpolation estimator.
In step 5, the peak time is updated as follows,
the control word ω (m) of the interpolation estimator starts at the previous peak time and continues with ω (m) as the step length until the next peak is reached within one signal period;
when the timing error is a positive value, increasing omega (m) to enable eta (m + 1) < omega (m) to appear in advance, and adjusting the timing pulse backwards to slightly reduce the interval between pulses;
when the timing error is a negative value, the adjustment is carried out forward in the same way, and the interval between pulses is slightly increased;
when the timing error is 0, extreme value sampling is realized, the output of the loop filter is unchanged, and omega (m) is a real ratio obtained by timing recovery;
then comparing eta (m) with omega (m) and outputting the comparison result as the updated peak time; the output at peak time is a pulse written as:
wherein 1 is a high level, 0 is a low level, and the high level corresponds to a corresponding peak time;
in the updating process of the transition value time, the initial value of the transition value time of each symbol period is calculated from the previous peak value time, and sym _ clk is used as the decision basis of output, and the output is as follows:
tr(m+1)＝(tran(m)-ω(m))mod(1)
wherein, tran (m) represents the last decision of tran _ clk controlled by sym _ clk, and tr (m + 1) represents the value of tran (m) before update;
the output of the output timing error Decimal _ out is equal to:
furthermore, the interpolation estimator is implemented as follows,
the structure for judging the peak time comprises adder modules add1 and add2, a modulus operation module mod1 and a comparison judgment module match 1, and input error signals e (m) and
the control word ω (m) of the interpolation estimator is generated by adding at add1, m (m) and the content η (m) of the phase register at the previous mth clock instant are performed in add2Subtracting, and performing modulo 1 operation on the obtained difference value by using a modulo operation module mod1 to obtain the content eta (m + 1) of the updated (m + 1) th clock time phase register; then, the signal enters a delay unit delay1, the updated eta (m + 1) is kept, in the comparison and judgment module compare1, when the eta (m) is smaller than the omega (m), a peak pulse is output as a peak time sym _ clk, and the judgment for generating the peak time uses a delay unit delay2 to simulate the delay in the actual system at the output end of the comparison and judgment module compare 1;
the decision structure of the transition value time comprises adder modules add1 and add3, a modular operation module mod2, a comparison decision module compare2, a switch K1 and input error signals e (m) and
adding the control word ω (m) of the interpolation estimator at add1 to generate a subtraction operation between ω (m) and the content tran (m) of the previous mth clock time phase register at add3, and performing a modulo 1 operation on the obtained difference by using a modulo operation module mod1 to obtain the content tr (m + 1) of the updated mth +1 clock time phase register; then, the signal enters a delay unit delay3, the updated eta (m + 1) is maintained, and meanwhile, the signal entering the switch K1 is ensured to be the content tr (m) of the phase register at the mth clock moment; in the tap decision process of K1, the generation of tran (m) outputs a peak pulse (sym _ clk) with a peak time decision structure as a decision condition: when the peak pulse is output, the value of the previous signal tran (m) is represented by η (m) +0.5, and when the peak pulse is not output, the value of the previous signal tran (m) is represented by the value of tr (m), the obtained tran (m) is sent to a comparison decision module compare2, and in a transition value pulse output part of the comparison decision module compare2, when the tran (m) is smaller than ω (m), a transition value pulse is output as a transition value time tran _ clk for making a decision of the transition value time; the output end of the comparison judgment module compare2 uses a delay unit delay4 to simulate the delay in an actual system;
the decision structure of the timing error comprises D flip-flops D1 and D2, multiplier modules mul1 and mul2 and a switch K2, wherein the D flip-flop D1 stores the product of tran (m) and the reciprocal of omega (m) generated by the multiplier mul1, and transmits the product to the switch K2 when tran _ clk arrives; d flip-flop D2 stores the product generated by multiplying the reciprocal of eta (m) and omega (m) by multiplier mul2, and transmits the product to K2 when sym _ clk arrives; in the switch K2 generating the timing error module, the transition value timing decision structure outputs a peak pulse (tran _ clk) as a decision condition: when the transition value pulse is output, the output value of the timing pulse is the product of tran (m) and the reciprocal of ω (m), and when the transition value pulse is not output, the output value of the timing pulse is the product of η (m) and the reciprocal of ω (m).
In another aspect, the present invention further provides a variable symbol rate timing recovery device based on Gardner algorithm, for implementing the variable symbol rate timing recovery method based on Gardner algorithm as described above.
The invention improves on the basis of the traditional Gardner timing error detection, and solves the problem that the symbol rate and the sampling rate of a receiving end are not matched in communication. Under the condition of unchanging sampling rate, the timing recovery scheme of accurate sampling clock can be obtained for signals with any symbol rate.
The scheme of the invention is simple and convenient to implement, has strong practicability, solves the problems of low practicability and inconvenient practical application of the related technology, can improve the user experience, and has important market value.
Drawings
FIG. 1 is a system block diagram of an embodiment of the present invention;
FIG. 2 is a schematic diagram of the Gardner timing error detection according to an embodiment of the present invention, wherein FIG. 2a is
FIG. 2b is a timing error diagram of
FIG. 2c is a schematic diagram of timing error of
Timing error diagram of (a);
FIG. 3 is a schematic diagram showing the result of the Gardner timing error detection module outputting with time in the structure of the embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating the convergence of the timing error generated by the Gardner timing error detection module after loop filter processing according to an embodiment of the present invention;
fig. 5 is a schematic diagram of an interpolation estimator according to an embodiment of the present invention, in which fig. 5a is an overview diagram of the interpolation estimator, fig. 5b is a partial enlarged view of a decision structure at a peak time in fig. 5a, fig. 5c is a partial enlarged view of a decision structure at a peak transition time in fig. 5a, and fig. 5d is a partial enlarged view of a decision structure of a peak timing error in fig. 5 a.
FIG. 6 is a timing waveform diagram of an interpolation estimator according to an embodiment of the present invention.
Detailed Description
The technical solution of the present invention is specifically described below with reference to the accompanying drawings and examples.
Fig. 1 is a system structure diagram of an embodiment of the present invention, and the existing timing recovery system includes a signal receiver, a cubic interpolator, a Gardner timing error detection module, and a loop filter, which are connected in sequence.
The improved method for realizing the Gardner timing recovery algorithm with the variable symbol rate provided by the embodiment of the invention comprises the following steps:
an AD module, a down-conversion module and a low-pass filter are usually arranged in the signal receiver.
The specific process of the step 1 in the embodiment is as follows: taking a QPSK receiver as an example, an intermediate frequency signal received by the signal receiver is processed by an AD module through down conversion to obtain two signals, I and Q, and then is processed by a low pass filter to obtain I and Q baseband signals required for demodulation. In specific implementation, the method of the present invention can also be used in a BPSK receiver, and the implementation process is the same.
the specific process of the step 2 is as follows: and (2) a sampling judgment condition (timing error Decimal out output by the interpolation estimator) generated by the interpolation estimator and the I and Q baseband signals obtained in the step (1) after down-conversion and filtering processing enter the cubic interpolator together, and the I and Q paths are interpolated respectively according to the timing error Decimal out output by the interpolation estimator as the interpolation time.
Specifically, in the initial state, since no sampling decision condition is generated, the output result of the cubic interpolator is the baseband I, Q signal at the input end. And then, according to the sampling judgment condition generated by the interpolation estimator, the interpolation is carried out and the output is obtained.
Cubic interpolation, simply fitting a curve using a cubic polynomial. Converting the samples into a weighted analog pulse sequence, applying it to a time-continuous, analog, pulse-response hI(t) in the interpolation filter. Assume a sampling period of TsThe input symbol period is TiObtaining:
y(kTi)＝∑mx(mTs)hI(kTi-mTs)(1)
wherein, y (kT)i) Is the interpolated output, x (mT)s) Is the sampling of the baseband signal by the local sampling clock, hI(kTi-mTs) Is the impulse response of the interpolation filter and m is the time instant. T is a unit ofsIs the period of the local sampling clock. The above expression is the expression of cubic interpolation, and after passing through the cubic interpolator, new I, Q baseband signals after interpolation can be obtained.
the peak time sys _ clk and the transition time tran _ clk are used as trigger conditions of the D flip-flop, that is, only when the peak time sys _ clk and the transition time tran _ clk are pulsed, the data in the Gardner timing error detection module is updated. Specifically, in the initial state, the peak time sys _ clk and the transition time tran _ clk may take random values or may be set to 0. The update results generated by the interpolation estimator are subsequently used.
The specific process of the step 3 is as follows:
and (3) sending the interpolated baseband I and Q signals obtained in the step (2) to a Gardner timing error detection module. The Gardner timing error detection module is a module based on a Gardner timing error detection algorithm. The advantage of the Gardner timing error detection algorithm is that it is non-decision-oriented and timing recovery is independent of carrier phase. Using QPSK as an example, the subsequent interpolation estimator outputs two samples per symbol interval, and the samples between the sequence pairs are coincident in time. The symbols are transmitted synchronously at time intervals T. And (3) sending the interpolated baseband I and Q signals obtained in the step (2) to a Gardner timing error detection module. The Gardner timing error detection module is a module based on a Gardner timing error detection algorithm. The advantage of the Gardner timing error detection algorithm is that it is not decision-oriented and timing recovery is independent of carrier phase. Taking QPSK as an example, the subsequent interpolation estimator outputs two samples in each symbol interval, and the samples between the sequence pairs are coincident in time. The Gardner algorithm has two sampling points within one symbol, and takes the values of the peak time sys _ clk and the transition value time tran _ clk as the sampling points, one sampling point occurs at the peak time of the data, and the other sampling point occurs at the intermediate transition value time of the two optimal sampling points. y isI(r)、yQ(r) is the optimal sampling point value of the data of the r-th code element of the I path and the Q path,
the sample point value of the middle transition value time of the r-th and r-1-th code elements of the I path and the Q path. The Gardner timing error detection algorithm can be expressed as:
the Gardner timing error detection algorithm can be expressed as:
wherein err (r) is a timing error detection result, and if the error is positive, the timing lags; if the error is negative, the timing is advanced. However, if no transition occurs in the adjacent symbol waveform, this case does not allow information to be obtained from the timing error.
The above formula represents: and the timing error detection module samples at the moment of a transition value between each peak value of the I and Q baseband signals. Assuming that if there is no timing error, the value of the transition value point should be 0, if the value of the transition value time is not 0, the value of the timing error can be represented by the value, and since the value of the transition value time can be positive or negative, the present invention also needs the peak time to provide the positive or negative direction of the error, as shown in fig. 2, the direction of the error can be determined according to the sign relationship between two peaks. In the illustrated construction, the sign value of the sample value at the previous peak time is subtracted from the sign value of the sample value at the current peak time. If the sampled values at the two peak instants are of the same sign, there is no transition instant near the zero crossing, i.e. this transition instant is discarded. The same structure is adopted for the decision of the timing error err (r), and the timing error output in the design is shown in fig. 3.
FIG. 2 illustrates the Gardner timing error detection principle, which can be measured by the position y of the peak sampling pointI(n)-yI(n-1) reflecting the phase deviation direction of the local timing pulse, wherein when the timing is delayed, the error is positive; the error is negative with timing advance. Otherwise, it is the best sampling point. y (n) represents the nth sample point of the Gardner timing error detection, y (n-1) represents the last sample point of y (n), and y (n-1/2) represents the point just in between y (n-1) and y (n).
As can be seen in FIG. 2a, the sampled values y of adjacent symbolsI(n)、yIWhen (n-1) is not equal, if yI(n-1/2) =0, this means that the local timing pulse generated is exactly atThe optimal sampling position, where there is no timing error. FIG. 2b shows the values y of samples of adjacent symbolsI(n)、yIWhen (n-1) is not equal, if
The local timing pulse lags behind the ideal timing pulse. When the timing is delayed, the timing error is positive. FIG. 2c shows the values y of samples of adjacent symbolsI(n)、yIWhen (n-1) is not equal, if
A situation where the local timing pulse leads the ideal timing pulse. The timing error is negative when the timing is advanced.
Fig. 3 shows the result of increasing the output of the Gardner timing error detection module in the present design structure with time. And 4, performing loop filtering on the timing error generated by the Gardner algorithm module in a loop filter, and filtering noise interference to obtain a more effective timing error.
The specific process of the step 4 comprises the following steps: the timing error generated in the Gardner timing error detection module in step 3 enters a loop filter, which aims to obtain a timing error with better effect and filter interference and noise in the error. When the loop filter enters a steady state, the timing error generated by the Gardner timing error detection module will converge to near true values, as shown in FIG. 4.
Fig. 4 shows the convergence of the timing error generated by the Gardner timing error detection module after the loop filter processing, and it can be seen that the timing error value becomes smaller and smaller as time increases, and finally convergence is achieved.
And 5, updating the sampling decision condition and the peak value moment and the transition value moment by the interpolation estimator according to the timing error output by the loop filter. After updating, the steps S2-S5 are repeated to continuously perform timing recovery.
The filtered timing error generated in step 4 is fed to an interpolation estimator. The interpolation estimator is a modulo-1 phase decrementer, assuming symbol period intervals of the input signal are TiThen, thenThe purpose of the interpolation estimator is to generate an average period of TiTo make a sampling decision on the input signal. Every time the phase decrementer overflows it means the execution of a sampling decision. Assuming that the content of the phase register at the mth clock time of the interpolation estimator corresponding to the peak time is η (m), and the control word of the interpolation estimator is ω (m), the difference formula of the phase decrement is:
η(m+1)＝η(m)-ω(m))mod(1) (3)
where mod (1) represents a modulo 1 operation.
Omega (m) is adjusted by an error signal generated by a Gardner timing error detection module, and its value is obtained by the formula
In the formula, the sampling interval is TsSymbol period interval of input signal is TiThere is often a certain error between the initial value and the actual real value. e (m) is the output of the Gardner timing error detection module after the timing error is loop filtered, and is used for adjusting omega (m) so as to update the peak value time and the transition value time generated by the sampling decision condition and the interpolation estimator.
The updating process of the peak time is as follows: the control word ω (m) of the interpolation estimator starts at the previous peak time within one signal period and continues with ω (m) as the step length until the next peak is reached. When the timing error is a positive value, namely timing lags, ω (m) is increased, which leads η (m + 1) < ω (m) to appear in advance, namely, the timing pulse is adjusted backwards, and the interval between pulses is slightly reduced; when the timing error is negative, the adjustment is performed in the same manner, and the interval between pulses is slightly increased. When the timing error is 0, extremum sampling is realized, at this time, the loop filter output is unchanged, and ω (m) is the real ratio obtained by timing recovery. Then, η (m) is compared with ω (m), and the comparison result is outputted as the updated peak time. As shown in the dashed line box in fig. 5 (b), the output at the peak time is a pulse, which can be written as:
where 1 is high and 0 is low. A high level corresponds to the respective peak instant.
The updating process of the transition value time is similar to the peak time, but the initial value of the transition value time of each symbol period is calculated from the previous peak time. Assuming that the content of the phase register at the mth clock instant of the interpolation estimator corresponding to the instant of the transition value is tr (m), as shown in the dashed box of fig. 5 (c), the corresponding output is:
tr(m+1)＝tran(m)-ω(m))mod(1) (7)
where tran (m) is the middle value of the transition value time, and represents the last decision of tran _ clk controlled by sym _ clk, and tr (m + 1) represents the value of tran (m) before update.
The structure of the output timing error Decimal _ out is shown in the dashed box of FIG. 5 (d), with the output equal to:
in specific implementation, the structure of the interpolation estimator is preferably implemented as follows:
fig. 5 is a block diagram of an interpolation estimator, as shown in fig. 5, which provides an output value at the peak time of decision generation, an output value at the transition time, and an output value of timing error.
Wherein figure 5a is an overview of the interpolation estimator.
Wherein FIG. 5b is a decision structure of peak time, the structure comprising an adderThe module add1, add2, the module mod1 and the comparison and decision module compare1. Input error signal e (m) and
(e.g. taking
) Adding at add1 generates the control word ω (m) of the interpolation estimator, and ω (m) and the content η (m) of the previous mth clock time phase register are subtracted at add2, and then the obtained difference is subjected to modulo-1 operation by a modulo-1 operation module mod1 to obtain the content η (m + 1) of the updated m +1 th clock time phase register. And then entering a delay unit delay1, holding the updated η (m + 1), and outputting a peak pulse (sym _ clk) in the comparison decision module compare1 when η (m) is less than ω (m) to make a decision of the peak time. And a Delay unit Delay2 is used at the output end of the comparison decision module compare1 to simulate the Delay in an actual system.
Fig. 5c is a structure of a decision at a transition value time, which is similar to the structure of a decision at a peak value time, and includes adder modules add1 and add3, a modulo operation module mod2, a comparison decision module compare2, and a switch K1. Input error signals e (m) and
(e.g. taking
) Adding at add1 generates the control word ω (m) of the interpolation estimator, and ω (m) and the content tran (m) of the previous mth clock time phase register are subtracted in add3, and then the resulting difference is modulo-1 operated by the modulo-1 operation module mod1, so as to obtain the content tr (m + 1) of the updated (m + 1) th clock time phase register. Then enters the delay unit delay3, and the updated η (m + 1) is maintained, and meanwhile, the signal entering the switch K1 is ensured to be the content tr (m) of the phase register at the mth clock moment. In the tap decision process of K1, the generation of tran (m) is output in a peak time decision structurePeak pulse (sym _ clk) as decision condition: the value of the previous-stage signal tran (m) may be represented by η (m) +0.5 when the peak pulse is output, and may be represented by the value tr (m) when the peak pulse is not output. The obtained tran (m) is sent to a comparison decision module compare2, and in a transition value pulse output part of the comparison decision module compare2, when the tran (m) is smaller than ω (m), a transition value pulse (tran _ clk) is output to generate the decision of the transition value time. The output end of the comparison decision module compare2 uses a Delay unit Delay4 to simulate the Delay in the actual system.
Where figure 5d is the decision structure for timing errors. Comprises D flip-flops D1 and D2, multiplier modules mul1 and mul2 and a switch K2.D flip-flop D1 stores the product produced by the inverse of tran (m) and ω (m) via multiplier mul1, passing to K2 when tran _ clk arrives; d flip-flop D2 stores the product of η (m) and the reciprocal of ω (m) via multiplier mul2, which is passed to K2 when sym _ clk arrives. In the switch K2 generating the timing error module, the transition value timing decision structure outputs a peak pulse (tran _ clk) as a decision condition: when the transition value pulse is output, the output value of the timing pulse is the product of tran (m) and the reciprocal of ω (m), and when the transition value pulse is not output, the output value of the timing pulse is the product of η (m) and the reciprocal of ω (m).
The delay elements added in fig. 5 are to simulate the processing delays in practical applications and to keep the timing of these signals consistent. The pulse waveforms of stm _ clk and tran _ clk generated by the interpolation estimator are shown in fig. 6.
Fig. 6 is a timing waveform in the interpolation estimator. The first row is the I-path signal input by the baseband, the second row is the sampling point at the peak moment, and the third row is the sampling point at the transition value moment.
The whole system loop is shown in fig. 1, and the required accurate decision time can be obtained by continuously repeating the previous steps by using the peak value time and the transition value time generated by the interpolation estimator.
In specific implementation, the structure of the interpolation estimator can be realized by adopting an FPGA or a software mode. It is within the scope of the present invention to implement a timing recovery system, such as an FPGA implemented device, including a signal receiver, a cubic interpolator, a Gardner timing error detection module, a loop filter, and an interpolation estimator.
The specific embodiments described herein are merely illustrative of the spirit of the invention. Various modifications or additions may be made to the described embodiments or alternatives may be employed by those skilled in the art without departing from the spirit or ambit of the invention as defined in the appended claims.
Claims (5)
1. A variable symbol rate timing recovery method based on Gardner algorithm, realize the timing recovery of the variable symbol rate based on timing recovery system, include the signal receiver, cubic interpolator, gardner timing error detection module and loop filter connected sequentially in the said timing recovery system, characterized by that: in a timing recovery system, an interpolation estimator is provided, the execution comprising the steps of,
step 1, performing down-conversion and filtering processing on an intermediate frequency signal received by a signal receiver to obtain baseband I and Q signals;
step 2, interpolating the baseband I and Q signals by using a sampling judgment condition generated by an interpolation estimator to obtain interpolated baseband I and Q signals;
step 3, based on the interpolated baseband I, Q signals obtained in the step 2, under the trigger of the peak value moment and the transition value moment generated by the interpolation estimator, a timing error is obtained by using a Gardner algorithm module;
step 4, performing loop filtering on the timing error generated by the Gardner algorithm module, and filtering noise interference to obtain a more effective timing error;
step 5, the interpolation estimator updates the sampling judgment condition and the peak value time and the transition value time generated by the interpolation estimator according to the timing error output by the loop filter, updates the sampling judgment condition and the peak value time and the transition value time generated by the interpolation estimator by using the interpolation estimator, and repeats the steps 2-5;
let the content of the phase register at the mth clock instant of the interpolation estimator be η (m), the control word of the interpolation estimator be ω (m), and the difference formula of the decreasing phase is:
η(m+1)＝(η(m)-ω(m))mod(1)
ω (m) is adjusted by the error signal generated by the Gardner timing error detection module, as follows,
wherein the sampling interval is TsSymbol period interval of input signal is TiE (m) is a value of the timing error filtered by the loop to adjust ω (m) to update the sampling decision condition and the peak time sys _ clk and the transition time tran _ clk generated by the interpolation estimator;
in step 5, the peak time is updated as follows,
the control word ω (m) of the interpolation estimator starts at the previous peak time and continues with ω (m) as the step length until the next peak is reached within one signal period;
when the timing error is a positive value, increasing omega (m), leading eta (m + 1) < omega (m) to appear in advance, adjusting the timing pulse backwards, and slightly reducing the interval between pulses;
when the timing error is a negative value, the adjustment is carried out forward in the same way, and the interval between pulses is slightly increased;
when the timing error is 0, extreme value sampling is realized, the output of the loop filter is unchanged, and omega (m) is a real ratio obtained by timing recovery;
then comparing eta (m) with omega (m) and outputting the eta (m) and omega (m) as the updated peak value moment; the output at peak time is a pulse written as:
wherein 1 is a high level, 0 is a low level, and the high level corresponds to a corresponding peak time;
in the updating process of the transition value time, the initial value of the transition value time of each symbol period is calculated from the previous peak value time, and sym _ clk is used as the decision basis of output, and the output is as follows:
tr(m+1)＝(tran(m)-ω(m))mod(1)
wherein, tran (m) represents the upper-level decision of tran _ clk controlled by sym _ clk, and tr (m + 1) represents the value of tran (m) before update;
the output of the output timing error Decimal _ out is equal to:
2. the method of claim 1 for variable symbol rate timing recovery based on Gardner algorithm, wherein: and the sampling judgment condition generated by the interpolation estimator is timing error Decimal out, and baseband I and Q signals are respectively interpolated according to the timing error Decimal out output by the interpolation estimator as the interpolation time.
3. A variable symbol rate timing recovery method based on Gardner algorithm according to claim 2, characterized in that: the interpolation estimator is a modulo-1 phase decrementer, assuming a symbol period interval of the input signal of TiThe interpolation estimator is used to generate an average period of TiTo the input signalThe numbers are sampled and decided.
4. The method of claim 1 for variable symbol rate timing recovery based on Gardner algorithm, wherein: the interpolation estimator is implemented as follows,
the structure for judging the peak time comprises adder modules add1 and add2, a modulus operation module mod1 and a comparison judgment module match 1, and input error signals e (m) and
adding the control word omega (m) of the interpolation estimator at add1, carrying out subtraction operation on omega (m) and the content eta (m) of the previous mth clock time phase register in add2, and then carrying out modulo 1 operation on the obtained difference value by using a modulo operation module mod1 to obtain the content eta (m + 1) of the updated m +1 th clock time phase register; then, the output signal enters a delay unit delay1, the updated eta (m + 1) is kept, in a comparison and judgment module compare1, when the eta (m) is smaller than omega (m), a peak pulse is output as a peak time sym _ clk, and the judgment for generating the peak time uses a delay unit delay2 to simulate the delay in an actual system at the output end of the comparison and judgment module compare 1;
the structure for judging the transition value moment comprises adder modules add1 and add3, a modular operation module mod2, a comparison judgment module compare2, a switch K1 and input error signals e (m) and
adding the control word ω (m) of the interpolation estimator at add1, subtracting ω (m) from the content tran (m) of the previous mth clock time phase register at add3, and performing modulo-1 operation on the obtained difference by using a modulo operation module mod1 to obtain the content tr (m + 1) of the updated (m + 1) th clock time phase register; then, the signal enters a delay unit delay3, the updated eta (m + 1) is kept, and meanwhile, the signal entering the switch K1 is ensured to be the content tr (m) of the phase register at the mth clock moment; in the tap decision process of K1, the generation of tran (m) is decided at peak timeThe structure outputs a peak pulse (sym _ clk) as a judgment condition: when the peak pulse is output, the value of the previous signal tran (m) is represented by η (m) +0.5, and when the peak pulse is not output, the value of the previous signal tran (m) is represented by the value of tr (m), the obtained tran (m) is sent to a comparison decision module compare2, and in a transition value pulse output part of the comparison decision module compare2, when the tran (m) is smaller than ω (m), a transition value pulse is output as a transition value time tran _ clk for making a decision of the transition value time; the output end of the comparison judgment module match 2 uses a delay unit delay4 to simulate the delay in an actual system;
the decision structure of the timing error comprises D flip-flops D1 and D2, multiplier modules mul1 and mul2 and a switch K2, wherein the D flip-flop D1 stores the product of tram (m) and the reciprocal of omega (m) generated by the multiplier mul1, and transmits the product to the switch K2 when tran _ clk arrives; d flip-flop D2 stores the product of eta (m) and the reciprocal of omega (m) through multiplier mu12, and transmits to K2 when sym _ c1K arrives; in the switch K2 generating the timing error module, the transition value timing decision structure outputs a peak pulse (tran _ clk) as a decision condition: when the transition value pulse is output, the output value of the timing pulse is the product of tran (m) and the reciprocal of ω (m), and when the transition value pulse is not output, the output value of the timing pulse is the product of η (m) and the reciprocal of ω (m).
5. A variable symbol rate timing recovery device based on Gardner algorithm, characterized by: a method for implementing a variable symbol rate timing recovery based on the Gardner algorithm as claimed in any one of claims 1-4.
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