CN113162622A

CN113162622A - Analog-to-digital converter device and clock skew correction method

Info

Publication number: CN113162622A
Application number: CN202010074212.XA
Authority: CN
Inventors: 康文柱; 陈昱竹; 汪鼎豪
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd; Global Unichip Corp
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd; Global Unichip Corp
Priority date: 2020-01-22
Filing date: 2020-01-22
Publication date: 2021-07-23
Anticipated expiration: 2040-01-22
Also published as: CN113162622B

Abstract

An analog-to-digital converter device and a clock skew correction method are disclosed. The analog-to-digital converter device includes: a plurality of analog-to-digital conversion circuits, a correction circuit, and a skew adjustment circuit. The plurality of analog-to-digital conversion circuits are used for converting the input signal according to the plurality of staggered clock signals to generate a plurality of first quantized outputs. The correction circuit is used for executing at least one correction operation according to the first quantized output so as to generate a plurality of second quantized outputs. The skew adjusting circuit is used for determining a plurality of calculation signals respectively corresponding to the second quantization output in a preset period, averaging the calculation signals to generate a reference signal, comparing the reference signal with the calculation signals to generate a plurality of detection signals, and judging whether to adjust the detection signals according to the signal frequency to generate a plurality of adjusting signals, wherein the adjusting signals are used for reducing the clock skew of the analog-digital conversion circuit. Therefore, the effects of reducing the overall power consumption and correcting the period are achieved.

Description

Analog-to-digital converter device and clock skew correction method

Technical Field

The present disclosure relates to an analog-to-digital converter device, and more particularly, to a time-interleaved analog-to-digital converter and a clock skew correction method thereof.

Background

Analog-to-digital converters (ADCs) are commonly used in various electronic devices to convert analog signals into digital signals for signal processing. In practical applications, the ADC may affect its own resolution or linearity due to gain error, voltage error or timing error. In the prior art, for timing errors, complicated circuits (e.g., additional reference ADC circuits, auxiliary ADC circuits) are required to be provided or off-chip (off-chip) correction is used for correction, so that power consumption of the ADC or a period required for correction is higher and higher.

Disclosure of Invention

In a first aspect of the present invention, an analog-to-digital converter device is provided, including: a plurality of analog-to-digital conversion circuits, a correction circuit, and a skew adjustment circuit. The plurality of analog-to-digital conversion circuits are used for converting the input signal according to the plurality of staggered clock signals to generate a plurality of first quantized outputs. The correction circuit is used for executing at least one correction operation according to the first quantized output so as to generate a plurality of second quantized outputs. The skew adjusting circuit is used for determining a plurality of calculation signals respectively corresponding to the second quantization output in a preset period, averaging the calculation signals to generate a reference signal, comparing the reference signal with the calculation signals to generate a plurality of detection signals, and judging whether to adjust the detection signals according to the signal frequency to generate a plurality of adjusting signals, wherein the adjusting signals are used for reducing the clock skew of the analog-digital conversion circuit.

According to an embodiment of the present disclosure, the skew adjustment circuit is further configured to perform a plurality of absolute value operations on a plurality of difference signals to generate a plurality of absolute value signals, and to perform a plurality of maximum value operations on the plurality of absolute value signals to generate a plurality of maximum value signals, wherein the plurality of difference signals are generated according to the plurality of second quantized outputs.

According to an embodiment of the present invention, the skew adjustment circuit is configured to multiply the detection signals by a first ratio to generate the adjustment signals when the frequency of the signal is greater than a frequency threshold.

According to an embodiment of the present invention, the skew adjustment circuit is configured to multiply the detection signals by a second ratio to generate the adjustment signals when the frequency of the signal is less than a frequency threshold.

According to an embodiment of the present disclosure, the skew adjustment circuit includes: a delay circuit for delaying a last one of the second quantized outputs to generate a delayed quantized output; a plurality of operational circuits for receiving the delayed quantized output and the second quantized outputs in sequence, and for generating a plurality of difference signals according to two signals of the delayed quantized output and the second quantized outputs; a plurality of absolute value circuits, wherein each of the absolute value circuits is configured to perform an absolute value operation according to a corresponding one of the difference signals to generate a corresponding absolute value signal; a plurality of maximum value circuits, wherein each maximum value circuit is used for receiving a corresponding absolute value signal and executing a maximum value operation to output a corresponding maximum value signal, wherein the corresponding maximum value signal is generated by a maximum value of the corresponding absolute value signal in the preset period; an averaging circuit for performing an averaging operation to average the maximum value signals to generate the reference signal; a plurality of comparison circuits for comparing each of the maximum value signals with the reference signal to generate the detection signals; and a plurality of multiplying circuits for multiplying the detecting signals by one of a first ratio and a second ratio according to the signal frequency to generate the adjusting signals.

According to an embodiment of the present disclosure, the skew adjustment circuit includes: a first adjusting circuit for analyzing even quantized outputs of the second quantized outputs to generate a first portion of the adjusted signals; and a second adjusting circuit for analyzing odd-numbered quantized outputs of the second quantized outputs to generate a second portion of the adjusted signals.

According to an embodiment of the present invention, when the signal frequency is greater than a frequency threshold, the first adjusting circuit is configured to multiply an even number of the detection signals by a first ratio to generate the first portion of the adjusting signals; and the second adjusting circuit is used for multiplying odd detecting signals in the detecting signals by the first ratio to generate the second parts of the adjusting signals.

According to an embodiment of the present invention, when the signal frequency is less than a frequency threshold, the first adjusting circuit is configured to multiply an even number of the detection signals by a second ratio to generate the first portion of the adjusting signals; and the second adjusting circuit is used for multiplying odd detection signals in the detection signals by the second ratio to generate the second parts of the adjusting signals.

According to an embodiment of the present disclosure, the first adjusting circuit further includes: a delay circuit for delaying a last one of the even quantized outputs to generate a delayed quantized output; a plurality of operational circuits for receiving the delayed quantized output and the even-numbered quantized outputs in sequence, and for generating a plurality of difference signals according to two signals of the delayed quantized output and the second quantized outputs, respectively; a plurality of absolute value circuits, wherein each of the absolute value circuits is configured to perform an absolute value operation according to a corresponding one of the difference signals to generate a corresponding absolute value signal; a plurality of statistical circuits, wherein each statistical circuit is used for receiving a corresponding absolute value signal in the preset period and executing a statistical operation to output a corresponding calculation signal; an averaging circuit for performing an averaging operation to average the calculated signals to generate the reference signal; a plurality of comparison circuits for comparing each of the calculation signals with the reference signal to generate the detection signals; and a plurality of multiplication circuits for multiplying even ones of the detection signals by one of a first ratio and a second ratio according to the signal frequency to generate the first portions of the adjustment signals.

According to an embodiment of the present disclosure, the second adjusting circuit further includes: a delay circuit for delaying a last one of the odd quantized outputs to generate a delayed quantized output; a plurality of operational circuits for receiving the delayed quantized output and the odd-numbered quantized outputs in sequence, and for generating a plurality of difference signals according to two signals of the delayed quantized output and the second quantized outputs; a plurality of absolute value circuits, wherein each of the absolute value circuits is configured to perform an absolute value operation according to a corresponding one of the difference signals to generate a corresponding absolute value signal; a plurality of statistical circuits, wherein each statistical circuit is used for receiving a corresponding absolute value signal in the preset period and executing a statistical operation to output a corresponding calculation signal; an averaging circuit for performing an averaging operation to average the calculated signals to generate the reference signal; a plurality of comparison circuits for comparing each of the calculation signals with the reference signal to generate the detection signals; and a plurality of multiplication circuits for multiplying even ones of the detection signals by one of a first ratio and a second ratio according to the signal frequency to generate the first portions of the adjustment signals.

In a second aspect, a clock skew correction method is provided, which includes: performing at least one correction operation according to a plurality of first quantized outputs generated by a plurality of analog-to-digital conversion circuits to generate a plurality of second quantized outputs; determining a plurality of calculation signals respectively corresponding to the second quantization output in a predetermined period through a skew adjusting circuit, and averaging the calculation signals to generate a reference signal; comparing the reference signals with the calculation signals respectively through a skew adjusting circuit to generate a plurality of detection signals; judging whether to adjust the detection signal or not according to the signal frequency through a skew adjusting circuit so as to generate a plurality of adjusting signals; the adjusting signal is used for reducing the clock skew of the analog-digital conversion circuit.

According to an embodiment of the present invention, determining the calculation signals further comprises: performing a plurality of absolute value operations on a plurality of difference signals to generate a plurality of absolute value signals, wherein the difference signals are generated according to the second quantized outputs; and performing a plurality of maximum value operations on the absolute value signals respectively to generate a plurality of maximum value signals.

According to an embodiment of the present invention, the skew adjustment circuit is configured to multiply the detection signals by a second ratio to generate the adjustment signals when the frequency of the signal is greater than a frequency threshold.

According to an embodiment of the present invention, determining the calculation signals further comprises: delaying a last one of the second quantized outputs to generate a delayed quantized output; sequentially receiving the delayed quantized output and the second quantized outputs, and respectively generating a plurality of difference signals according to two signals of the delayed quantized output and the second quantized outputs; performing an absolute value operation according to a corresponding difference signal of the difference signals to generate a corresponding absolute value signal; receiving the corresponding absolute value signal in the preset period and executing a maximum value operation to output a corresponding maximum value signal, wherein the corresponding maximum value signal is generated by a maximum value of the corresponding absolute value signal in the preset period; performing an averaging operation to average the maximum signals to generate the reference signal; comparing each of the maximum value signals with the reference signal to generate the detection signals; and multiplying the detection signals by one of a first ratio and a second ratio according to the signal frequency to generate the adjustment signals.

According to an embodiment of the present disclosure, generating the adjustment signals includes: analyzing even-numbered quantized outputs of the second quantized outputs by a first adjusting circuit to generate a first part of the adjusting signals; and analyzing odd-numbered quantized outputs of the second quantized outputs by a second adjusting circuit to generate a second portion of the adjusting signals.

According to an embodiment of the present disclosure, generating the first portion of the adjustment signals includes: delaying a last one of the even numbered quantized outputs to generate a delayed quantized output; sequentially receiving the delayed quantized output and the even quantized outputs, and respectively generating a plurality of difference signals according to two signals of the delayed quantized output and the second quantized outputs; performing an absolute value operation according to a corresponding difference signal of the difference signals to generate a corresponding absolute value signal; receiving corresponding absolute value signals in the preset period, and executing a statistic operation to output corresponding calculation signals; performing an averaging operation to average the calculated signals to generate the reference signal; comparing each of the calculated signals with the reference signal to generate the detection signals; and multiplying even ones of the detection signals by one of a first ratio and a second ratio according to the signal frequency to generate the first portions of the adjustment signals.

According to an embodiment of the present disclosure, generating the second portion of the adjustment signals includes: delaying a last one of the odd quantized outputs to generate a delayed quantized output; sequentially receiving the delayed quantized output and the odd-numbered quantized outputs, and respectively generating a plurality of difference signals according to two signals of the delayed quantized output and the second quantized outputs; performing an absolute value operation according to a corresponding difference signal of the difference signals to generate a corresponding absolute value signal; receiving corresponding absolute value signals in the preset period, and executing a statistic operation to output corresponding calculation signals; performing an averaging operation to average the calculated signals to generate the reference signal; comparing each of the calculated signals with the reference signal to generate the detection signals; and multiplying odd-numbered detection signals of the detection signals by one of a first ratio and a second ratio according to the signal frequency to generate the second part of the adjustment signals.

The analog-to-digital converter device and the clock skew correction method of the invention mainly selectively adjust the detection signal according to the signal frequency, so that when the input signal frequency is greater than the Nyquist frequency, the digital converter device can still obtain the clock skew information through simple operation to correct. Thus, the overall power consumption and calibration period can be reduced.

Drawings

The foregoing and other objects, features, advantages and embodiments of the disclosure will be apparent from the following more particular description of the disclosure, as illustrated in the accompanying drawings in which:

fig. 1A is a schematic diagram of an adc device according to some embodiments of the disclosure;

FIG. 1B is a waveform diagram of the clock signals of FIG. 1A according to some embodiments of the disclosure;

FIG. 2 is a circuit diagram illustrating the skew adjustment circuitry of FIG. 1A according to some embodiments of the present disclosure;

fig. 3 is a flowchart illustrating a method of clock skew correction according to some embodiments of the disclosure;

FIG. 4 is a schematic diagram of an analog-to-digital converter device according to some embodiments of the present disclosure;

FIGS. 5A and 5B are schematic circuit diagrams of the adjusting circuit of FIG. 4 according to some embodiments of the disclosure; and

fig. 6 is a flowchart illustrating a clock skew correction method according to some embodiments of the disclosure.

[ notation ] to show

100 … analog-to-digital converter device

110 … A/D converter circuit

120 … correction circuit

130 … skew adjustment circuit

132. 134 … regulating circuit

140 … output circuit

CLK₀～CLK_M-1… clock signal

Q₀～Q_M-1、CQ_-2～CQ_M-1、CQ_-1… quantized output

SIN … input signal

fs … sampling frequency

TS … sampling period

ST … predetermined period

SOUT … digital signal

T₀～T_M-1… adjustment signal

205. 207, 209 … delay circuit

210. 212, 214 … arithmetic circuit

220. 222, 224 … absolute value circuit

230 … maximum value circuit

232. 234 … statistical circuit

240. 242, 244 … averaging circuit

250. 252, 254 … comparison circuit

260. 262, 264 … multiplication circuit

270. 272, 274: filter circuit

280. 282, 284: integrating circuit

D₀～D_M-1… difference signal

A₀～A_M-1… absolute value signal

M₀～M_M-1… maximum value signal

REF, REF1, REF2 … reference signals

SD₀～SD_M-1、TSD₀～TSD_M-1… detection signal

K … ratio

Threshold value TH1 …

TR₀～TR_M-1… trigger signal

300. 600 … clock skew correction method

S310 to S340, S610 to S640 …

Detailed Description

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference numbers indicate the same or similar elements or process flows.

Referring to fig. 1A and 1B, fig. 1A is a schematic diagram of an analog-to-digital converter (ADC) device 100 according to some embodiments of the disclosure. FIG. 1B illustrates the plurality of clock signals CLK of FIG. 1A according to some embodiments of the disclosure₀～CLK_M-1Schematic diagram of the waveform of (1). In some embodiments, the ADC device 100 operates as a time-interleaved ADC with multiple channels.

In some embodiments, the ADC device 100 includes a plurality of analog-to-digital conversion circuits 110, a correction circuit 120, a skew (skew) adjustment circuit 130, and an output circuit 140. It is noted that each ADC circuit 110 operates as a single channel. In other words, in this example, the ADC device 100 includes M channels. In some embodiments, M is an even number. As shown in FIG. 1A, the analog-to-digital conversion circuits 110 are configured to convert a plurality of clock signals CLK₀～CLK_M-1One of them performs analog-to-digital conversion on the input signal SIN to generate the corresponding quantized output Q₀～Q_M-1。

As shown in FIG. 1B, a plurality of clock signals CLK₀～CLK_M-1Two adjacent clock signals have a time interval between them, so that the 1 st channel and the 2 nd channel perform sampling operation and analog-to-digital conversion at different times. For example, the 1 st channel (i.e., according to the clock signal CLK)₀The operational ADC circuit 110) samples the input signal SIN at the 1 st sampling time S1, performs ADC, and performs the 2 nd pass (i.e. according to the clock signal CLK)₁The operational adc circuit 110) samples the input signal SIN at the 2 nd sampling time S2 and performs adc. The difference between the sampling times S1 and S2 is the sampling period TS (corresponding to the sampling frequency fs, that is, TS is 1/fs).And so on, M channels may operate according to multiple staggered timings).

As mentioned above, the calibration circuit 120 is coupled to each adc circuit 110 for receiving a plurality of quantized outputs Q₀～Q_M-1. The calibration circuit 120 outputs Q according to the quantization₀～Q_M-1Performing at least one correction operation to correct offset (offset) and gain (gain) errors in the analog-to-digital conversion circuits 110 and generate a plurality of corrected quantized outputs CQ₀～CQ_M-1。

In some embodiments, the correction circuit 120 may be a foreground correction circuit or a background correction circuit. For example, the calibration circuit 120 may include a pseudo-random number generator circuit (not shown) and a digital processing circuit (not shown), wherein the pseudo-random number generator circuit generates a calibration signal to the adc circuit 110, and the digital processing circuit outputs Q according to a plurality of quantization levels₀～Q_M-1An adaptive algorithm (i.e., the aforementioned at least one correction operation) is performed to reduce the quantized output Q₀～Q_M-1Offset or error of. The calibration circuit 120 is only used for illustration, and the disclosure is not limited thereto. Various types of calibration circuits 120 are contemplated by the present disclosure.

In light of the above, the skew adjusting circuit 130 is electrically coupled to the correcting circuit 120 to receive the plurality of corrected quantized outputs CQ₀～CQ_M-1. In some embodiments, the skew adjustment circuit 130 may output the CQ according to the quantization₀～CQ_M-1Analyzing the clock skew (corresponding to phase error) existing among the analog-to-digital conversion circuits 110 to generate a plurality of adjusting signals T₀～T_M-1. In some embodiments, the skew adjustment circuitry 130 adjusts the plurality of adjustment signals T₀～T_M-1Respectively output to a plurality of analog-to-digital conversion circuits 110, a plurality of adjustment signals T₀～T_M-1The timing adjustment module is used for indicating the timing required to adjust the plurality of analog-to-digital conversion circuits 110 due to clock skew.

In some embodiments, the analog-to-digital conversion circuits 110 can adjust the adjustment signals T according to the adjustment signals T₀～T_M-1Adjusting the execution timing of the sampling operation and/or the analog-to-digital conversion operation to equivalently correct the clock skew. Alternatively, in some embodiments, multiple clock signals CLK₀～CLK_M-1Can be directly based on a plurality of adjusting signals T₀～T_M-1Adjusted to equivalently reduce clock skew. For example, a plurality of adjustment signals T₀～T_M-1Is inputted to a clock signal CLK for generating a plurality of clock signals₀～CLK_M-1A clock generator, a phase interpolator, or a digital delay control line for adjusting a plurality of clock signals CLK₀～CLK_M-1The phase of (c). According to the adjusting signal T₀～T_M-1The manner of reducing clock skew is used for illustration and the disclosure is not limited thereto.

In light of the above, the output circuit 140 is electrically coupled to the calibration circuit 120 for receiving the calibrated multiple quantized outputs CQ₀～CQ_M-1. The output circuit 140 outputs CQ according to the plurality of quantized outputs after correction₀～CQ_M-1The data combining operation is performed to generate the digital signal SOUT. Through the data combination operation, a plurality of quantized output CQ provided by M channels can be output₀～CQ_M-1Are combined into a single digital signal SOUT having a sampling frequency fs, wherein the sampling frequency fs is M times the clock signal frequency. In some embodiments, the output circuit 140 may be implemented by a multiplexer circuit, but the disclosure is not limited thereto.

Referring to fig. 2, fig. 2 is a circuit diagram illustrating the skew adjustment circuitry 130 of fig. 1A according to some embodiments of the disclosure. For ease of understanding, similar elements of FIG. 2 will be designated with the same reference numerals with reference to FIG. 1A. In some embodiments, the skew adjustment circuit 130 includes a delay circuit 205, a plurality of operation circuits 210, a plurality of absolute value circuits 220, a plurality of maximum value circuits 230, an averaging circuit 240, a plurality of comparison circuits 250, and a plurality of multiplication circuits 260.

The delay circuit 205 is used to delay the quantized output CQ of FIG. 1A_M-1To generate a delayed quantized output CQ_-1. In some embodiments, the delay time introduced by the delay circuit 205 is equivalent toThe period M × TS in fig. 1B. The delay circuit 205 may be implemented by various digital circuits, such as buffers, inverters, filters, and so on. The above-described implementation of the delay circuit 205 is used for example, and the disclosure is not limited thereto.

The plurality of operation circuits 210 are electrically coupled to the calibration circuit 120 in fig. 1A. The plurality of arithmetic circuits 210 sequentially receive the quantized output CQ_-1To CQ_M-1To respectively generate a plurality of difference signals D₀～D_M-1. Taking the 1 st operational circuit 210 as an example, the 1 st operational circuit 210 receives the quantized output CQ_-1And CQ₀And outputs the quantization CQ₀Subtract the quantized output CQ_-1To generate a difference signal D₀. The setting and operation of the rest of the operation circuits 210 can be analogized, and thus, the description thereof is not repeated. In some embodiments, the operation circuit 210 can be implemented by a subtractor or other processing circuits with the same function. Various circuits for implementing the operation circuit 210 are within the scope of the present disclosure.

The absolute value circuits 220 are electrically coupled to the operation circuits 210 respectively to receive the difference signals D respectively₀～D_M-1. Each absolute value circuit 220 is based on a plurality of difference signals D₀～D_M-1Performs an absolute value operation on a corresponding difference signal to generate a plurality of absolute value signals A₀～A_M-1One corresponding to the other. Taking the 1 st absolute value circuit 220 as an example, the 1 st absolute value circuit 220 receives the difference signal D₀And performing an absolute value operation to obtain a difference signal D₀To generate an absolute value signal a₀. The setting and operation of the remaining absolute value circuits 220 may be similar, and thus are not repeated. In some embodiments, the absolute value circuit 220 may be implemented by a processing circuit or a rectifying circuit, and various circuits for implementing the absolute value circuit 220 are all within the scope of the present disclosure.

The maximum value circuits 230 are electrically coupled to the absolute value circuits 220 respectively to receive the absolute value signals a respectively₀～A_M-1. Each maximum circuit 230 is used for continuously receiving a plurality of absolute values in a predetermined period STFor value signal A₀～A_M-1And performing a maximum value operation to output a corresponding maximum value signal M₀～M_M-1. Corresponding maximum value signal M₀～M_M-1Is generated from a maximum value of the corresponding absolute value signal within the predetermined period ST. The setting and operation of the remaining maximum value circuit 230 can be analogized, and thus, the description thereof is not repeated.

In some embodiments, the maximum circuit 230 may be implemented by a digital processing circuit, a comparison circuit and/or a register circuit, but the disclosure is not limited thereto. Various circuits for implementing the maximum circuit 230 are within the scope of the present disclosure.

The averaging circuit 240 is electrically coupled to the maximum value circuits 230 for receiving the maximum value signals M₀～M_M-1. The averaging circuit 240 is used for generating a plurality of maximum value signals M₀～M_M-1Performing an averaging operation to average multiple maximum value signals M₀～M_M-1To generate a reference signal REF. In some embodiments, the averaging circuit 240 may be implemented by a digital processing circuit, but the disclosure is not limited thereto.

The plurality of comparison circuits 250 are coupled to the averaging circuit 240 to receive the reference signal REF. Each comparison circuit 250 is used for comparing each maximum value signal M₀～M_M-1And a reference signal REF to generate a corresponding detection signal SD₀～SD_M-1. Taking the 1 st comparator 250 as an example, the comparator 250 compares the maximum value signal M₀And a reference signal REF to generate a detection signal SD₀. The setting and operation of the other comparison circuits 250 can be analogized, and thus, the description thereof is not repeated.

In some embodiments, the comparison circuit 250 may be implemented by a comparator. Alternatively, in some embodiments, the comparison circuit 250 may be implemented by a subtractor circuit and subtracts the reference signal REF from the corresponding maximum signal M₀～M_M-1To generate a corresponding detection signal SD₀～SD_M-1. The above embodiments of the comparator circuit 250 are provided for illustration purposes, and the disclosure is not limited thereto.

The plurality of multiplication circuits 260 are electrically coupled to the comparison circuit 250 for receiving the plurality of detection signals SD₀～SD_M-1. Each multiplication circuit 260 is used for generating each detection signal SD according to the signal frequency₀～SD_M-1Multiplying by a ratio K to generate a corresponding adjusted detection signal TSD₀～TSD_M-1. In some embodiments, the multiplication circuit 260 may be implemented by a multiplier circuit. In other embodiments, the multiplication circuit 260 can be implemented by a multiplexer circuit, but the disclosure is not limited thereto.

As mentioned above, the multiplication circuit 260 is used to detect the signal SD when the frequency of the signal is greater than the frequency threshold₀～SD_M-1Multiplying the ratio K to generate an adjusted detection signal TSD₀～TSD_M-1. In one embodiment, the frequency threshold may be implemented as a Nyquist frequency (Nyquist frequency). For example, when the frequency of the input signal SIN is greater than the Nyquist frequency, the ratio K is set to-1, so that the adjusted detection signal TSD₀～TSD_MNegative detection signal SD₀～SD_M-1。

As mentioned above, when the signal frequency is less than the frequency threshold (i.e. the frequency of the input signal SIN is less than the nyquist frequency), the ratio K is set to 1, so that the adjusted detection signal TSD₀～TSD_M-1And a detection signal SD₀～SD_M-1The same is true.

Taking the operation of the 1 st operational circuit 210 as an example, as shown in FIG. 2, the signal T is adjusted₀Based on quantizing the output CQ₀And the quantized output CQ_-1The difference between them generating the adjusting signal T₀Can be used for indicating time T₀(i.e., quantizes the output CQ)₀Corresponding sampling time point) and time T_-1(i.e., quantizes the output CQ)_-1Corresponding sampling time points). Difference signal D₀In the time domain, the following equation (1) can be derived:

CQ₀-CQ_-1＝sin(2πf(n+1)(T+Δt))-sin(2πfnT)

≈2cos(2πfnT+πf(T+ΔT))·sin(πfT-πfnΔt)…(1)

wherein (n +1) (T + Δ T) corresponds to the quantized output CQ₀Corresponding sampling time points, k for indicating each quantized output CQ₀Or CQ_-1At the corresponding sampling time point, f is the frequency of the input signal SIN, Δ T is the time difference, and T is the period TS.

When the frequency of the input signal SIN is much less than the nyquist frequency (1/2T), equation (1) can be further derived as equation (2) below:

sin(2πf(n+1)(T+Δt))-sin(2πfnT)≈2cos(2πfnT+πf(T+Δt))·(πfT-πfnΔt)…(2)

from the equation (2), it can be known that the time difference Δ T and the difference signal D satisfy the condition that the frequency f is much less than 1/2T₀Is related to the amplitude of (i.e., pi fT-pi fn Δ t). Therefore, the maximum value signal M is generated by the operations of the absolute value circuit 220 and the maximum value circuit 230₀Information of the time difference value deltat can be reflected.

From this, the signal M is calculated by comparison₀The effect of the time difference Δ t caused by clock skew can be known from the reference signal REF 1. For example, if the signal M is calculated₀Greater than the reference signal REF, represents a positive contribution of the time difference Δ t. Under this condition, the clock skew causes the clock signal CLK₀Is incorrectly advanced. Alternatively, if the calculated signal M0 is lower than the reference signal REF, the effect of the representative time difference Δ t is negative. Under this condition, the clock skew causes the clock signal CLK₀Lags behind the incorrect phase of (b). Therefore, the adjusted detecting signal TSD is based on different comparison results₀Will have different logic values to reflect the phase information of the 1 st adc circuit 110 to be adjusted due to clock skew. By analogy, the above operations can be applied to the adjustment signals T₀～T_M-1And the adjusted detection signal TSD₀～TSD_M-1Therefore, the description is not repeated herein.

When the frequency of the input signal SIN is greater than the nyquist frequency (1/2T), equation (1) can be further derived as equation (3) below:

sin(2πf(n+1)(T+Δt))-sin(2πfnT)≈2cos(2πfnT+πf(T+Δt))·sin(-πfT-πfnΔt)…(3)

from the equation (3), the time difference Δ T and the difference signal D satisfy the condition that the frequency f is greater than 1/2T₀And the time difference deltat and the difference signal D when the relative frequency f is less than 1/2T₀The amplitude of (c) differs by a negative value. In other words, when the frequency f is greater than 1/2T, the operation with the frequency f greater than 1/2T can be the same as the operation with the frequency f less than 1/2T by multiplying the frequency f by a negative sign in the following operation.

In the following operation, when the signal frequency is higher than the nyquist frequency, the adjusted detecting signal TSD can still be used₀～TSD_M-1To reflect the phase information of the analog-to-digital conversion circuit 110 required to adjust due to clock skew.

In some related technologies, the information of clock skew is obtained when the signal frequency is less than the nyquist frequency. However, as the input frequency increases, in the case where it is difficult to increase the sampling frequency, a technique for obtaining information of clock skew even when the signal frequency is higher than the nyquist frequency is required. Therefore, compared with the above-mentioned techniques, the embodiments of the present disclosure can achieve that when the input signal frequency is greater than the nyquist frequency, the digitizer device can still obtain the information of the clock skew for calibration through simple operations, which can achieve lower power consumption and fewer calibration cycles.

In some further embodiments, the skew adjustment circuit 130 may further include a plurality of filtering circuits 270 and a plurality of integrating circuits 280. The plurality of filter circuits 270 are respectively coupled to the plurality of multiplier circuits 260 for respectively receiving the plurality of adjusted detection signals TSD₀～TSD_M。

The plurality of filter circuits 270 are arranged according to the plurality of adjusted detection signals TSD₀～TSD_M-1Generates a plurality of trigger signals TR with at least one threshold TH1₀～TR_M-1. The integrating circuits 280 are respectively coupled to the filtering circuits 270 to respectively receive the trigger signals TR₀～TR_M-1. Multiple integration circuits 280 based on multiple trigger signals TR₀～TR_M-1Producing a plurality of tonesInteger signal T₀～T_M-1。

In view of the above, taking the 1 st filter circuit 270 and the 1 st integrator circuit 280 as examples, the filter circuit 270 is electrically coupled to the 1 st multiplier circuit 260 for receiving the adjusted detection signal TSD₀. In some embodiments, the filter circuit 270 may continuously accumulate the adjusted detection signal TSD₀And comparing the accumulated adjusted detection signal TSD₀And at least one threshold value TH1 for outputting one or more trigger signals TR₀. For example, when the accumulated adjusted detection signal TSD₀When the accumulated adjusted detection signal TSD is greater than at least one threshold value TH1, the filter circuit 270 outputs the accumulated adjusted detection signal TSD₀Output as corresponding trigger signal TR₀. The 1 st integrator 280 is coupled to the 1 st filter 270 to receive the trigger signal TR₀. The integration circuit 280 is used for accumulating the trigger signal TR₀And the accumulated trigger signal TR is added₀Output as an adjustment signal T₀To match different timing control methods. The arrangement and operation of the remaining filter circuit 270 and the integrator circuit 280 may be similar, and thus are not repeated.

By providing the filter circuit 270, the number of clock skew correction operations can be reduced, thereby reducing the dynamic power consumption of the ADC apparatus 100. Meanwhile, jitter (jitter) caused by the corrected clock skew can be reduced by providing the filter circuit 270. By providing the integration circuit 280, the timing adjustment method can be adjusted to a corresponding value. In practical applications, the filter circuit 270 and the integrator circuit 280 can be selectively configured according to actual requirements. In addition, the threshold TH1 can be adjusted according to actual requirements.

In various embodiments, the filter circuit 270 and the integrator circuit 280 may be implemented by at least one comparator (e.g., for comparing the trigger signal with the threshold TH1 or comparing the accumulated trigger signal), at least one register (e.g., for storing the accumulated trigger signal or the accumulated trigger signal, etc.), at least one clearing circuit (e.g., for clearing data from the register), and/or at least one operational circuit (e.g., for generating the accumulated trigger signal or accumulating the trigger signal). The above arrangement of the filter circuit 270 and the integrator circuit 280 is for example, and the disclosure is not limited thereto.

Referring to fig. 3, fig. 3 is a flowchart illustrating a clock skew correction method 300 according to some embodiments of the disclosure. For ease of understanding, the clock skew correction method 300 will be described with reference to the aforementioned figures. In one embodiment, the clock skew correction method 300 first executes step S310 according to the quantized outputs Q generated by the analog-to-digital conversion circuits 110₀～Q_M-1Performing at least one correction operation to generate a plurality of quantized outputs CQ₀～CQ_M-1。

The clock skew correction method 300 then executes step S320 to determine the quantized output CQ through the skew adjustment circuit 130₀～CQ_M-1A plurality of maximum value signals M respectively corresponding to the predetermined period ST₀～M_M-1Averaging a plurality of maximum value signals M₀～M_M-1To generate a reference signal REF.

In step S330, the reference signal REF is respectively coupled to the maximum value signals M by the skew adjustment circuit 130₀～M_M-1Comparing to generate a plurality of detection signals SD₀～SD_M-1。

As mentioned above, in step S340, the skew adjustment circuit 130 determines whether to adjust the detection signal SD according to the signal frequency₀～SD_M-1To generate a plurality of adjusting signals T₀～T_M-1To reduce the clock skew in the analog-to-digital conversion circuits 110. The descriptions and the embodiments of the above operations can refer to the descriptions of the above embodiments, and thus the descriptions thereof are not repeated herein.

In another embodiment, fig. 4 is a schematic diagram of an adc device 400 according to some embodiments of the present disclosure. In some embodiments, the ADC unit 400 operates as a time-interleaved analog-to-digital converter with multiple channels. In this embodiment, the ADC device 400 is similar to the ADC device 100, and the difference between the two is the implementation of the skew adjustment circuit 130.

In light of the above, it is desirable that,in this embodiment, the skew adjustment circuit 130 includes

adjustment circuits

132 and 134. The adjusting circuit 132 is used for analyzing the quantized output CQ₀～CQ_M-1Quantized output CQ of (1)₀、CQ₂、…、CQ_M-2To generate the adjusting signals T₀～T_M-1First part (i.e. T)₀、T₂、…、T_M-2) And the adjusting circuit 134 is used for analyzing the quantized output CQ₀～CQ_M-1Quantized output CQ of odd term₁、CQ₃、…、CQ_M-1To generate a plurality of adjusting signals T₀～T_M-1Second part (i.e. T)₁、T₃、…、T_M-1)。

The adjustment circuit 132 quantizes the output CQ according to the even term₀、CQ₂、…、CQ_M-2Analyzing the clock skew (corresponding to the time difference information) existing between the even-term analog-to-digital conversion circuits 110 to generate a plurality of adjusting signals T₀、T₂、…、T_M-2. Output CQ due to quantization₀Corresponding to the 1 st sampling time S1 and quantizing the output CQ₂Corresponding to the 3 rd sampling time S3, the period difference between the two corresponding times is 2 sampling periods TS, so the analysis quantization output CQ₀And quantizing the output CQ₂Can obtain the clock signal CLK₀And a clock signal CLK₂Time difference information within 2 sampling periods TS. By analogy, in this way, the adjusting circuit 132 can analyze the clock signal CLK₀、CLK₂、…、CLK_M-2Time difference information within 2 sampling periods TS.

Similarly, the adjustment circuit 134 quantizes the output CQ according to odd terms₁、CQ₃、…、CQ_M-1Analyzing the clock skew existing between the odd-term analog-to-digital conversion circuits 110 to generate a plurality of adjusting signals T₁、T₃、…、T_M-1. With this arrangement, the adjusting circuit 134 can analyze the clock signal CLK₁、CLK₃、…、CLK_M-1Time difference information within 2 sampling periods TS.

Please refer to fig. 5A and fig5B, FIGS. 5A and 5B are schematic circuit diagrams of the adjusting circuit of FIG. 4 according to some embodiments of the disclosure. The adjusting circuit 132 is used for performing a statistical operation to determine an even-term quantized output CQ₀、CQ₂、…、CQ_M-2A plurality of corresponding calculation signals (for example, M in FIG. 5A)₀、M₂、…、M_M-2) And averages these calculated signals to generate a reference signal (e.g., REF1 in fig. 5A). The adjusting circuit 132 further compares the reference signal with the plurality of calculation signals to generate the plurality of adjusting signals T₀、T₂、…、T_M-2. The operation of this will be described in detail with reference to fig. 5A in the following paragraphs.

Accordingly, in some embodiments, the adjusting circuit 134 is configured to perform a statistical operation to determine the odd-term quantized output CQ₁、CQ₃、…、CQ_M-1Respectively corresponding multiple calculation signals (for example, M in FIG. 5B)₁、M₃、…、M_M-1) And averages these calculated signals to generate a reference signal (e.g., REF2 in fig. 5B). The adjusting circuit 134 further compares the reference signal with the plurality of calculation signals to generate the plurality of adjusting signals T₁、T₃、…、T_M-1。

In some embodiments, the analog-to-digital conversion circuits 110 can adjust the timing of the sampling operation and/or the analog-to-digital conversion operation according to the adjustment signals T0-TM-1 to equivalently correct the clock skew. The operation of the analog-to-digital conversion circuit 110 is similar to that of the previous embodiment, and is not described herein again.

As shown in fig. 5A, the adjusting circuit 132 includes a delay circuit 207, a plurality of arithmetic circuits 212, an absolute value circuit 222, a statistical circuit 232, an averaging circuit 242, a comparator circuit 252, and a multiplication circuit 262. The operations of the delay circuit 207, the plurality of operation circuits 212, the absolute value circuit 222, the averaging circuit 242, and the comparator circuit 252 are similar to those of the delay circuit 205, the plurality of operation circuits 210, the absolute value circuit 220, the averaging circuit 240, and the comparator circuit 250 of the previous embodiments, and are not repeated herein.

As described above, each of the plurality of statistical circuits 232Coupled to the absolute value circuits 222 for respectively receiving the absolute value signals A₀、A₂、…、A_M-2. Each statistic circuit 230 is used for continuously receiving a plurality of absolute value signals A in a predetermined period ST₀、A₂、…、A_M-2And performing a statistical operation to output a plurality of calculation signals M₀、M₂、…、M_M-2A corresponding one of (1).

In some embodiments, the statistical operation may be a maximum operation or an average operation. Taking the 1 ST statistic circuit 232 as an example, the 1 ST statistic circuit 232 continuously receives the absolute value signal A during the predetermined period ST₀And performing a maximum value operation to output a maximum absolute value signal A received within the predetermined period ST₀For calculating the signal M₀. Alternatively, the 1 ST statistic circuit 232 continuously receives the absolute value signal a for a predetermined period ST₀And performing an averaging operation to average all absolute value signals A received during the predetermined period ST₀For calculating the signal M₀. The setting and operation of the other statistical circuits 232 can be analogized, and thus the description is not repeated.

In some embodiments, the statistical circuit 232 may be implemented by a digital processing circuit, a comparator circuit, and/or a register circuit, but the disclosure is not limited thereto. Various circuits for implementing the statistical circuit 232 are within the scope of the present disclosure.

As noted above, the operation of the multiplication circuit 262 is similar to the multiplication circuit 260. The plurality of multiplication circuits 262 are electrically coupled to the comparison circuit 252 for receiving the plurality of detection signals SD₀、…、SD_M-2. Each multiplication circuit 262 is used for outputting each detection signal SD according to the signal frequency₀、…、SD_M-2Multiplying by a ratio K to generate a corresponding adjusted detection signal TSD₀、…、TSD_M-2。

As mentioned above, the multiplication circuit 262 is used to detect the signal SD when the frequency of the signal is greater than the frequency threshold₀、…、SD_M-2Multiplying the ratio K to generate an adjusted detection signal TSD₀、…、TSD_M-2. In a trueIn an embodiment, the frequency threshold may be implemented as a nyquist frequency. For example, when the frequency of the input signal SIN is greater than the Nyquist frequency, the ratio K is set to-1, so that the adjusted detection signal TSD₀、…、TSD_M-2Negative detection signal SD₀、…、SD_M-2。

As mentioned above, when the signal frequency is less than the frequency threshold (i.e. the frequency of the input signal SIN is less than the nyquist frequency), the ratio K is set to 1, so that the adjusted detection signal TSD₀、…、TSD_M-2And a detection signal SD₀、…、SD_M-2The same is true.

Taking the operation of the 2 nd arithmetic circuit 212 as an example, as shown in FIG. 5A, the adjustment signal T2 is based on the quantized output CQ₀And the quantized output CQ₂The difference between them, the adjustment signal T2 may be used to indicate the quantized output CQ₀Corresponding sample time S1 and quantized output CQ₂Corresponding to the time difference between sampling times S3. The derivation of the difference signal D2 in the time domain is the same as the equation (1), and is not repeated herein.

In some embodiments, the adjusting circuit 132 may further include a plurality of filtering circuits 272 and a plurality of integrating circuits 282. The plurality of filter circuits 272 are respectively coupled to the plurality of multiplier circuits 262 to respectively receive the plurality of adjusted detection signals TSD₀、TSD₂、…、TSD_M-2. The implementation of the filter circuit 272 and the integrator circuit 282 is similar to that of the filter circuit 270 and the integrator circuit 280, and therefore, the detailed description thereof is omitted.

Referring to fig. 5B, as shown in fig. 5B, the adjusting circuit 134 includes a delay circuit 209, a plurality of operation circuits 214, an absolute value circuit 224, a statistic circuit 234, an averaging circuit 244, a comparator circuit 254, and a multiplication circuit 264. The circuit structure of the adjusting circuit 134 is the same as that of the adjusting circuit 132, and the operation method thereof is also similar to that of the adjusting circuit 132, which is not described herein again.

Referring to fig. 6, fig. 6 is a flowchart illustrating a clock skew correction method 600 according to some embodiments of the disclosure. For ease of understanding, the clock skew correction method 600 will be described with reference to the foregoing embodimentsThe drawings are described. In an embodiment, the clock skew correction method 600 first executes step S610 according to the quantized outputs Q generated by the analog-to-digital conversion circuits 110₀～Q_M-1Performing at least one correction operation to generate a plurality of quantized outputs CQ₀～CQ_M-1。

The clock skew correction method 600 then executes step S620 to determine the quantized output CQ through the adjusting circuit 132₀、…、CQ_M-2A plurality of calculation signals M respectively corresponding to the predetermined period ST₀、…、M_M-2Averaging a plurality of calculated signals M₀、…、M_M-2To generate a reference signal REF 1; and determining the quantized output CQ by the skew adjustment circuit 134_-1、…、CQ_M-1A plurality of calculation signals M respectively corresponding to the predetermined period ST₁、…、M_M-1Averaging a plurality of calculated signals M₁、…、M_M-1To generate a reference signal REF 2.

In step S630, the reference signal REF1 is respectively coupled to the plurality of calculation signals M by the adjusting circuit 132₀、…、M_M-2Comparing to generate a plurality of detection signals SD₀、…、SD_M-2(ii) a The reference signal REF2 is respectively connected to a plurality of calculation signals M by the adjusting circuit 134₁、…、M_M-1Comparing to generate a plurality of detection signals SD₁、…、SD_M-1。

In step S640, the adjusting circuit 132 determines whether to adjust the detecting signal SD according to the signal frequency₀、…、SD_M-2To generate a plurality of adjusting signals T₀、…、T_M-2And determining whether to adjust the detection signal SD by the adjusting circuit 134 according to the signal frequency₁、…、SD_M-1To generate a plurality of adjusting signals T₁、…、T_M-1To reduce clock skew in the analog-to-digital conversion circuits 110. The descriptions and the embodiments of the above operations can refer to the descriptions of the above embodiments, and thus the descriptions thereof are not repeated herein.

In summary, the adc device and the clock skew correction method of the present disclosure mainly selectively adjust the detection signal according to the signal frequency, so that when the input signal frequency is greater than the Nyquist frequency (Nyquist frequency), the dac device can still obtain the clock skew information through simple operation for correction. Thus, the overall power consumption and calibration period can be reduced.

Certain terms are used throughout the description and following claims to refer to particular components. However, those of ordinary skill in the art will appreciate that the various elements may be referred to by different names. The specification and claims do not intend to distinguish between components that differ in name but not function. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Further, "coupled" herein includes any direct and indirect connection. Therefore, if a first element is coupled to a second element, the first element may be directly connected to the second element through an electrical connection or a signal connection such as wireless transmission or optical transmission, or may be indirectly connected to the second element through another element or a connection means.

In addition, any reference to singular is intended to include the plural unless the specification specifically states otherwise.

The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.

Claims

1. An analog-to-digital converter apparatus, comprising:

a plurality of analog-to-digital conversion circuits for converting an input signal according to a plurality of interleaved clock signals to generate a plurality of first quantized outputs;

a correction circuit for performing at least one correction operation based on the first quantized outputs to generate a plurality of second quantized outputs; and

a skew adjusting circuit for determining a plurality of calculation signals respectively corresponding to the second quantization outputs in a predetermined period, averaging the calculation signals to generate a reference signal, comparing the reference signal with the calculation signals to generate a plurality of detection signals, and determining whether to adjust the detection signals according to a signal frequency to generate a plurality of adjusting signals, wherein the adjusting signals are used for reducing a clock skew of the analog-to-digital conversion circuits.

2. The ADC apparatus of claim 1 wherein the skew adjustment circuit is further configured to perform a plurality of absolute value operations on a plurality of difference signals to generate a plurality of absolute value signals, respectively, and to perform a plurality of maximum value operations on the plurality of absolute value signals to generate a plurality of maximum value signals, respectively, wherein the difference signals are generated according to the second quantized outputs.

3. The ADC apparatus of claim 1 wherein the skew adjustment circuit is configured to multiply the detection signals by a first ratio to generate the adjustment signals when the frequency of the signal is greater than a frequency threshold.

4. The ADC apparatus of claim 1 wherein the skew adjustment circuit is configured to multiply the detected signals by a second ratio to generate the adjusted signals when the frequency of the signal is less than a frequency threshold.

5. The adc device of claim 2, wherein the skew adjustment circuit comprises:

a delay circuit for delaying a last one of the second quantized outputs to generate a delayed quantized output;

a plurality of operational circuits for receiving the delayed quantized output and the second quantized outputs in sequence, and for generating a plurality of difference signals according to two signals of the delayed quantized output and the second quantized outputs;

a plurality of absolute value circuits, wherein each of the absolute value circuits is configured to perform an absolute value operation according to a corresponding one of the difference signals to generate a corresponding absolute value signal;

a plurality of maximum value circuits, wherein each maximum value circuit is used for receiving a corresponding absolute value signal and executing a maximum value operation to output a corresponding maximum value signal, wherein the corresponding maximum value signal is generated by a maximum value of the corresponding absolute value signal in the preset period;

an averaging circuit for performing an averaging operation to average the maximum value signals to generate the reference signal;

a plurality of comparison circuits for comparing each of the maximum value signals with the reference signal to generate the detection signals; and

the plurality of multiplying circuits are used for multiplying the detection signals by one of a first ratio and a second ratio according to the signal frequency so as to generate the adjusting signals.

6. The analog-to-digital converter device of claim 1, wherein the skew adjustment circuit comprises:

a first adjusting circuit for analyzing even quantized outputs of the second quantized outputs to generate a first portion of the adjusted signals; and

a second adjusting circuit for analyzing odd-numbered quantized outputs of the second quantized outputs to generate a second portion of the adjusting signals.

7. The ADC device of claim 6, wherein the first adjusting circuit is configured to multiply even ones of the detection signals by a first ratio to generate the first portion of the adjusting signals when the signal frequency is greater than a frequency threshold; and the second adjusting circuit is used for multiplying odd detecting signals in the detecting signals by the first ratio to generate the second parts of the adjusting signals.

8. The ADC apparatus of claim 6, wherein the first adjusting circuit is configured to multiply even ones of the detection signals by a second ratio to generate the first portion of the adjusting signals when the signal frequency is less than a frequency threshold; and the second adjusting circuit is used for multiplying odd detection signals in the detection signals by the second ratio to generate the second parts of the adjusting signals.

9. The analog-to-digital converter device of claim 6, wherein the first adjusting circuit further comprises:

a delay circuit for delaying a last one of the even quantized outputs to generate a delayed quantized output;

a plurality of operational circuits for receiving the delayed quantized output and the even-numbered quantized outputs in sequence, and for generating a plurality of difference signals according to two signals of the delayed quantized output and the second quantized outputs, respectively;

a plurality of statistical circuits, wherein each statistical circuit is used for receiving a corresponding absolute value signal in the preset period and executing a statistical operation to output a corresponding calculation signal;

an averaging circuit for performing an averaging operation to average the calculated signals to generate the reference signal;

a plurality of comparison circuits for comparing each of the calculation signals with the reference signal to generate the detection signals; and

a plurality of multiplication circuits for multiplying even ones of the detection signals by one of a first ratio and a second ratio according to the signal frequency to generate the first portions of the adjustment signals.

10. The analog-to-digital converter device of claim 6, wherein the second adjusting circuit further comprises:

a delay circuit for delaying a last one of the odd quantized outputs to generate a delayed quantized output;

a plurality of operational circuits for receiving the delayed quantized output and the odd-numbered quantized outputs in sequence, and for generating a plurality of difference signals according to two signals of the delayed quantized output and the second quantized outputs;

a plurality of multiplication circuits for multiplying odd-numbered detection signals of the detection signals by one of a first ratio and a second ratio according to the signal frequency to generate the second part of the adjustment signals.

11. A method for clock skew correction, comprising:

performing at least one correction operation according to a plurality of first quantized outputs generated by a plurality of analog-to-digital conversion circuits to generate a plurality of second quantized outputs;

determining a plurality of calculation signals respectively corresponding to the second quantization outputs in a preset period through a skew adjusting circuit, and averaging the calculation signals to generate a reference signal;

comparing the reference signal with the calculation signals respectively through the skew adjusting circuit to generate a plurality of detection signals; and

judging whether to adjust the detection signals according to a signal frequency through the deflection adjusting circuit so as to generate a plurality of adjusting signals;

the adjusting signals are used for reducing a clock skew of the analog-digital conversion circuits.

12. The method of claim 11, wherein determining the calculation signals further comprises:

performing a plurality of absolute value operations on a plurality of difference signals to generate a plurality of absolute value signals, wherein the difference signals are generated according to the second quantized outputs; and

a plurality of maximum value operations are respectively performed on the absolute value signals to generate a plurality of maximum value signals.

13. The clock skew correction method of claim 11, wherein the skew adjustment circuit is configured to multiply the detection signals by a first ratio to generate the adjustment signals when the frequency of the signal is greater than a frequency threshold.

14. The clock skew correction method of claim 11, wherein the skew adjustment circuit is configured to multiply the detected signals by a second ratio to generate the adjusted signals when the frequency of the signal is greater than a frequency threshold.

15. The method of claim 12, wherein determining the calculation signals further comprises:

delaying a last one of the second quantized outputs to generate a delayed quantized output;

sequentially receiving the delayed quantized output and the second quantized outputs, and respectively generating a plurality of difference signals according to two signals of the delayed quantized output and the second quantized outputs;

performing an absolute value operation according to a corresponding difference signal of the difference signals to generate a corresponding absolute value signal;

receiving the corresponding absolute value signal in the preset period and executing a maximum value operation to output a corresponding maximum value signal, wherein the corresponding maximum value signal is generated by a maximum value of the corresponding absolute value signal in the preset period;

performing an averaging operation to average the maximum signals to generate the reference signal;

comparing each of the maximum value signals with the reference signal to generate the detection signals; and

the detection signals are multiplied by one of a first ratio and a second ratio according to the signal frequency to generate the adjustment signals.

16. The method of claim 11, wherein generating the adjustment signals comprises:

analyzing even-numbered quantized outputs of the second quantized outputs by a first adjusting circuit to generate a first part of the adjusting signals; and

the odd quantized outputs of the second quantized outputs are analyzed by a second adjusting circuit to generate a second portion of the adjusted signals.

17. The clock skew correction method of claim 16, wherein the first adjusting circuit is configured to multiply even ones of the detection signals by a first ratio to generate the first portion of the adjustment signals when the signal frequency is greater than a frequency threshold; and the second adjusting circuit is used for multiplying odd detecting signals in the detecting signals by the first ratio to generate the second parts of the adjusting signals.

18. The clock skew correction method of claim 16, wherein the first adjustment circuit is configured to multiply even ones of the detection signals by a second ratio to generate the first portion of the adjustment signals when the signal frequency is less than a frequency threshold; and the second adjusting circuit is used for multiplying odd detection signals in the detection signals by the second ratio to generate the second parts of the adjusting signals.

19. The method of claim 16, wherein generating the first portion of the adjustment signals comprises:

delaying a last one of the even numbered quantized outputs to generate a delayed quantized output;

sequentially receiving the delayed quantized output and the even quantized outputs, and respectively generating a plurality of difference signals according to two signals of the delayed quantized output and the second quantized outputs;

receiving corresponding absolute value signals in the preset period, and executing a statistic operation to output corresponding calculation signals;

performing an averaging operation to average the calculated signals to generate the reference signal;

comparing each of the calculated signals with the reference signal to generate the detection signals; and

the even number of the detection signals is multiplied by one of a first ratio and a second ratio according to the signal frequency to generate the first part of the adjustment signals.

20. The method of claim 16, wherein generating the second portion of the adjustment signals comprises:

delaying a last one of the odd quantized outputs to generate a delayed quantized output;

sequentially receiving the delayed quantized output and the odd-numbered quantized outputs, and respectively generating a plurality of difference signals according to two signals of the delayed quantized output and the second quantized outputs;

the odd-numbered detection signals of the detection signals are multiplied by one of a first ratio and a second ratio according to the signal frequency to generate the second part of the adjustment signals.