CN113162445A - Quadruple boosting nine-level switch capacitor inverter and expansion topology thereof - Google Patents

Quadruple boosting nine-level switch capacitor inverter and expansion topology thereof Download PDF

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CN113162445A
CN113162445A CN202110388689.XA CN202110388689A CN113162445A CN 113162445 A CN113162445 A CN 113162445A CN 202110388689 A CN202110388689 A CN 202110388689A CN 113162445 A CN113162445 A CN 113162445A
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switch
capacitor
diode
collector
topology
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CN113162445B (en
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潘健
陈光义
陈庆东
石迪
宋豪杰
熊嘉鑫
刘孙德
刘雨晴
张琦
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Hubei University of Technology
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels

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Abstract

The invention relates to a power electronic technology, in particular to a quadruple boosting nine-level switch capacitor inverter and an expansion topology thereof, wherein the basic unit topology is composed of a direct current source VinA first switch S1A second switch
Figure DDA0003015547250000011
Third switch S2And a fourth switch
Figure DDA0003015547250000012
Fifth switch S3The sixth switch
Figure DDA0003015547250000013
Seventh switch S4The eighth switch
Figure DDA0003015547250000014
Ninth switch S5A first diode D1A second diode D2And a first capacitorDevice C1A second capacitor C2And (4) forming. The topology can realize nine-level output, effectively reduces the volume of the device, improves the power density of the device and saves the cost. By reasonably changing the DC source and the first capacitor C1And a second capacitor C2The series-parallel connection mode can realize the capability of quadruple boosting by the basic unit topology of the nine-level switch capacitor inverter, and an additional boosting circuit is not needed, so that the topological structure is simpler, and the expansion performance is good.

Description

Quadruple boosting nine-level switch capacitor inverter and expansion topology thereof
Technical Field
The invention belongs to the technical field of power electronics, and particularly relates to a four-time boosting nine-level switch capacitor inverter and an expansion topology thereof.
Background
A Multi-Level Inverter (MLI) is widely used in a renewable energy system because of its advantages of low Total Harmonic Distortion (THD), low switching voltage stress, low switching loss, and the need for a small output filter. Classical multilevel inverter topologies include Cascaded H-Bridge (CHB), Neutral Point Clamped (NPC), and Flying Capacitor (FC). However, when the number of operating voltage levels exceeds 3, the three conventional multi-level inverters have the problems of voltage imbalance and more components. And three conventional multilevel inverters do not have boost capability, generally renewable energy sources such as photovoltaic and fuel cells are provided in the form of low voltage power sources. The traditional solutions are of two kinds: one boosting scheme is to connect multiple photovoltaic modules in series into a high voltage string, and many mismatch problems have been encountered at present; another solution is to cascade the front-end DC-DC boost converter with the back-end conventional MLI. This increases complexity and reduces efficiency.
The use of integrated boost technology based on switched capacitors has been widely studied as a new approach to solving the above-mentioned problems. At the same time, scalability of the multilevel inverter is an important property thereof. Especially in high-power application occasions, the switching frequency of the inverter is limited due to the limitation of the material and the process level of power electronic devices, so that the quality of output electric energy is reduced. There are two solutions in MLI: one solution is to increase the switching frequency by reducing the maximum voltage stress experienced across each switching device of the MLI, achieving high power quality output. However, this approach has high requirements for MLI topology, requiring that the maximum voltage stress across all high frequency switching devices cannot exceed the rating for safe operation of the switching devices. Also, this solution increases the switching frequency, which means an increase in switching losses. Another effective solution is to increase the number of output levels. Through a Nearest Level Control technology (near Level Control Methods), the output bus voltage presents step waves, high-frequency switching of two levels is not needed, the switching frequency only needs hundreds of hertz, and the number of the step waves is determined by the number of the levels. However, an increase in the number of output levels necessarily increases the number of inverter components, which increases the inverter size and decreases efficiency.
Disclosure of Invention
In view of the problems in the background art, the present invention provides a basic unit topology structure of a nine-level switch capacitor inverter, which aims to reduce the number of switches, improve the output voltage gain, and improve the expansion performance.
In order to solve the technical problems, the invention adopts the following technical scheme: a basic unit topology of nine-level switch capacitor inverter is composed of a DC source VinA first switch S1A second switch
Figure BDA0003015547230000021
Third switch S2And a fourth switch
Figure BDA0003015547230000022
Fifth switch S3Sixth, openingClosing device
Figure BDA0003015547230000023
Seventh switch S4The eighth switch
Figure BDA0003015547230000024
Ninth switch S5A first diode D1A second diode D2And a first capacitor C1A second capacitor C2Composition is carried out; first switch S1Emitter and second switch
Figure BDA0003015547230000025
Is connected to the collector of the second switch
Figure BDA0003015547230000026
Emitter and fourth switch
Figure BDA0003015547230000027
Emitter electrode of (1), first capacitor C1Negative electrode of (1), first diode D1And a second diode D2Is connected to the cathode of the first switch S1Collector and third switch S2Collector, fifth switch S3Collector and second capacitor C2Is connected to the positive pole of the fifth switch S3Emitter and eighth switch
Figure BDA0003015547230000028
Is connected to the collector of a second capacitor C2Negative electrode of (2) and sixth switch
Figure BDA0003015547230000029
Emitter and ninth switch S5Is connected to the collector of the ninth switch S5And the second diode D2Is connected to the anode of the seventh switch S4Collector and first capacitor C1Positive electrode and eighth switch
Figure BDA00030155472300000210
Of the emitterConnecting; DC source VinPositive pole and sixth switch
Figure BDA00030155472300000211
Is connected with a DC source VinCathode and first diode D1Cathode connected to a fifth switch S3Emitter and fourth switch
Figure BDA00030155472300000215
The collector electrodes of (a) are connected by a wire.
An extended topology of a nine-level switched capacitor inverter base cell topology in which the number of voltage levels is increased by cascading a plurality of base cells; the connection mode of cascading a basic unit is as follows: a first capacitor C of a first-stage nine-level switch capacitor inverter1Negative electrode of (1), first diode D1Anode and second switch
Figure BDA00030155472300000213
Emitter electrode of, second diode D2The tenth switch S of the second-stage nine-level switch capacitor inverter is addedd1Collector and eighth switch
Figure BDA00030155472300000214
And a seventh switch S4Is connected to the collector of the eleventh switch Sd2Collector and tenth switch Sd1Is connected to an eleventh switch Sd2Emitter of (2) and first capacitor C1Negative electrode of (2) and first diode D1Anode of (2), third diode Dd1Is connected to the cathode of a third diode Dd1Cathode and eleventh switch Sd2Is connected to the emitter of a third diode Dd1Anode and third capacitor Cd1Is connected to the negative pole of a third capacitor Cd1Positive pole of (2) and tenth switch Sd1Emitter and eleventh switch Sd2Is connected with the collector of the first switch, and the cathode of the first switch is connected with the second switch
Figure BDA00030155472300000212
The emitting electrodes are connected; and the connection mode of cascading a plurality of basic units is similar.
In the extended topology of the basic unit topology of the nine-level switch capacitor inverter, the number of the switches of the extended topology is NSWThe number of capacitors NCNumber of diodes NdThe relational expression with the number of levels N is:
Figure BDA0003015547230000031
as can be seen from equation (1), the output voltage v is obtained for every 2 switches, 1 capacitor and 1 diodebusThe number of levels is increased by 4.
Compared with the prior art, the invention has the beneficial effects that:
(1) the basic unit topology of the nine-level switch capacitor inverter only needs one direct-current voltage source, two capacitors, two diodes and nine power switches, so that nine-level output can be realized, the size of the device is effectively reduced, the power density of the device is improved, and the cost is saved.
(2) By using the principle of switched capacitor, the DC source and the first capacitor C are reasonably changed1And a second capacitor C2The series-parallel connection mode can realize the capability of quadruple boosting by the basic unit topology of the nine-level switch capacitor inverter, and an additional boosting circuit is not needed, so that the topological structure is simpler.
(3) The expansion performance is good, and on the basis of the basic unit topology of the nine-level switch capacitor inverter, the output voltage v is output every time 2 switches, 1 capacitor and 1 power diode are addedbusThe number of levels is increased by 4.
(4) In a nine-level switched capacitor inverter basic cell topology, a first capacitor C1And a second capacitor C2Realize charge-discharge balance, and the first capacitor C1The charge and discharge are carried out alternately at the highest level and the next highest level, so that the problem of continuous attenuation of the voltage at two ends of the capacitor is optimized.
(5) Nine-level switch capacitor9 switches of the inverter base cell topology, switch SiHas the following advantages
Figure BDA0003015547230000032
The complementary operation of (2) simplifies the switch control. And a first switch S1And a second
Figure BDA0003015547230000033
Operating at low frequencies further reduces switching losses.
Drawings
FIG. 1 is a schematic diagram of a basic cell topology of a nine-level switched capacitor inverter according to an embodiment of the present invention;
FIG. 2 is an expanded topology structure diagram of a nine-level switched capacitor inverter based base cell topology according to an embodiment of the present invention;
FIG. 3-1 is a topology diagram of a nine-level switched capacitor inverter base cell topology in a first operating state A in accordance with an embodiment of the present invention;
3-2 is a topology diagram of a nine-level switched capacitor inverter base cell topology in a second operating state B in accordance with one embodiment of the present invention;
3-3 are topology diagrams of a nine level switched capacitor inverter base cell topology in a third operating state C in accordance with one embodiment of the present invention;
3-4 are topology diagrams of a nine level switched capacitor inverter base cell topology in a fourth operating state D in accordance with an embodiment of the present invention;
3-5 are topology diagrams of a nine-level switched capacitor inverter base cell topology in a fifth operating state E in accordance with an embodiment of the present invention;
FIG. 4-1 shows a nine-level switched capacitor inverter basic cell topology at resistive load (Z) according to an embodiment of the present invention 150 Ω), bus voltage VbusAn output voltage VoutAnd an output current ioutThe simulated waveform of (2);
FIG. 4-2 shows a nine-level switched capacitor inverter base unit topology with inductive load (Z) according to an embodiment of the present invention 250 Ω +100mH), the bus voltage VbusAn output voltage VoutAnd an output current ioutThe simulated waveform of (2);
4-3 illustrate a nine-level switched capacitor inverter base unit topology with inductive load Z according to one embodiment of the present invention2Lower, bus voltage VbusVoltage V of switch capacitor C1, C2C1And VC2The simulated waveform of (2);
FIGS. 4-4 illustrate a nine-level switched capacitor inverter base unit topology with inductive load Z according to an embodiment of the present invention2Lower, bus voltage vbusThe FFT simulation waveform of (2);
FIGS. 4-5 illustrate a nine-level switched capacitor inverter base unit topology with inductive load Z according to one embodiment of the present invention2When the modulation factor M is changed from 0.2 to 1, the bus voltage VbusAn output voltage VoutAnd an output current ioutThe simulated waveform of (2);
FIGS. 4-6 illustrate a nine-level switched capacitor inverter base unit topology with no load step change to an inductive load Z2Time, bus voltage VbusAn output voltage VoutAnd an output current ioutThe simulated waveform of (2);
FIG. 5-1 is a hardware experimental platform of a basic unit topology of a nine-level switched capacitor inverter according to an embodiment of the present invention;
5-2(a) is a nine-level switched capacitor inverter basic cell topology at resistive load (Z) according to an embodiment of the present invention 345 Ω), bus voltage VbusAn output voltage VoutAnd an output current ioutThe experimental waveform of (2);
5-2(b) is a nine-level switched capacitor inverter basic cell topology at resistive load (Z) in accordance with one embodiment of the present invention 345 Ω), bus voltage VbusVoltage V of switch capacitor C1, C2C1And VC2The experimental waveform of (2);
5-3(a) are nine-level switched capacitor inverter base cell topologies at resistive load (Z) according to one embodiment of the present invention 345 Ω) when the modulation ratio M changes from 0.2 to 0.6, the bus voltage V is increasedbusAn output voltage VoutOfTesting a waveform;
5-3(b) are nine-level switched capacitor inverter base cell topologies at resistive load (Z) according to one embodiment of the present invention 345 Ω) when the modulation ratio M is changed from 0.9 to 0.4, the bus voltage V is increasedbusAn output voltage VoutThe experimental waveform of (2);
5-4 are nine-level switched capacitor inverter base cell topologies going from no load step to load (Z) according to one embodiment of the present invention 345 Ω), bus voltage VbusAn output voltage VoutAnd an output current ioutExperimental waveforms of (4).
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the following embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The present invention is further illustrated by the following examples, which are not to be construed as limiting the invention.
The basic unit topology of the nine-level switch capacitor inverter of the embodiment only uses 9 switches to realize nine-level voltage output with four times of voltage gain, and can be used as a conventional multi-level inverter. In addition, the basic unit topology has good expansibility, and higher level number can be expanded and output only by adding a small number of components.
As shown in fig. 1, the basic unit topology of the nine-level switched capacitor inverter is composed of a dc source, nine switches, two diodes and two switched capacitors. First switch S1Emitter and second switch
Figure BDA0003015547230000051
Is connected to the collector of the second switch
Figure BDA0003015547230000052
Emitter and fourth switch
Figure BDA0003015547230000053
Emitter electrode of (1), first capacitor C1Negative electrode of (1), first diode D1And a second diode D2Is connected to the cathode of the first switch S1Collector and second switch S2Collector, fifth switch S3Collector and second capacitor C2Is connected to the positive pole of the fifth switch S3Emitter and eighth switch
Figure BDA0003015547230000054
Is connected to the collector of the second capacitor C2, and the negative pole of the second capacitor C2 is connected to the sixth switch
Figure BDA0003015547230000055
Emitter and ninth switch S5Is connected to the collector of the ninth switch S5And the second diode D2Is connected to the anode of the seventh switch S4With the positive pole of the first capacitor C1 and an eighth switch
Figure BDA0003015547230000056
Are connected. DC source VinPositive pole and sixth switch
Figure BDA0003015547230000057
Is connected with a DC source VinCathode and first diode D1Cathode, emitter of the fifth switch S3 and the sixth switch
Figure BDA0003015547230000058
The collector electrodes of (a) are connected by a wire.
As shown in FIG. 2, the topology is an extended topology structure of the basic unit topology of the nine-level switch capacitor inverter, in which a plurality of basic units can be cascadedTo increase the number of voltage levels. A first capacitor C1Negative electrode of (1), first diode D1Anode and second switch
Figure BDA0003015547230000062
Emitter electrode of, second diode D2Is open, the tenth switch S is addedd1Collector and eighth switch
Figure BDA0003015547230000063
And a seventh switch S4Is connected to the collector of the eleventh switch Sd2Collector and tenth switch Sd1Is connected to an eleventh switch Sd2Emitter of (2) and first capacitor C1Negative electrode of (2) and first diode D1Anode of (2), third diode Dd1Is connected to the cathode of a third diode Dd1Cathode and eleventh switch Sd2Is connected to the emitter of a third diode Dd1Anode and third capacitor Cd1Is connected to the negative pole of a third capacitor Cd1Positive pole of (2) and tenth switch Sd1Emitter and eleventh switch Sd2Is connected with the collector of the first switch, and the cathode of the first switch is connected with the second switch
Figure BDA0003015547230000064
Are connected. The device connection of the cascade extension is similar to that described above.
The embodiment simultaneously gives the switch number N of the extended topologySWThe number of capacitors NCNumber of power diodes NdA relational expression with the number N of levels.
Figure BDA0003015547230000061
The relational expression of the quantity of the switches, the capacitors and the diodes and the quantity of the levels in the expanded circuit can be obtained by the formula (1). According to their relationship, the output voltage v is increased every 2 switches, 1 capacitor and 1 power diodebusThe number of levels is increased by 4.The basic unit nine-level inverter is proved to have good expansion performance.
In specific implementation, fig. 1 is a schematic diagram of a basic unit topology of the nine-level switched capacitor inverter provided in this embodiment. Only one DC source is needed to realize the bus voltage VbusAnd (4) four times boosting nine-level output. As shown in FIG. 1, the topology is composed of a DC source VinA first, a second, a third, a fourth, a fifth, a sixth, a seventh and an eighth switch tube S1,
Figure BDA0003015547230000065
S2、
Figure BDA0003015547230000066
S3、
Figure BDA0003015547230000067
S4、
Figure BDA0003015547230000068
S5, first diode D1A second diode D2And first and second switched capacitors C1、C2And (4) forming. The output performance of the high-power-density and high-performance nine-level inverter of the embodiment is verified by adopting a simple LC filter circuit in a simulation experiment. Z is a load part, and the reactive power regulation capability of the embodiment is verified under two load conditions, namely a resistive load Z 150 omega, inductive load Z2＝50Ω+100mH。VoutIs an alternating voltage on the load Z, ioutIs the output ac current flowing through the load Z. Under resistive load Z3Experimental verification was performed under 45 Ω.
Table 1 shows the switching states of the nine-level inverter with high power density and high performance in each level, where "0" indicates that the switch is turned off and "1" indicates that the switch is turned on. Fig. 3-1 to 3-5 show the current paths in the positive half cycle in each case, respectively. All power devices are ideal, and the on-resistance and the forward voltage drop of the power devices are zero; the capacitance of the two capacitors is sufficiently large; the designed inverter has entered steady stateAnd the capacitor voltage is at VC1＝VinAnd VC2＝2VinIs constant.
TABLE 1 switching patterns and capacitor states at each voltage level
Figure BDA0003015547230000071
And a state A: as can be seen from Table 1 and FIGS. 3-1, in state A, the first and second capacitors C1、C2And a power supply VinDischarge in series, they share the same discharge current. At this time, the bus voltage vbusIs that
Vbus＝VC1+Vin+VC2＝4Vin (2)
And a state B: in state B shown in FIG. 3-2, the first capacitor C1And a power supply VinAre charged in parallel, so that the first capacitor C1And a power supply VinAre equal. A second capacitor C2And a power supply VinAnd discharging in series. At this time, the bus voltage vbusIs that
VC1＝Vin (3)
vbus＝Vin+VC2＝3Vin (4)
And C, state C: in the state C shown in FIGS. 3-3, the first capacitor C1And a power supply VinAfter being connected in series, the load and a second capacitor C2And (5) supplying power. At this time, the bus voltage vbusIs that
VC2＝VC1+Vin＝2Vin (5)
vbus＝VC1+Vin＝2Vin (6)
And a state D: in the state D shown in Figs. 3-4, the first capacitor C1And a power supply VinAnd charging in parallel to satisfy formula (3). A second capacitor C2Does not participate in the charging and discharging process, and maintains the voltage state of the previous moment unchanged.
At this time, the bus voltage vbusIs that
vbus＝Vin (7)
And a state E: in the state E shown in FIGS. 3-5, the first capacitor C1And a power supply VinAfter being connected in series, is a second capacitor C2And (5) charging to satisfy the formula (5). At this time, the bus voltage vbusIs that
vbus＝0 (8)
Simulink simulations were performed to verify the performance of the proposed basic cell nine level inverter. The simulation parameters are shown in table 2.
TABLE 2 topology simulation verification parameters of nine-level switch capacitor inverter basic unit
Figure BDA0003015547230000081
FIGS. 4-1 and 4-2 show the pure resistive load Z1And an inductive load Z2And (3) a simulation waveform diagram of the lower bus voltage, the output voltage and the output current. The 50V voltage is selected as the dc input, which results in the first capacitor C1And a second capacitor C2The voltages across the terminals were 50V and 100V, respectively. The resulting nine-level output voltage has a peak value of 200V. Wherein the inductive load Z2Lower first capacitor C1And a second capacitor C2The dc voltage across is shown in fig. 4-3. The simulated waveform is consistent with the analysis condition.
At a load Z2Lower bus voltage vbusThe FFT analysis of (a) is shown in fig. 4-4. It can be seen that the odd order harmonics are attenuated considerably compared to the fundamental frequency component, which has the same frequency as the output voltage. I.e., low THD, is obtained by the nine-stage inverter described herein with fewer components. Fig. 4-4, on the other hand, show bus voltage vbusThe THD of (B) was 16.89%.
FIGS. 4-5 illustrate the proposed base unit topology under inductive load Z2A dynamically varying waveform of the lower modulation index M. With the gradual increase of the modulation index from 0.2 to 1, the power quality of the output voltage and current waveform is improved. Moreover, when the modulation index M is dynamically changed, the dynamic performance of the modulation index M is not reduced.
Fig. 4-6 show the proposed basic cell topology, the critical waveform case in case of sudden load. FIGS. 4-6 are graphs from no-load jump to inductive load Z2Bus voltage v under circumstancesbusOutput voltage voutAnd an output current ioutThe output voltage is stable and unchanged under the condition of sudden load, and the output current can be smoothly transited.
To further verify the feasibility of the nine-level switched capacitor inverter base cell topology, an experimental prototype as shown in fig. 9 was employed. The experimental circuit parameters and equipment specifications are shown in table 3.
TABLE 3 topology experiment verification parameters of nine-level switch capacitor inverter basic unit
Figure BDA0003015547230000091
The control of the system is realized by a single chip microcomputer of STM32H750VBT6 model, the voltage of the direct current side of the system is 50V, and the modulation index is 0.9. A pure resistive load with the load of 45 omega is adopted, the filter inductor is self-wound, the size of the filter inductor is 1.1mH, the filter capacitor is 8 muF, the switching frequency is 10kHz, and the output fundamental wave frequency is 50 Hz.
As shown in fig. 5-2(a), under purely resistive load, the output voltage sum has the same output phase. 5-2(b) shows the DC voltage waveform diagrams at two ends of the main circuit, the experimental condition and the simulation are completely consistent, and the voltage fluctuation is small.
Fig. 5-3 show experimental results when the modulation index is dynamically changed. When the modulation index is increased from 0.2 to 0.6 in fig. 5-3(a), the output bus voltage is transited from 3-level output to 7-level output, and the dynamic performance of the transition is good. Fig. 5-3(b) shows a dynamic change of modulation index from 0.9 to 0.4, where the output bus voltage transitions from a 9-level output to a 5-level output corresponding to a level, and the output waveform remains stable as the output level decreases. Fig. 5-4 show experimental results for the basic cell nine-level switched capacitor inverter described herein under sudden load changes. When the load is suddenly applied, the experimental waveform is consistent with the simulation.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims (3)

1. A basic unit topology of a nine-level switch capacitor inverter is characterized in that a direct current source (V)in) A first switch (S)1) A second switch
Figure FDA0003015547220000011
Third switch (S)2) And a fourth switch
Figure FDA0003015547220000012
Fifth switch (S)3) The sixth switch
Figure FDA0003015547220000013
Seventh switch (S)4) The eighth switch
Figure FDA0003015547220000014
Ninth switch (S)5) A first diode (D)1) A second diode (D)2) And a first capacitor (C)1) A second capacitor (C)2) Composition is carried out; a first switch (S)1) Emitter and second switch
Figure FDA0003015547220000015
Is connected to the collector of the second switch
Figure FDA0003015547220000016
And an emitter electrode ofThe fourth switch
Figure FDA0003015547220000017
Emitter electrode, first capacitor (C)1) Negative electrode of (D), first diode (D)1) And a second diode (D)2) Is connected to the cathode of the first switch (S)1) Collector and third switch (S)2) Collector electrode of (1), fifth switch (S)3) Collector and second capacitor (C)2) Is connected to the positive pole of the fifth switch (S)3) Emitter and eighth switch
Figure FDA0003015547220000018
Is connected to the collector of a second capacitor (C)2) Negative electrode of (2) and sixth switch
Figure FDA0003015547220000019
Emitter and ninth switch (S)5) Is connected to the collector of the ninth switch (S)5) And a second diode (D)2) Is connected to the anode of the seventh switch (S)4) Collector and first capacitor (C)1) Positive electrode and eighth switch
Figure FDA00030155472200000110
The emitting electrodes are connected; DC source (V)in) Positive pole and sixth switch
Figure FDA00030155472200000111
Is connected with a DC source (V)in) A cathode and a first diode (D)1) Cathode connected to a fifth switch (S)3) Emitter and fourth switch
Figure FDA00030155472200000112
The collector electrodes of (a) are connected by a wire.
2. The extended topology of nine level switch capacitor inverter base cell topology of claim 1, wherein switching at nine levelsThe number of voltage levels is increased in the capacitive inverter basic unit by cascading a plurality of basic units; the connection mode of cascading a basic unit is as follows: a first capacitor (C) of a first-stage nine-level switch capacitor inverter1) Negative electrode of (D), first diode (D)1) Anode and second switch
Figure FDA00030155472200000113
Emitter of (D), second diode (D)2) The tenth switch (S) of the second stage nine-level switch capacitor inverter is addedd1) Collector and eighth switch
Figure FDA00030155472200000114
And a seventh switch (S)4) Is connected to the collector of the eleventh switch (S)d2) Collector and tenth switch (S)d1) Is connected to the emitter of the eleventh switch (S)d2) Emitter and first capacitor (C)1) Negative electrode of (D) and first diode (D)1) Anode of (D), third diode (D)d1) Is connected to the cathode of a third diode (D)d1) And the eleventh switch (S)d2) Is connected to a third diode (D)d1) Anode and third capacitor (C)d1) Is connected to the negative pole of the third capacitor (C)d1) Positive electrode of (2) and tenth switch (S)d1) Emitter and eleventh switch (S)d2) Is connected with the collector of the first switch, and the cathode of the first switch is connected with the second switch
Figure FDA00030155472200000115
The emitting electrodes are connected; and the connection mode of cascading a plurality of basic units is similar.
3. The extended topology of nine-level switched capacitor inverter base cell topology of claim 2, wherein the number of switches of the extended topology is NSWThe number of capacitors NCNumber of diodes NdThe relational expression with the number of levels N is:
Figure FDA0003015547220000021
as can be seen from equation (1), the voltage (v) is output for every 2 switches, 1 capacitor, and 1 diodebus) The number of levels is increased by 4.
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WO2019204935A1 (en) * 2018-04-25 2019-10-31 Ecole De Technologie Superieure Voltage level multiplier module for multilevel power converters
CN111130371A (en) * 2020-01-21 2020-05-08 湖北工业大学 Nine level dc-to-ac converter of 2 times step up based on switched capacitor
CN111628668A (en) * 2020-06-09 2020-09-04 华东交通大学 Nine-level inverter adopting asymmetric voltage source
US10965221B1 (en) * 2020-09-01 2021-03-30 King Abdulaziz University Switched capacitor based boost inverter topology with a higher number of levels and higher voltage gain
CN114629368A (en) * 2022-03-10 2022-06-14 西南交通大学 Nine level dc-to-ac converter of switched capacitor high gain

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019204935A1 (en) * 2018-04-25 2019-10-31 Ecole De Technologie Superieure Voltage level multiplier module for multilevel power converters
CN111130371A (en) * 2020-01-21 2020-05-08 湖北工业大学 Nine level dc-to-ac converter of 2 times step up based on switched capacitor
CN111628668A (en) * 2020-06-09 2020-09-04 华东交通大学 Nine-level inverter adopting asymmetric voltage source
US10965221B1 (en) * 2020-09-01 2021-03-30 King Abdulaziz University Switched capacitor based boost inverter topology with a higher number of levels and higher voltage gain
CN114629368A (en) * 2022-03-10 2022-06-14 西南交通大学 Nine level dc-to-ac converter of switched capacitor high gain

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