CN113162376B - Pulse frequency control circuit, control system and control method thereof - Google Patents
Pulse frequency control circuit, control system and control method thereof Download PDFInfo
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- CN113162376B CN113162376B CN202010074125.4A CN202010074125A CN113162376B CN 113162376 B CN113162376 B CN 113162376B CN 202010074125 A CN202010074125 A CN 202010074125A CN 113162376 B CN113162376 B CN 113162376B
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- 238000000034 method Methods 0.000 title claims abstract description 11
- 238000006243 chemical reaction Methods 0.000 claims abstract description 26
- 239000003990 capacitor Substances 0.000 claims description 20
- 238000001514 detection method Methods 0.000 claims description 17
- 238000007599 discharging Methods 0.000 claims description 3
- 238000003491 array Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 12
- 101100033865 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RFA1 gene Proteins 0.000 description 5
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- 102100029469 WD repeat and HMG-box DNA-binding protein 1 Human genes 0.000 description 5
- 101710097421 WD repeat and HMG-box DNA-binding protein 1 Proteins 0.000 description 5
- 101100219315 Arabidopsis thaliana CYP83A1 gene Proteins 0.000 description 4
- 101000806846 Homo sapiens DNA-(apurinic or apyrimidinic site) endonuclease Proteins 0.000 description 4
- 101000835083 Homo sapiens Tissue factor pathway inhibitor 2 Proteins 0.000 description 4
- 101100269674 Mus musculus Alyref2 gene Proteins 0.000 description 4
- 101100140580 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) REF2 gene Proteins 0.000 description 4
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- HCUOEKSZWPGJIM-YBRHCDHNSA-N (e,2e)-2-hydroxyimino-6-methoxy-4-methyl-5-nitrohex-3-enamide Chemical compound COCC([N+]([O-])=O)\C(C)=C\C(=N/O)\C(N)=O HCUOEKSZWPGJIM-YBRHCDHNSA-N 0.000 description 3
- 101001109689 Homo sapiens Nuclear receptor subfamily 4 group A member 3 Proteins 0.000 description 3
- 101000598778 Homo sapiens Protein OSCP1 Proteins 0.000 description 3
- 101001067395 Mus musculus Phospholipid scramblase 1 Proteins 0.000 description 3
- 102100022673 Nuclear receptor subfamily 4 group A member 3 Human genes 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 230000001105 regulatory effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R1/00—Details of transducers, loudspeakers or microphones
- H04R1/20—Arrangements for obtaining desired frequency or directional characteristics
- H04R1/22—Arrangements for obtaining desired frequency or directional characteristics for obtaining desired frequency characteristic only
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- Health & Medical Sciences (AREA)
- Otolaryngology (AREA)
- Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
A pulse frequency control circuit, a control system and a control method. The pulse frequency control circuit comprises a first comparison circuit, a second comparison circuit, a gear switching circuit, a slope judging circuit and a trigger circuit. The first comparison circuit is used for outputting a first signal according to the output voltage of the power conversion circuit. The gear switching circuit is used for outputting a gear switching signal according to the output current of the power supply switching circuit. The slope determination circuit is used for outputting a slope modulation voltage and determining whether the slope modulation voltage has a first slope or a second slope according to the gear switching signal. The second comparison circuit is used for outputting a second signal according to the slope modulation voltage. The trigger circuit is used for outputting a control signal to the power conversion circuit according to the first signal and the second signal. When the slope modulation voltage has a first or second slope, the control signal has a first or second frequency, respectively. The first frequency is higher than the second frequency.
Description
Technical Field
The present disclosure relates to a pulse frequency control circuit, a control system, and a control method thereof, and more particularly, to a pulse frequency control circuit, a control system, and a control method thereof for reducing noise.
Background
With the development of technology, portable electronic devices (e.g., wireless bluetooth headset and mobile phone) having Audio Codec (Audio Codec) or Audio amplifier (Audio Amp) circuit have been widely used in daily life.
When these devices are operated in a power saving mode, the power supply circuit typically uses pulse frequency modulation (Pulse frequency modulation, PFM) to reduce overall power consumption to extend the standby time of the device. And when the audio circuit in the device is loaded small and low in power, noise spurs may be caused to enter low frequencies, which in turn may cause discomfort to the human ear.
Therefore, how to reduce noise bursts is an important issue in the art.
Disclosure of Invention
An embodiment of the present disclosure relates to a pulse frequency control circuit including a first comparison circuit, a gear switching circuit, a slope determination circuit, a second comparison circuit, and a trigger circuit. The first comparison circuit is used for outputting a first signal according to the output voltage of the power conversion circuit. The gear switching circuit is used for outputting a gear switching signal according to the output current of the power supply switching circuit. The slope determination circuit is used for outputting a slope modulation voltage and determining whether the slope modulation voltage has a first slope or a second slope according to the gear switching signal. The second comparison circuit is used for outputting a second signal according to the slope modulation voltage. The trigger circuit is used for outputting a control signal to the power conversion circuit according to the first signal and the second signal. When the slope modulation voltage has a first slope, the control signal has a first frequency, and when the slope modulation voltage has a second slope, the control signal has a second frequency, the first frequency being higher than the second frequency.
An embodiment of the present disclosure relates to a pulse frequency control system including a power conversion circuit and a pulse frequency control circuit. The power conversion circuit is used for charging and discharging the load according to the control signal so as to generate an output signal. The pulse frequency control circuit comprises a first comparison circuit, a gear switching circuit, a slope judging circuit, a second comparison circuit and a trigger circuit. The first comparison circuit is used for outputting a first signal according to the output voltage of the output signal. The gear switching circuit is used for outputting a gear switching signal according to the output current of the output signal. The slope determination circuit is used for outputting a slope modulation voltage and determining whether the slope modulation voltage has a first slope or a second slope according to the gear switching signal. The second comparison circuit is used for outputting a second signal according to the slope modulation voltage. The trigger circuit is used for outputting a control signal to the power conversion circuit according to the first signal and the second signal.
Another embodiment of the present disclosure relates to a pulse frequency control method including: the pulse frequency control circuit outputs a control signal; the power supply conversion circuit charges and discharges the load according to the control signal so as to generate an output signal; judging whether a load connected with the power conversion circuit is in light load or not according to the output signal, and judging whether the frequency of the control signal is lower than that of the low-frequency square wave signal or not; when the load is in light load and the frequency of the control signal is lower than that of the low-frequency square wave signal, the capacitor array of the pulse frequency control circuit is switched to a first capacitance value to generate the control signal with a first frequency; and when the load is not in light load or the frequency of the control signal is not lower than the frequency of the low-frequency square wave signal, switching the capacitor array of the pulse frequency control circuit to a second capacitance value to generate the control signal with the second frequency, wherein the first capacitance value is smaller than the second capacitance value, and the first frequency is higher than the second frequency.
Drawings
Fig. 1 is a schematic diagram of a pulse frequency control system according to an embodiment of the present disclosure.
Fig. 2 is a schematic diagram of a pulse frequency control circuit according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram of a portion of a specific circuit of the embodiment of fig. 2 according to the present disclosure.
Fig. 4 is a schematic diagram of signal waveforms of the embodiment of fig. 3 according to the present disclosure.
Fig. 5 is a flowchart of a pulse frequency control method according to an embodiment of the present disclosure.
Fig. 6 is a schematic diagram of another portion of the embodiment of fig. 2 according to the present disclosure.
Fig. 7 is a schematic diagram of signal waveforms of the embodiment of fig. 6 according to the present disclosure.
Symbol description
900: Pulse frequency control system
100: Pulse frequency control circuit
200: Power supply conversion circuit
110. 120: Comparison circuit
130: Trigger circuit (flip-flop circuit)
140: Slope determination circuit
150: Gear switching circuit
BUF1, BUF2: buffer circuit
M1, M2, M3, M4: switch
Lx: inductance
Cx, C0, C1, C2, C3: capacitance device
VCC: high system voltage
CS: control signal
PG, NG: delay signal
Iout: output current
Vout: output voltage
LHZ: low frequency signal
ZCD: detecting a signal
CCOT: gear shift signal
REF1, REF2: reference signal
VC: slope modulated voltage
SET: first signal
RE: second signal
COMP1, COMP2: comparison amplifier
NOR1, NOR2: NOR gate (NOR gate)
IS: current source
EN: enable signal
SW [0] to SW [3]: switch
P1 to P4, T1 to T6: during the period of time
500: Pulse frequency control method
S510, S520, S530, S540: operation of
151: Detection circuit
FF1, FF2, FF3: trigger device
AND1, AND2: AND gate (AND gate)
HV: high reference voltage
ENL: low frequency enable signal
Q1, R1, QB2, R2: discriminating signal
Detailed Description
The following detailed description of the embodiments is provided in conjunction with the accompanying drawings, but the specific embodiments described are merely illustrative of the disclosure and not intended to limit the disclosure, and the description of the structure operations is not intended to limit the order in which the operations may be performed, and any arrangement of elements that may be rearranged to produce a result with equivalent technical results is within the scope of the disclosure.
Please refer to fig. 1. Fig. 1 is a schematic diagram of a pulse frequency control system 900 according to an embodiment of the present disclosure. As shown in fig. 1, the pulse frequency control system 900 includes a pulse frequency control circuit 100, buffer circuits BUF1 and BUF2, and a power conversion circuit 200. The pulse frequency control circuit 100 is connected to the power conversion circuit 200 through buffer circuits BUF1 and BUF2. Specifically, the pulse frequency control circuit 100 outputs the control signal CS to the buffer circuits BUF1 and BUF2. The buffer circuits BUF1 and BUF2 generate delay signals PG and NG, respectively, to the power conversion circuit 200 according to the control signal CS.
In some embodiments, the power conversion circuit 200 may be implemented by a Buck Converter (Buck Converter). As shown in fig. 1, the power conversion circuit 200 includes an inductance Lx, a capacitance Cx, and switches M1 and M2. Specifically, a first terminal of the switch M1 is connected to the system high voltage VCC. The control terminal of the switch M1 receives the delay signal PG. The second terminal of the switch M1 and the first terminal of the switch M2 are connected to the first terminal of the inductance Lx. The control terminal of the switch M2 receives the delay signal NG. The second terminal of the switch M2 is grounded. The second terminal of the inductance Lx is connected to the first terminal of the capacitance Cx. The second terminal of the capacitance Cx is grounded.
In operation, when the control signal CS is at a low level, the delay signals PG and NG are also at a low level, so that the switch M1 is turned on and the switch M2 is turned off, to provide the system high voltage VCC to the inductor Lx, the capacitor Cx and the back-end load (not shown) for charging. When the control signal CS is at a high level, the delay signals PG and NG are also at a high level, so that the switch M1 is turned off and the switch M2 is turned on to ground the inductor Lx, the capacitor Cx and the rear load for discharging.
In this way, the power conversion circuit 200 can charge and discharge the load by the level of the control signal CS to generate the output signal (i.e. the output current Iout and the output voltage Vout in fig. 1). Further, the pulse frequency control circuit 100 receives the control signal CS, the delay signals PG and NG, the output current Iout, and the output voltage Vout, and performs feedback control based on these signals.
Please refer to fig. 2. Fig. 2 is a schematic diagram of a pulse frequency control circuit 100 according to an embodiment of the present disclosure. As shown in fig. 2, the pulse frequency control circuit 100 includes comparison circuits 110 and 120, a flip-flop circuit 130, a slope determination circuit 140, and a shift switching circuit 150. The slope determination circuit 140 connects the shift switching circuit 150 and the comparison circuit 120. The comparison circuits 110 and 120 are respectively connected to the flip-flop circuit 130.
In operation, the comparison circuit 110 outputs a first signal SET according to the reference signal REF1 and the output voltage Vout. The comparison circuit 120 outputs a second signal RE according to the reference signal REF2 and the slope modulation voltage VC. The flip-flop circuit 130 outputs the control signal CS according to the first signal SET and the second signal RE. The slope determination circuit 140 outputs a slope modulation voltage VC according to the delay signal PG, and determines a slope of the slope modulation voltage VC according to the gear switching signal CCOT. The shift position switching circuit 150 outputs a shift position switching signal based on the low frequency signal LHZ and the detection signal ZCD.
Please refer to fig. 3 and fig. 4 together. Fig. 3 is a schematic diagram of a portion of a specific circuit of the embodiment of fig. 2 according to the present disclosure. Fig. 4 is a schematic diagram of signal waveforms of the embodiment of fig. 3 according to the present disclosure. As shown in fig. 3, the comparison circuits 110 and 120 may be implemented by comparators COMP1 and COMP2, respectively. The flip-flop circuit 130 may be implemented by an RS flip-flop composed of two NOR gates NOR1, NOR 2.
Specifically, the two input terminals of the comparator COMP1 receive the reference signal REF1 and the output voltage Vout, respectively. The output of the comparator COMP1 is connected to the first input of the RS flip-flop. For example, as shown in the period P1 in fig. 4, when the output voltage Vout is less than or equal to the reference signal REF1, the comparator COMP1 outputs the first signal SET with high level to the NOR gate NOR1.
The two inputs of the comparator COMP2 receive the reference signal REF2 and the slope modulation voltage VC, respectively. The output of the comparator COMP2 is connected to the second input of the RS flip-flop via a NOT gate. For example, as shown in the period P2 in fig. 4, when the slope modulation voltage VC is greater than or equal to the reference signal REF2, the comparator COMP2 outputs the high second signal RE to the NOR gate NOR2 through the NOR gate.
According to the logic operation of the RS flip-flop, when the first signal SET is at the high level and the RE signal is at the low level, the output terminal of the NOR gate NOR2 outputs the low level control signal CS through the NOR gate (as shown in the period T1 of fig. 4). When the second signal RE is at the high level, the output of the NOR gate NOR2 outputs the control signal CS at the high level via the NOR gate (as shown in the period T2 of fig. 4).
In some embodiments, as shown in FIG. 3, the slope determination circuit 140 includes a current source IS, switches M3, M4, SW [0] to SW [3], and capacitors C0 to C3. Specifically, the current source IS connected between the system high voltage VCC and the first terminal of the switch M3. The second terminal of the switch M3 and the first terminal of the switch M4 are connected to the output terminal. The second terminal of the switch M4 is grounded. The first ends of the switches SW 0-SW 3 are connected to the output end. The second ends of the switches SW 0-SW 3 are respectively connected with the first ends of the capacitors C0-C3. The second ends of the capacitors C0-C3 are grounded.
In operation, the switch M3 IS selectively turned on according to the enable signal EN to enable the system high voltage VCC and the current source IS to supply the voltage current to the output terminal. The switch M4 is selectively turned on according to the delay signal PG to ground the output terminal. For example, as shown in the period T1 in fig. 4, when the enable signal EN is at the high level and the delay signal PG is at the low level, the switch M3 is turned on and the switch M4 is turned off, so that the slope modulation voltage VC of the output terminal rises. As shown in the period T2 in fig. 4, when the enable signal EN is at the low level and the delay signal PG is at the high level, the switch M3 is turned off and the switch M4 is turned on, so that the slope modulation voltage VC of the output terminal becomes the ground voltage level.
In addition, the switches SW [0] to SW [3] determine which is turned on or off according to the gear switching signal CCOT, so that the output end is connected with a corresponding one or more of the capacitors C0 to C3, and the equivalent capacitance value is the minimum capacitance value or the preset capacitance value. For example, in some embodiments, the capacitances C0-C3 have different capacitance values, with the capacitance value of the capacitance C0 being the smallest. When the shift switching signal CCOT is at the low level, only the switch SW [0] is turned on, so that the equivalent capacitance of the output terminal is at a minimum value, and thus the slope of the slope modulation voltage VC is at a maximum, as shown in the period T1 of FIG. 4. When the shift switching signal CCOT is at a high level, one of the switches SW [1] to SW [3] is turned on, so that the equivalent capacitance value of the output terminal connection becomes large, and therefore the rising slope of the slope modulation voltage VC becomes small, as shown in the period T3 in FIG. 4.
In this way, the equivalent capacitance of the connection capacitor is adjusted by the level of the shift switching signal CCOT, so as to influence the rising slope of the slope modulation voltage VC, so that the frequency of the control signal CS generated by the comparison circuits 110 and 120 and the trigger circuit 130 can be regulated. When the equivalent capacitance is smaller, the slope of the slope modulation voltage VC increases, and the frequency of the control signal CS increases, as shown by periods T1 and T2 in fig. 4. Conversely, as the equivalent capacitance increases, the slope of the slope modulation voltage VC increases, and the frequency of the control signal CS decreases, as shown by periods T3 and T4 in fig. 4.
It should be noted that the switches SW [0] to SW [3] and the capacitors C0 to C3 shown in FIG. 3 are only illustrative examples and are not intended to limit the present disclosure. The amount of capacitance, the magnitude of capacitance and the gear setting of the slope determination circuit 140 can be adjusted and designed according to actual requirements. For example, in other embodiments, the capacitances of the capacitors C0-C3 may be the same, and different numbers of capacitors may be connected to different gear positions according to the setting. For another example, two or more gears may be set according to the gear shift signal CCOT.
Please refer to fig. 5. Fig. 5 is a flow chart of a pulse frequency control method 500 according to an embodiment of the present disclosure. As shown in fig. 5, the pulse frequency control method 500 includes operations S510 to S540.
First, in operation S510, a low frequency square wave is taken, and the control signal CS and the output signals Iout, vout are detected.
Next, in operation S520, it is determined whether the load is in light load and the control signal CS is lower than the low frequency signal LHZ. Since the lowest audible frequency of the human ear is about 20KHz, the low frequency signal LHZ may be set to a square wave signal of 32KHz above this frequency (as shown in fig. 7), but is not limited thereto.
When the load is not in light load or the control signal CS is not lower than the low frequency signal LHZ, operation S530 is performed, and the load is switched to the preset capacitance value according to the gear switching signal CCOT. In this way, when the control signal CS is already at a sufficiently high frequency or heavy load, the control signal CS can be switched back to the preset capacitance value to ensure sufficient power supply to the load.
When the load is in light load and the control signal CS is lower than the low frequency signal LHZ, operation S540 is performed, and the minimum capacitance is switched according to the gear switching signal CCOT. Therefore, when the power supply to the load is enough, the frequency of the output signal can be increased by switching to the minimum capacitance value, so that noise surge is prevented from affecting the audio quality along with the input of the output signal into the audio equipment.
Please refer to fig. 6 and fig. 7 together. Fig. 6 is a schematic diagram of another portion of the embodiment of fig. 2 according to the present disclosure. Fig. 7 is a schematic diagram of signal waveforms of the embodiment of fig. 6 according to the present disclosure. As shown in fig. 6, the shift position switching circuit 150 includes a detection circuit 151, flip-flops FF1 to FF3, AND gates AND1, AND2.
Specifically, the detection circuit 151 receives the output current Iout, outputs the detection signal ZCD at the high level according to the output current Iout approaching zero, and outputs the detection signal ZCD at the low level according to the output current Iout being greater than zero.
Flip-flop FF1 is an RS flip-flop. The S input receives the delay signal NG. The R input terminal is connected to the detection circuit 151 to receive the detection signal ZCD. According to the logic operation of the RS flip-flop, when the delay signal NG is at a high level, the Q output terminal outputs the high level discrimination signal Q1. When the detection signal ZCD is at the high level, the Q output terminal outputs the low level determination signal Q1. When both the delay signal NG and the detection signal ZCD are at the low level, the determination signal Q1 maintains the original level.
The AND gate AND1 receives the low-frequency enable signal ENL, AND is connected to the Q output terminal of the flip-flop FF1 to receive the discrimination signal Q1. When the low-frequency enable signal ENL is turned to a high level, the level of the determination signal R1 outputted from the AND gate AND1 is changed along with the determination signal Q1.
Flip-flop FF2 is a D flip-flop. The D input receives a high reference voltage HV (or system high voltage VCC). The CK clock input receives the control signal CS. The reset input is connected to the AND gate AND1 to receive the discrimination signal R1. According to the logic operation of the D flip-flop, when the determination signal R1 is at the low level, the QB output terminal must output the determination signal QB2 at the high level. When the determination signal R1 is at the high level, the QB output terminal outputs the low level determination signal QB2 when the control signal CS is turned to the high level.
The AND gate AND2 receives the low frequency enable signal ENL, AND is connected to the flip-flop FF2 to receive the discrimination signal QB2. When the low-frequency enable signal ENL is turned to a high level, the level of the determination signal R2 outputted from the AND gate AND2 is changed along with the determination signal QB2.
Flip-flop FF3 is a D flip-flop. The D input receives a high reference voltage HV (or system high voltage VCC). The CK clock input receives a low frequency signal LHZ. The reset input is connected to the AND gate AND2 to receive the discrimination signal R2. According to the logic operation of the D flip-flop, when the determination signal R2 is at the low level, the QB output terminal must output the high level shift switch signal CCOT. When the determination signal R2 is at the high level, the QB output terminal outputs the low level shift switching signal CCOT when the low frequency signal LHZ is turned to the high level.
In this way, as shown in the period T5 of fig. 7, when the output current Iout is insufficient (heavy load) to maintain the detection signal ZCD at the low level, the shift switching signal CCOT is switched to the high level to switch to the preset capacitance value when the control signal CS is switched from the low level to the high level, so as to ensure that the power conversion circuit 200 can supply sufficient power to the load. In addition, as shown in the period T6 of fig. 7, when the output current Iout is again approaching zero so that the detection signal ZCD goes to the high level, the gear switching signal CCOT goes to the low level to switch to the minimum capacitance value to increase the operation frequency of the power conversion circuit 200 when the low frequency signal LHZ goes from the low level to the high level, thereby avoiding falling to the low frequency.
In summary, the pulse frequency control circuit 100 adjusts the level of the control signal CS according to the feedback of the control signal CS, the delay signals PG and NG, the output current Iout and the output voltage Vout, so as to control the power conversion circuit 200 to charge and discharge the load to generate the output signal. The equivalent capacitance value of the connection capacitor is controlled by the level of the shift switching signal CCOT, so that the rising slope of the slope modulation voltage VC can be controlled, and the frequency of the control signal CS can be regulated.
While the present disclosure has been described with reference to the embodiments, it should be understood that the invention is not limited thereto, but may be variously modified and modified by those skilled in the art without departing from the spirit and scope of the present disclosure, and thus the scope of the present disclosure is defined by the appended claims.
Claims (10)
1. A pulse frequency control circuit comprising:
a first comparison circuit for outputting a first signal according to an output voltage of a power conversion circuit;
a gear switching circuit for outputting a gear switching signal according to an output current of the power switching circuit;
A slope determination circuit for outputting a slope modulation voltage and determining whether the slope modulation voltage has a first slope or a second slope according to the gear switching signal;
A second comparison circuit for outputting a second signal according to the slope modulation voltage; and
A trigger circuit for outputting a control signal to the power conversion circuit according to the first signal and the second signal,
When the frequency of the control signal is lower than that of a low-frequency signal, the gear switching circuit outputs the gear switching signal with a first level, so that the slope modulation voltage has the first slope and the control signal has a first frequency, and when the frequency of the control signal is not lower than that of the low-frequency signal, the gear switching circuit outputs the gear switching signal with a second level, so that the slope modulation voltage has the second slope and the control signal has a second frequency, and the first frequency is higher than the second frequency.
2. The pulse frequency control circuit of claim 1, wherein the first comparator is configured to output a first signal when the output voltage is less than or equal to a first reference signal, and the second comparator is configured to output a second signal when the slope modulation voltage is greater than or equal to a second reference signal.
3. The pulse frequency control circuit of claim 2, wherein the trigger circuit outputs the control signal having a first level when the trigger circuit receives the first signal, and outputs the control signal having a second level when the trigger circuit receives the second signal.
4. The pulse frequency control circuit of claim 3, wherein the slope determination circuit comprises:
A current source;
an output end;
a grounding end;
the first switch is electrically connected between the current source and the output end;
The second switch is electrically connected between the output end and the grounding end; and
The capacitor array is electrically connected to the output end through a switch array, wherein when the control signal has the first level, the first switch is turned on and the second switch is turned off, so that the current source charges the capacitor array, and when the control signal has the second level, the first switch is turned off and the second switch is turned on, so that the capacitor array discharges.
5. The pulse frequency control circuit according to claim 4, wherein when the shift switching signal is at a low level, a corresponding one of the switch arrays is turned on to electrically connect the output terminal with a first capacitance value in the capacitor array, and when the shift switching signal is at a high level, a predetermined one of the switch arrays is turned on to electrically connect the output terminal with a second capacitance value in the capacitor array, wherein the second capacitance value is greater than the first capacitance value.
6. The pulse frequency control circuit according to claim 3, wherein the shift switching circuit comprises:
A detection circuit for generating a detection signal according to the output current;
The first trigger is used for receiving the detection signal and a delay signal of the output voltage and generating a first judging signal according to the detection signal and the delay signal;
the second trigger is used for receiving the first judging signal and the control signal and generating a second judging signal according to the first judging signal and the control signal; and
The third trigger is used for receiving the second judging signal and the low-frequency signal and generating the gear switching signal according to the second judging signal and the low-frequency signal.
7. The pulse frequency control circuit according to claim 6, wherein the first flip-flop is configured to output the first determination signal having a high level when the voltage level of the delay signal increases, and to output the first determination signal having a low level when the voltage level of the detection signal increases,
The second trigger is used for outputting the second judging signal with the high level when the first judging signal is positioned at the low level, and outputting the second judging signal with the low level when the first judging signal is positioned at the high level and the voltage level of the control signal is increased,
The third trigger is used for outputting the gear switching signal with the high level when the second judging signal is positioned at the low level, and outputting the gear switching signal with the low level when the second judging signal is positioned at the high level and the low-frequency square wave signal rises.
8. A pulse frequency control system comprising:
The power supply conversion circuit is used for charging and discharging a load according to a control signal so as to generate an output signal; and
A pulse frequency control circuit comprising:
a first comparison circuit for outputting a first signal according to an output voltage of the output signal;
a gear switching circuit for outputting a gear switching signal according to an output current of the output signal, the control signal and a low frequency signal;
A slope determination circuit for outputting a slope modulation voltage and determining whether the slope modulation voltage has a first slope or a second slope according to the gear switching signal;
A second comparison circuit for outputting a second signal according to the slope modulation voltage; and
A trigger circuit for outputting the control signal to the power conversion circuit according to the first signal and the second signal,
When the frequency of the control signal is lower than the frequency of the low-frequency signal, the gear switching circuit outputs the gear switching signal with a first level, so that the slope modulation voltage has the first slope and the control signal has a first frequency, and when the frequency of the control signal is not lower than the frequency of the low-frequency signal, the gear switching circuit outputs the gear switching signal with a second level, so that the slope modulation voltage has the second slope and the control signal has a second frequency, and the first frequency is higher than the second frequency.
9. The pulse frequency control system of claim 8, wherein the power conversion circuit is configured to charge the load when receiving the control signal having a first level, and is configured to discharge the load when receiving the control signal having a second level.
10. A pulse frequency control method comprising:
a pulse frequency control circuit outputs a control signal;
a power supply conversion circuit charges and discharges a load according to the control signal so as to generate an output signal;
Judging whether the load connected with the power conversion circuit is in light load or not according to the output signal, and judging whether the frequency of the control signal is lower than that of a low-frequency signal or not;
When the load is in light load and the frequency of the control signal is lower than the frequency of the low-frequency signal, a capacitor array of the pulse frequency control circuit is switched to a first capacitance value so as to generate the control signal with a first frequency; and
When the load is not in light load or the frequency of the control signal is not lower than the frequency of the low-frequency signal, the capacitor array of the pulse frequency control circuit is switched to a second capacitance value to generate the control signal with a second frequency, wherein the first capacitance value is smaller than the second capacitance value, and the first frequency is higher than the second frequency.
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| US7869499B2 (en) * | 2007-07-27 | 2011-01-11 | Fsp Technology Inc. | Variable-frequency circuit with a compensation mechanism |
| TWI568165B (en) * | 2014-10-09 | 2017-01-21 | 立錡科技股份有限公司 | Flyback power converter with programmable function and control circuit and control method thereof |
| CN105896934B (en) * | 2016-04-13 | 2018-10-30 | 成都芯源***有限公司 | Switching power supply with adaptive clock and controller and control method thereof |
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| 基于COT控制的高效率BUCK变换器的研究与设计;李要;中国优秀硕士学位论文全文数据库（电子期刊）工程科技II辑》(第3期);全文 * |
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