CN113161868A - Wafer and manufacturing method thereof - Google Patents

Wafer and manufacturing method thereof Download PDF

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Publication number
CN113161868A
CN113161868A CN202110389796.4A CN202110389796A CN113161868A CN 113161868 A CN113161868 A CN 113161868A CN 202110389796 A CN202110389796 A CN 202110389796A CN 113161868 A CN113161868 A CN 113161868A
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China
Prior art keywords
layer
bragg reflector
distributed bragg
manufacturing
type distributed
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Pending
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CN202110389796.4A
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Chinese (zh)
Inventor
韩春霞
杨旭
刘哲
周璇
黄蓓
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Wuhan Qianmu Laser Co ltd
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Wuhan Qianmu Laser Co ltd
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Priority to CN202110389796.4A priority Critical patent/CN113161868A/en
Publication of CN113161868A publication Critical patent/CN113161868A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/185—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only horizontal cavities, e.g. horizontal cavity surface-emitting lasers [HCSEL]
    • H01S5/187—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only horizontal cavities, e.g. horizontal cavity surface-emitting lasers [HCSEL] using Bragg reflection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/2004—Confining in the direction perpendicular to the layer structure
    • H01S5/2009—Confining in the direction perpendicular to the layer structure by using electron barrier layers
    • H01S5/2013—MQW barrier reflection layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
    • H01S5/3403—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers having a strained layer structure in which the strain performs a special function, e.g. general strain effects, strain versus polarisation
    • H01S5/3406—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers having a strained layer structure in which the strain performs a special function, e.g. general strain effects, strain versus polarisation including strain compensation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Led Devices (AREA)

Abstract

The invention relates to a manufacturing method of a wafer, which comprises S1, sequentially growing an N-type distributed Bragg reflector layer and a P-type distributed Bragg reflector layer on a substrate; s2, growing a stress balance layer on one side of the substrate, which is far away from the N-type distributed Bragg reflector layer; and S3, manufacturing a metal thickening layer on the stress balancing layer. The wafer is also provided, the body comprises an N-type distributed Bragg reflector layer and a P-type distributed Bragg reflector layer, one side of the body close to the N-type distributed Bragg reflector layer is an N surface, and one side of the body close to the P-type distributed Bragg reflector layer is a P surface; and growing a stress balance layer on the N surface of the body, and manufacturing a metal thickening layer on the stress balance layer. The invention can reduce stress to avoid the risk of fragment, thereby improving the stability and reliability of the device, and meanwhile, the manufactured metal thickening layer can protect the stress balancing layer on one hand, and can enable the N-side metal to be smoother and more flat on the other hand, thereby facilitating subsequent packaging.

Description

Wafer and manufacturing method thereof
Technical Field
The invention relates to the technical field of lasers, in particular to a wafer and a manufacturing method thereof.
Background
With the progress of science and technology, the high power output performance of the VCSEL is equivalent to that of an edge-emitting semiconductor laser, and due to the unique structure and design, the VCSEL has many advantages in application, such as high reliability, high temperature resistance, uniform optical distribution, severe environment resistance and the like. In recent years, with the development of smart phones, functions such as 3D imaging, gesture recognition, auto-focusing, iris recognition, and 3D face recognition are being integrated into the smart phones, which will bring a new revolution to the VCSEL laser field. However, in the prior art, many processes may generate stress or warpage during the process of fabricating the VCSEL, for example: MOCVD is used for growing epitaxial structures, photoetching, film growing, etching, scribing and the like. If the stress or warpage is severe, it may affect the performance, stability and reliability of the device to some extent, and may even lead to device failure.
The deposition process of the multilayer epitaxial structure by Metal Organic Chemical Vapor Deposition (MOCVD) causes a large stress between the epitaxial layer and the substrate (GaAS), which causes the grown epitaxial wafer to be seriously warped. On the other hand, gallium arsenide (GaAS) chips are more easily broken than indium phosphide (InP) substrates, and in this case, chip-end processes are very likely to cause chip breakage, which seriously affects the effective yield per unit area and the work efficiency per unit time, especially for epitaxial chips with larger sizes.
During the thinning process of the chip end, if the wafer is directly thinned, the wafer may be damaged due to uneven stress caused by extrusion and the like. The stress is released after thinning, but the N side is plated with metal due to the process requirement, and the stress is rapidly increased by the metal deposition process. If the wafer is thin and only the metal seed layer is plated, the stress is likely to increase sharply, and the wafer may be broken.
During the process of cutting the chip, the chip is separated from the chip due to the extrusion of the laser, the blade and the external force, which causes the structure of the epitaxial layer to be subjected to a great stress and causes defects in the structure of the epitaxial layer, thereby affecting the stability and reliability of the device.
Disclosure of Invention
The invention aims to provide a wafer and a manufacturing method thereof, wherein a stress balance layer is grown on the N surface of the wafer, so that the stress can be reduced to avoid the risk of breakage, and further the stability and the reliability of a device are improved.
In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions: a method for manufacturing a wafer comprises the following steps:
s1, growing an N-type distributed Bragg reflector layer and a P-type distributed Bragg reflector layer on the substrate in sequence;
s2, growing a stress balance layer on one side of the substrate, which is far away from the N-type distributed Bragg reflector layer;
and S3, manufacturing a metal thickening layer on the stress balancing layer.
Further, the step S2 is performed after the thinning process is performed.
Furthermore, before the thinning process is carried out, a thickening layer is arranged on one side of the P-type distributed Bragg reflector layer, which is far away from the N-type distributed Bragg reflector layer, for thickening, and the thickening layer is removed after the wafer is manufactured.
Further, the thickening layer is disposed on the wafer to be processed by wax.
Furthermore, the thickening layer adopts sapphire, silicon, gallium arsenide, silicon carbide, zinc oxide or aluminum nitride.
Further, the stress balance layer adopts titanium, tungsten or a combination of the titanium and the tungsten.
Further, the temperature of the stress balance layer is 55-500 ℃.
Further, the stress balance layer is grown in a deposition mode, specifically, evaporation, physical vapor deposition, sputtering or electroplating.
Further, the substrate is a group III/V, IV compound semiconductor.
The embodiment of the invention provides another technical scheme: a wafer comprises a body, wherein the body comprises an N-type distributed Bragg reflector layer and a P-type distributed Bragg reflector layer, one side of the body, which is close to the N-type distributed Bragg reflector layer, is an N surface, and one side of the body, which is close to the P-type distributed Bragg reflector layer, is a P surface; and growing a stress balance layer on the N surface of the body, and manufacturing a metal thickening layer on the stress balance layer.
Compared with the prior art, the invention has the beneficial effects that: through the N face growth stress balance layer at the wafer, can reduce stress and avoid the risk of rupture of chip, and then promoted the stability and the reliability of device, the metal thickening layer of preparation simultaneously can protect the stress balance layer on the one hand, and on the other hand can make the smooth follow-up encapsulation of being convenient for of N face metal more.
Drawings
Fig. 1 is a schematic view of a wafer (including a thickening layer) according to an embodiment of the invention;
in the reference symbols: 101-a substrate; 102-N type distributed Bragg reflector layer; 103-multiple quantum well layer; 104-P type distributed Bragg reflector layer; 105-a cap layer; 106-oxidized pores; 107-metal layer; 108-a first insulating layer; 109-a planarization layer; 110-a second insulating layer; 111-electrode contact layer; 112-thickening layer; 113-a seed layer; 114-a stress-balancing layer; 115-metal thickening layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a wafer according to an embodiment of the present invention includes a body, where the body includes an N-type dbr layer 102 and a P-type dbr layer 104, one side of the body near the N-type dbr layer 102 is an N-plane, and one side of the body near the P-type dbr layer 104 is a P-plane; a stress balance layer 114 is grown on the N-face of the body, and a metal thickening layer 115 is fabricated on the stress balance layer 114. In the prior art, metal is directly plated on the N surface, and the stress is rapidly increased in the metal deposition process. In this case, the wafer is thin, and if only the metal plating layer 107 is formed, the stress is likely to increase sharply, and there is a risk of breakage. During the process of cutting the chip, the chip is separated from the chip due to the extrusion of the laser, the blade and the external force, which causes the structure of the epitaxial layer to be subjected to a great stress and causes defects in the structure of the epitaxial layer, thereby affecting the stability and reliability of the device. In this embodiment, through the N face growth stress balance layer 114 at the wafer, can reduce stress and avoid the risk of rupture of the wafer, and then promoted the stability and the reliability of device, the metal thickening layer 115 of preparation simultaneously can protect stress balance layer 114 on the one hand, and on the other hand can make the N face metal smooth more and flat be convenient for follow-up encapsulation, can not destroy the epitaxial structure layer, has improved the stability and the reliability of device. Specifically, the wafer defines an N-plane and a P-plane by the N-DBR layer (the N-DBR layer 102 layer) and the P-DBR layer (the P-DBR layer 104 layer), respectively, where the N-plane is the side of the N-DBR layer 102 away from the P-DBR layer 104, and the P-plane is the side of the P-DBR layer 104 away from the N-DBR layer 102. After the thinning process is completed, the stress balance layer 114 is grown on the N surface of the wafer, and the stress generated after thinning can be reduced, wherein the stress balance layer 114 adopts titanium (Ti), tungsten (W) or a combination of the two. In order to protect the stress balance layer 114, a metal thickening layer 115 may be formed on the stress balance layer 114, and after the metal thickening layer 115 is formed, the N-side metal may be made smoother and more planar for subsequent packaging. Preferably, the stress balance layer 114 is deposited by evaporation (including but not limited to electron beam), Physical Vapor Deposition (PVD), sputtering (sputtering), Plating (Plating), and the like. And the thickness of the deposited stress balance layer 114 is between 50 nm and 5000 nm. Preferably, the temperature of the stress balance layer 114 is between 55 and 500 ℃.
As an optimized solution of the embodiment of the present invention, please refer to fig. 1, in which the body further includes a substrate 101, the N-type dbr layer 102 and the P-type dbr layer 104 are both located on the same side of the substrate 101, the N-type dbr layer 102 is located between the substrate 101 and the P-type dbr layer 104, and the stress balancing layer 114 and the metal thickening layer 115 are both located on a side of the substrate 101 away from the N-type dbr layer 102. Preferably, a seed layer 113 is provided between the substrate 101 and the stress balance layer 114. Preferably, a multiple quantum well layer 103 is provided between the N-type dbr layer 102 and the P-type dbr layer 104. Preferably, the body further includes a cap layer 105 disposed on a side of the P-type dbr layer 104 away from the N-type dbr layer 102. The cap layer 105 is provided with a metal layer 107 and a first insulating layer 108. A second insulating layer 110 is further disposed on the first insulating layer 108, and an electrode contact layer 111 is disposed on the second insulating layer 110. Preferably, the body further includes a planarization layer 109 and an oxide hole 106, the planarization layer 109 penetrates through the P-type dbr layer 104 and extends to the N-type dbr layer 102, and the oxide hole 106 is disposed in the P-type dbr layer 104. In the present embodiment, the structure of the wafer has been refined, wherein the substrate 101 is made of a group iii/v, iv compound semiconductor, specifically gallium arsenide (GaAS), indium phosphide (InP), silicon (Si), gallium nitride (GaN), silicon carbide (SiC), or germanium (Ge). The thickness of the stress balance layer 114 is between 50 nm and 5000 nm. Preferably, the size of the substrate 101 is controlled to be 2-12 inches, and the substrate 101 is a GaAs substrate.
The embodiment of the invention provides a VCSEL laser which comprises a plurality of wafers.
The embodiment of the invention provides a manufacturing method of a wafer, which comprises the following steps: s1, growing an N-type distributed Bragg reflector layer 102 and a P-type distributed Bragg reflector layer 104 on a substrate 101 in sequence; s2, growing a stress balance layer 114 on the side of the substrate 101, which faces away from the N-type distributed Bragg reflector layer 102; s3, forming a metal thickening layer 115 on the stress balance layer 114. In the prior art, metal is directly plated on the N surface, and the stress is rapidly increased in the metal deposition process. In this case, the wafer is thin, and if only the metal plating layer 107 is formed, the stress is likely to increase sharply, and there is a risk of breakage. During the process of cutting the chip, the chip is separated from the chip due to the extrusion of the laser, the blade and the external force, which causes the structure of the epitaxial layer to be subjected to a great stress and causes defects in the structure of the epitaxial layer, thereby affecting the stability and reliability of the device. In this embodiment, through the N face growth stress balance layer 114 at the wafer, can reduce stress and avoid the risk of rupture of the wafer, and then promoted the stability and the reliability of device, the metal thickening layer 115 of preparation simultaneously can protect stress balance layer 114 on the one hand, and on the other hand can make the N face metal smooth more and flat be convenient for follow-up encapsulation, can not destroy the epitaxial structure layer, has improved the stability and the reliability of device. Specifically, the wafer defines an N-plane and a P-plane by the N-DBR layer (the N-DBR layer 102 layer) and the P-DBR layer (the P-DBR layer 104 layer), respectively, where the N-plane is the side of the N-DBR layer 102 away from the P-DBR layer 104, and the P-plane is the side of the P-DBR layer 104 away from the N-DBR layer 102. After the thinning process is completed, the stress balance layer 114 is grown on the N surface of the wafer, and the stress generated after thinning can be reduced, wherein the stress balance layer 114 adopts titanium (Ti), tungsten (W) or a combination of the two. In order to protect the stress balance layer 114, a metal thickening layer 115 may be formed on the stress balance layer 114, and after the metal thickening layer 115 is formed, the N-side metal may be made smoother and more planar for subsequent packaging. Preferably, the stress balance layer 114 is deposited by evaporation (including but not limited to electron beam), Physical Vapor Deposition (PVD), sputtering (sputtering), Plating (Plating), and the like. And the thickness of the deposited stress balance layer 114 is between 50 nm and 5000 nm.
As an optimized scheme of the embodiment of the invention, the step S2 is performed after the thinning process is performed. Before the thinning process is performed, a thickening layer 112 is arranged on one side of the P-type distributed bragg reflector layer 104 far away from the N-type distributed bragg reflector layer 102 to be thickened, and the thickening layer 112 is removed after the wafer is manufactured. The thickening layer 112 is provided on the wafer to be processed by wax. In this embodiment, the wafer is first subjected to a bonder (bonding) process with a thickening layer 112 before the thinning process, so that the risk of chipping can be avoided during thinning. Bonder may use a substance such as wax that will readily separate the thickening layer 112 during subsequent processing. And the thickening layer 112 is preferably sapphire, silicon, gallium arsenide, silicon carbide, zinc oxide, or aluminum nitride. Preferably, the thickness of the thickening layer 112 is 600-1500 μm, and the size of the thickening layer 112 is slightly larger than the size of the wafer, so that the P surface of the wafer cannot be damaged in the processes of the binder and the de-binder.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (10)

1. A method for manufacturing a wafer is characterized by comprising the following steps:
s1, growing an N-type distributed Bragg reflector layer and a P-type distributed Bragg reflector layer on the substrate in sequence;
s2, growing a stress balance layer on one side of the substrate, which is far away from the N-type distributed Bragg reflector layer;
and S3, manufacturing a metal thickening layer on the stress balancing layer.
2. The method for manufacturing a wafer according to claim 1, wherein: the step S2 is performed after the thinning process is performed.
3. The method for manufacturing a wafer according to claim 2, wherein: before the thinning process is carried out, a thickening layer is arranged on one side of the P-type distributed Bragg reflector layer, which is far away from the N-type distributed Bragg reflector layer, for thickening, and the thickening layer is removed after the wafer is manufactured.
4. The method for manufacturing a wafer according to claim 3, wherein: the thickening layer is arranged on a wafer to be processed through wax.
5. The method for manufacturing a wafer according to claim 3, wherein: the thickening layer is made of sapphire, silicon, gallium arsenide, silicon carbide, zinc oxide or aluminum nitride.
6. The method for manufacturing a wafer according to claim 1, wherein: the stress balance layer adopts titanium, tungsten or a combination of the titanium and the tungsten.
7. The method for manufacturing a wafer according to claim 1, wherein: the temperature of the stress balance layer is 55-500 ℃.
8. The method for manufacturing a wafer according to claim 1, wherein: the stress balance layer grows in a deposition mode, specifically evaporation, physical vapor deposition, sputtering or electroplating.
9. The method for manufacturing a wafer according to claim 1, wherein: the substrate is a III/V, IV group compound semiconductor.
10. A wafer comprising a body, characterized in that: the body comprises an N-type distributed Bragg reflector layer and a P-type distributed Bragg reflector layer, wherein an N surface is arranged on one side of the body close to the N-type distributed Bragg reflector layer, and a P surface is arranged on one side of the body close to the P-type distributed Bragg reflector layer; and growing a stress balance layer on the N surface of the body, and manufacturing a metal thickening layer on the stress balance layer.
CN202110389796.4A 2021-04-12 2021-04-12 Wafer and manufacturing method thereof Pending CN113161868A (en)

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Publication number Priority date Publication date Assignee Title
CN103151432A (en) * 2011-02-03 2013-06-12 Soitec公司 Metallic carrier for layer transfer and methods for forming the same
CN103560193A (en) * 2013-08-29 2014-02-05 南昌黄绿照明有限公司 Vertical structure light emitting diode chip with low cost and preparation method thereof
CN106449912A (en) * 2016-11-28 2017-02-22 东莞市中镓半导体科技有限公司 GaN-based composite substrate with stress balance structural layer and method for preparing GaN-based composite substrate
CN106611717A (en) * 2015-10-22 2017-05-03 浙江中纳晶微电子科技有限公司 Procedure of processing workpiece and apparatus designed for procedure
US20170186919A1 (en) * 2015-12-29 2017-06-29 Light Share, LLC Optoelectronic Semiconductor Devices with Enhanced Light Output
CN108767083A (en) * 2018-05-30 2018-11-06 河源市众拓光电科技有限公司 A kind of adjustable light emitting diode (LED) chip with vertical structure of stress and preparation method thereof
CN109103747A (en) * 2017-06-20 2018-12-28 稳懋半导体股份有限公司 To reduce the structure-improved of compound semiconductor wafer deformation
CN110235220A (en) * 2016-09-16 2019-09-13 Ii-Vi光电子设备有限公司 The metal adjustable thin film stress compensation of epitaxial wafer
CN112186079A (en) * 2020-09-28 2021-01-05 厦门士兰明镓化合物半导体有限公司 Preparation method of LED chip with vertical structure
CN214506049U (en) * 2021-04-12 2021-10-26 武汉仟目激光有限公司 Wafer and VCSEL laser

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103151432A (en) * 2011-02-03 2013-06-12 Soitec公司 Metallic carrier for layer transfer and methods for forming the same
CN103560193A (en) * 2013-08-29 2014-02-05 南昌黄绿照明有限公司 Vertical structure light emitting diode chip with low cost and preparation method thereof
CN106611717A (en) * 2015-10-22 2017-05-03 浙江中纳晶微电子科技有限公司 Procedure of processing workpiece and apparatus designed for procedure
US20170186919A1 (en) * 2015-12-29 2017-06-29 Light Share, LLC Optoelectronic Semiconductor Devices with Enhanced Light Output
CN110235220A (en) * 2016-09-16 2019-09-13 Ii-Vi光电子设备有限公司 The metal adjustable thin film stress compensation of epitaxial wafer
CN106449912A (en) * 2016-11-28 2017-02-22 东莞市中镓半导体科技有限公司 GaN-based composite substrate with stress balance structural layer and method for preparing GaN-based composite substrate
CN109103747A (en) * 2017-06-20 2018-12-28 稳懋半导体股份有限公司 To reduce the structure-improved of compound semiconductor wafer deformation
CN108767083A (en) * 2018-05-30 2018-11-06 河源市众拓光电科技有限公司 A kind of adjustable light emitting diode (LED) chip with vertical structure of stress and preparation method thereof
CN112186079A (en) * 2020-09-28 2021-01-05 厦门士兰明镓化合物半导体有限公司 Preparation method of LED chip with vertical structure
CN214506049U (en) * 2021-04-12 2021-10-26 武汉仟目激光有限公司 Wafer and VCSEL laser

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Application publication date: 20210723