CN113161347B - Low-capacitance low-residual voltage high-power overvoltage protection device chip and manufacturing process thereof - Google Patents
Low-capacitance low-residual voltage high-power overvoltage protection device chip and manufacturing process thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 45
- 238000001259 photo etching Methods 0.000 claims abstract description 28
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 22
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 22
- 239000011521 glass Substances 0.000 claims abstract description 11
- 238000009792 diffusion process Methods 0.000 claims description 77
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 37
- 229910052698 phosphorus Inorganic materials 0.000 claims description 37
- 239000011574 phosphorus Substances 0.000 claims description 37
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 27
- 229910052796 boron Inorganic materials 0.000 claims description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 239000007788 liquid Substances 0.000 claims description 12
- 230000000873 masking effect Effects 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000002161 passivation Methods 0.000 claims description 6
- 238000005260 corrosion Methods 0.000 claims description 5
- 230000007797 corrosion Effects 0.000 claims description 5
- 230000001681 protective effect Effects 0.000 claims description 5
- 238000005520 cutting process Methods 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 3
- QQMBHAVGDGCSGY-UHFFFAOYSA-N [Ti].[Ni].[Ag] Chemical compound [Ti].[Ni].[Ag] QQMBHAVGDGCSGY-UHFFFAOYSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 238000004080 punching Methods 0.000 claims 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 239000003990 capacitor Substances 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 4
- 230000006978 adaptation Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses a low-capacitance low-residual-voltage high-power overvoltage protection device chip, which comprises an N-type monocrystalline silicon wafer, wherein a through region and a trigger region are formed on two sides of the N-type monocrystalline silicon wafer, a base region is formed on two sides of the N-type monocrystalline silicon wafer, a cathode region is formed on the base region on two sides of the N-type monocrystalline silicon wafer, a double-sided oxide layer is formed on two sides of the N-type monocrystalline silicon wafer, an inner groove table surface is formed at the position between an anode region and the through region on the double-sided oxide layer, a glass layer is filled at the position of the inner groove table surface, a silicon dioxide protection film is formed on the surface of the double-sided oxide layer and the inner groove table surface structure, lead windows are formed on the silicon dioxide protection film and the double-sided oxide layer by photoetching, and scribing grooves are formed on the edges of the two sides of the silicon dioxide protection film and the double-sided oxide layer.
Description
Technical Field
The invention relates to the technical field of chip manufacturing, in particular to a manufacturing process of a high-power semiconductor overvoltage protection device.
Background
The types of semiconductor overvoltage protection devices are more, and the most common types include transient suppression diodes and semiconductor discharge tubes, wherein the semiconductor discharge tubes are divided into: planar and mesa processes; the capacitor is divided into the following components: conventional capacitance and low capacitance; the pressure is divided according to residual pressure, and can be divided into high residual pressure and low residual pressure; the surge level is divided into 2000V/3000V/4000V/5000V/6000V, so that the surge level is more various, and the problem of use easily occurs under the condition that the application occasion is not known. The protection device has a common characteristic that a larger residual voltage (overshoot voltage) is generated when the device is opened, the higher the residual voltage is, the more easily the device burns out and fails, namely the surge resistance of the device is reduced, and conversely, the lower the residual voltage is, the stronger the surge resistance of the device is; the protection device also has another important parameter, namely the capacitor, the capacitor is an important parameter for determining the signal transmission frequency, and a lower capacitor is more suitable for being applied to high-frequency occasions, so that how to reduce residual voltage and reduce the capacitor are important points of various researches, the conventional mode is to reduce the residual voltage by directly reducing the resistivity of a substrate material, but at the cost of increasing the capacitor, and the like, the capacitor is reduced by increasing the resistivity of the substrate, but the residual voltage can not meet the requirements of customers, and how to ensure high surge capacity, low residual voltage and low capacitor is always the direction of the research of technicians.
Disclosure of Invention
The invention aims to provide a low-capacitance low-residual voltage high-power overvoltage protection device chip, which realizes compatibility of high surge, low residual voltage and low capacitance, has faster response speed, and is more suitable for the application environment in the current communication field.
The purpose of the invention is realized in the following way: the low-capacitance low-residual-voltage high-power overvoltage protection device chip comprises an N-type monocrystalline silicon wafer, wherein a through region and a trigger region are formed on two sides of the N-type monocrystalline silicon wafer through concentrated phosphorus diffusion, a base region is formed on the front surface and the back surface of the N-type monocrystalline silicon wafer through boron diffusion, an anode region with the depth larger than that of the base region is further arranged on the base region, a cathode region is formed on the base region on the front surface and the back surface of the N-type monocrystalline silicon wafer through phosphorus diffusion, double-sided oxide layers are formed on the surfaces of the base region, the anode region, the cathode region, the through region and the trigger region on the front surface and the back surface of the N-type monocrystalline silicon wafer, an inner groove mesa structure is formed between the anode region and the through region through silicon corrosion, a glass layer is filled in the inner groove mesa structure, a silicon dioxide protection film is formed on the surfaces of the double-sided oxide layers and the inner groove mesa structure, lead windows are formed on the silicon dioxide protection film and the double-sided oxide layers through photoetching, and lead windows are formed on the base region and the cathode region, and the edges on the double-sided oxide layers through photoetching, and a scribing groove is formed on the lead window;
the manufacturing process comprises the following steps:
step 1) growing a layer of silicon dioxide on an N-type monocrystalline silicon wafer through thermal oxidation;
step 2) photoetching a phosphorus-rich region window on the double-sided oxide layer;
step 3) locally diffusing a layer of concentrated phosphorus at high temperature by a liquid phosphorus source diffusion method;
step 4) carrying out concentrated phosphorus re-diffusion at high temperature to form a through region and a trigger region of the device, and simultaneously growing a layer of silicon dioxide on the surface to serve as a masking layer for subsequent diffusion;
step 5) photoetching a diffusion window of an anode region on the double-sided oxide layer;
step 6) pre-diffusing liquid boron sources on the two sides of the silicon wafer at high temperature;
step 7) performing boron re-diffusion at high temperature to form an anode region with a certain depth, and simultaneously growing an oxide layer on the surface of the anode region to serve as a masking layer for subsequent diffusion;
step 8) photoetching a base region diffusion window on the double-sided oxide layer;
step 9), liquid boron source pre-diffusion is carried out on the two sides of the silicon wafer at high temperature to dope the base region;
step 10), performing boron re-diffusion at high temperature to form a base region of the device, and simultaneously growing an oxide layer on the surface of the base region to serve as a masking layer for subsequent diffusion;
step 11), photoetching a short base region of the thyristor and a diffusion window of a boron-supplementing region of a base region of the triode on the front surface oxide layer, and photoetching a diffusion window of an anode region of the thyristor on the back surface oxide layer;
step 12) locally diffusing a layer of concentrated phosphorus at high temperature by a liquid phosphorus source diffusion method;
step 13) carrying out concentrated phosphorus re-diffusion at high temperature to form a cathode region of the device, and simultaneously growing a layer of silicon dioxide on the surface to serve as a masking layer for subsequent photoetching;
step 14), etching a deep groove etching window on the double-sided oxide layer by partial photoetching;
step 15), silicon etching is carried out at the double-sided deep groove etching window to form an inner groove mesa structure;
step 16), filling a glass layer in the inner groove as a final PN junction protection passivation layer;
step 17) depositing a silicon dioxide protective film on the surface by LPCVD;
step 18) photoetching lead windows on the front and back surfaces, and simultaneously cutting scribing grooves on the edges;
step 19) metallizing the front and back surfaces to obtain the chip.
As a further development of the invention, the temperature of the thermal oxidation in step 1) is: 1130-1180 ℃ and thickness of the obtained oxide layer: 1.3-1.8 mu m;
the temperature of diffusion in step 3) is: 1100-1160 ℃, R □ =0.6~1.5Ω/□；
The temperature of the concentrated phosphorus diffusion in the step 4) is as follows: 1250 ℃ to 1280 ℃ for the time of: 80-150 h, and finally x j =100~150µm；
The temperature of the boron pre-diffusion in step 6) is: 1000-1150 ℃ and time: 100-200 min, R □ =2~6Ω/□；
The temperature of boron re-diffusion in step 7) is: 1250 ℃ to 1280 ℃ for the time of: 50-100 h, and finally x j =50~100µm；
The temperature of the boron pre-diffusion in step 9) is: 900-1000 ℃ and the time is as follows: 60-90 min, R □ =20~40Ω/□；
The temperature of boron re-diffusion in step 10) is: 1220 ℃ to 1260 ℃ for the following time: 6-15 h, final x j =20~40µm；
The temperature of phosphorus diffusion in step 12) is: 1000-1100 ℃ and the time is as follows: 60-120 min, R □ =1.0~2.0Ω/□；
The temperature of the concentrated phosphorus diffusion in step 13) is: 1050 ℃ -1150 ℃ and time: 3-8 hours.
As a further improvement of the invention, the depth of the groove in step 15) is 30-60 μm.
As a further improvement of the invention, step 16) the glass passivation temperature is: 450-720 ℃.
As a further improvement of the invention, the metal layer in the step 19) is titanium nickel silver, and the thickness is 1-2 mu m.
Compared with the prior art, the invention has the beneficial effects that:
a) An N+ double-sided through structure is adopted, and a carrier evacuation channel is provided when the device is opened, so that lower residual voltage is generated, and the residual voltage is reduced by about 50% compared with a product with the same chip area of a conventional structure;
b) The trigger area is triggered by Deep N-well, so that the breakdown voltage consistency is good;
c) Except the trigger area, other areas are isolated by adopting a Trench structure, so that the junction capacitance is reduced by more than 50%;
d) The short circuit points of the cathode region are subjected to specialized treatment step by step, and the surge capacity of the device is higher under the condition of the same area of the chip, and is improved by more than 10%.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a front view of a chip of a low-capacitance low-residual voltage high-power overvoltage protection device manufactured by the invention.
FIG. 2 is a cross-sectional view of a chip of the low-capacitance low-residual voltage high-power overvoltage protection device manufactured by the invention.
FIGS. 3-21 are cross-sectional views of chips at various steps in the present invention.
Fig. 22 is a plan view of a cathode region according to the present invention.
The device comprises aN aN type monocrystalline silicon wafer, a b through region, a c trigger region, a d base region, aN e anode region, aN f cathode region, a g double-sided oxide layer, aN h inner groove mesa structure, aN i glass layer, a j protective film, a k lead window, a l scribing groove and aN m metal layer.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The low-capacitance low-residual voltage high-power overvoltage protection device chip shown in the figures 1-2 comprises an N-type monocrystalline silicon wafer, wherein a through region b and a trigger region c are formed on two sides of the N-type monocrystalline silicon wafer through concentrated phosphorus diffusion, a base region d is formed on the front surface and the back surface of the N-type monocrystalline silicon wafer through boron diffusion, a silicon dioxide protection film j is formed on the base region d, which is positioned on the front surface and the back surface of the N-type monocrystalline silicon wafer, a cathode region f is formed on the base region d, which is positioned on the front surface and the back surface of the N-type monocrystalline silicon wafer, through phosphorus diffusion, a double-sided oxide layer g is formed on the surfaces of the base region d, the anode region e, the cathode region f, the through region b and the trigger region c, an inner groove table structure h is formed between the anode region e and the through silicon corrosion on the double-sided oxide layer g, a glass layer i is filled in the inner groove table structure h, a silicon dioxide protection film j is formed on the surfaces of the double-sided oxide layer g and the inner groove table structure h, a window k is formed above the base region d, the anode region e and the cathode region f through phosphorus diffusion on the base region d, a double-sided oxide layer g is formed on the silicon dioxide protection film j, a double-sided oxide layer g, a lead wire forming groove is formed on the two sides, a metal lead wire scribing groove is formed on the double-sided oxide layer, and a metal scribing groove is formed on the edge of the metal m.
The cross-sectional view of the chip of the low-capacitance low-residual voltage high-power overvoltage protection device shown in the figures 3-21 comprises the following steps:
step 1) growing a layer of silicon dioxide on an N-type monocrystalline silicon wafer through thermal oxidation, wherein the thermal oxidation temperature is as follows: 1130-1180 ℃ and thickness of the obtained oxide layer: 1.3-1.8 mu m (see figure 3).
Step 2) photoetching a phosphorus-rich region window on the double-sided oxide layer (see figure 4).
Step 3) locally diffusing a layer of concentrated phosphorus by a liquid phosphorus source diffusion method at a high temperature, wherein the diffusion temperature is as follows: 1100-1160 ℃, R +=0.6-1.5 Ω/≡ (see fig. 5).
And 4) carrying out concentrated phosphorus re-diffusion at high temperature to form a through region and a trigger region of the device, and simultaneously growing a layer of silicon dioxide on the surface to serve as a masking layer for subsequent diffusion, wherein the temperature for the concentrated phosphorus diffusion is as follows: 1250 ℃ to 1280 ℃ for the time of: 80-150 h, and finally xj=100-150 [ mu ] m (see fig. 6).
Step 5) photolithography of a diffusion window of the anode region on the double-sided oxide layer (see fig. 7).
And 6) carrying out liquid boron source pre-diffusion on the two sides of the silicon wafer at high temperature, wherein the temperature of the boron pre-diffusion is as follows: 1000-1150 ℃ and time: 100-200 min, r +=2-6Ω/≡ (see fig. 8).
And 7) carrying out boron re-diffusion at high temperature to form an anode region with a certain depth, and simultaneously growing an oxide layer on the surface to serve as a masking layer for subsequent diffusion, wherein the boron re-diffusion temperature is as follows: 1250 ℃ to 1280 ℃ for the time of: 50-100 h, and finally xj=50-100 [ mu ] m (see fig. 9).
Step 8) photoetching a base region diffusion window on the double-sided oxide layer (see figure 10).
And 9) carrying out liquid boron source pre-diffusion on the two sides of the silicon wafer at high temperature to dope the base region, wherein the temperature of the boron pre-diffusion is as follows: 900-1000 ℃ and the time is as follows: 60-90 min, r +=20-40 Ω/+% (see fig. 11).
And 10) performing boron re-diffusion at high temperature to form a base region of the device, and simultaneously growing an oxide layer on the surface of the base region to serve as a masking layer for subsequent diffusion, wherein the boron re-diffusion temperature is as follows: 1220 ℃ to 1260 ℃ for the following time: 6-15 h, and finally xj=20-40 [ mu ] m (see fig. 12).
Step 11) photoetching a short base region of the thyristor and a diffusion window of a boron-supplementing region of the triode base region on the front surface oxide layer, and photoetching a diffusion window of an anode region of the thyristor on the back surface oxide layer (see figure 13).
Step 12) locally diffusing a layer of concentrated phosphorus by a liquid phosphorus source diffusion method at high temperature, wherein the diffusion temperature of the phosphorus is as follows: 1000-1100 ℃ and the time is as follows: 60-120 min, r ∈=1.0-2.0 Ω/∈ (see fig. 14).
And 13) carrying out concentrated phosphorus re-diffusion at high temperature to form a cathode region of the device, and simultaneously growing a layer of silicon dioxide on the surface to serve as a masking layer for subsequent photoetching, wherein the temperature of the concentrated phosphorus diffusion is as follows: 1050 ℃ -1150 ℃ and time: 3-8 h (see figure 15).
Step 14) etching a deep groove etching window (see fig. 16) on the double-sided oxide layer by partial photoetching.
And 15) performing silicon corrosion at the double-sided deep groove corrosion window to form an inner groove mesa structure, wherein the depth of the groove is 30-60 mu m (see figure 17).
Step 16) filling a glass layer in the inner groove as a final PN junction protection passivation layer, wherein the glass passivation temperature is as follows: 450 ℃ -720 ℃ (see figure 18).
Step 17) a silicon dioxide protective film is deposited on the surface by LPCVD (see FIG. 19).
Step 18) photoetching lead windows on the front and back surfaces, and simultaneously cutting scribing grooves on the edges (see fig. 20).
And 19) carrying out metallization on the front side and the back side to obtain the chip thickness of 1-2 mu m (see figure 21).
The invention adopts an N+ double-sided through structure (see figure 6), and provides a carrier evacuation channel when the device is opened, so that lower residual voltage is generated, and the residual voltage is reduced by about 50% compared with the product with the same chip area of the conventional structure; the trigger area adopts Deep N-well trigger, so that the consistency of breakdown voltage is good (see the 19-1 position of figure 21); in the invention, other areas except the trigger area are isolated by adopting a Trench structure, so that the junction capacitance is reduced (see the 19-2 position of the attached drawing 21), and the junction capacitance is reduced by more than 50%; the invention performs specialized treatment on the short circuit points of the cathode region step by step, the surge capacity of the device is higher (see figure 22) under the condition of the same area of the chip, and the surge capacity is improved by more than 10%.
The above description of the embodiments is only for aiding in the understanding of the method of the present invention and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the invention can be made without departing from the principles of the invention and these modifications and adaptations are intended to be within the scope of the invention as defined in the following claims.
Claims (6)
1. The low-capacitance low-residual-voltage high-power overvoltage protection device chip is characterized by comprising an N-type monocrystalline silicon wafer (a), wherein a punching region (b) and a trigger region (c) are formed on two sides of the N-type monocrystalline silicon wafer (a) through concentrated phosphorus diffusion, a base region (d) is formed on the front surface and the back surface of the N-type monocrystalline silicon wafer (a) through boron diffusion, an anode region (e) with the depth larger than that of the base region (d) is further arranged on the base region (d), a cathode region (f) is formed by phosphorus diffusion by the anode region (e) on the front surface and the back surface of the N-type monocrystalline silicon wafer (a), a base region (d), an anode region (e), an anode region (f), a punching region (b) and a trigger region (c) are formed on the surfaces of the N-type monocrystalline silicon wafer (a), an inner groove mesa structure (h) is formed between the anode region (e) and the back surface of the N-type monocrystalline silicon wafer (a), a double-sided oxide layer (j) is formed through silicon corrosion, a double-sided glass mesa structure (i) is filled on the inner groove mesa structure (h), and a double-sided silicon oxide film (j) is formed on the surface of the base region (j) and the silicon dioxide film (j) And forming a lead window (k) above the cathode region (f) by photoetching, forming a scribing groove (l) by photoetching on the edges of the two sides of the silicon dioxide protective film (j) and the double-sided oxide layer (g), and arranging a metal layer (m) at the lead window (k).
2. The chip manufacturing process according to claim 1, comprising the steps of:
step 1) growing a layer of silicon dioxide on an N-type monocrystalline silicon wafer through thermal oxidation;
step 2) photoetching a phosphorus-rich region window on the double-sided oxide layer;
step 3) locally diffusing a layer of concentrated phosphorus at high temperature by a liquid phosphorus source diffusion method;
step 4) carrying out concentrated phosphorus re-diffusion at high temperature to form a through region and a trigger region of the device, and simultaneously growing a layer of silicon dioxide on the surface to serve as a masking layer for subsequent diffusion;
step 5) photoetching a diffusion window of an anode region on the double-sided oxide layer;
step 6) pre-diffusing liquid boron sources on the two sides of the silicon wafer at high temperature;
step 7) performing boron re-diffusion at high temperature to form an anode region with a certain depth, and simultaneously growing an oxide layer on the surface of the anode region to serve as a masking layer for subsequent diffusion;
step 8) photoetching a base region diffusion window on the double-sided oxide layer;
step 9), liquid boron source pre-diffusion is carried out on the two sides of the silicon wafer at high temperature to dope the base region;
step 10), performing boron re-diffusion at high temperature to form a base region of the device, and simultaneously growing an oxide layer on the surface of the base region to serve as a masking layer for subsequent diffusion;
step 11), photoetching a short base region of the thyristor and a diffusion window of a boron-supplementing region of a base region of the triode on the front surface oxide layer, and photoetching a diffusion window of an anode region of the thyristor on the back surface oxide layer;
step 12) locally diffusing a layer of concentrated phosphorus at high temperature by a liquid phosphorus source diffusion method;
step 13) carrying out concentrated phosphorus re-diffusion at high temperature to form a cathode region of the device, and simultaneously growing a layer of silicon dioxide on the surface to serve as a masking layer for subsequent photoetching;
step 14), etching a deep groove etching window on the double-sided oxide layer by partial photoetching;
step 15), silicon etching is carried out at the double-sided deep groove etching window to form an inner groove mesa structure;
step 16), filling a glass layer in the inner groove as a final PN junction protection passivation layer;
step 17) depositing a silicon dioxide protective film on the surface by LPCVD;
step 18) photoetching lead windows on the front and back surfaces, and simultaneously cutting scribing grooves on the edges;
step 19) metallizing the front and back surfaces to obtain the chip.
3. The chip manufacturing process according to claim 2, wherein,
the temperature of the thermal oxidation in step 1) is: 1130-1180 ℃ and thickness of the obtained oxide layer: 1.3-1.8 mu m;
the temperature of diffusion in step 3) is: 1100-1160 ℃, R □ =0.6~1.5Ω/□；
The temperature of the concentrated phosphorus diffusion in the step 4) is as follows: 1250 ℃ to 1280 ℃ for a time: 80-150 h, and finally x j =100~150µm；
The temperature of the boron pre-diffusion in step 6) is: 1000-1150 ℃ and time: 100-200 min, R □ =2~6Ω/□；
The temperature of boron re-diffusion in step 7) is: 1250 ℃ to 1280 ℃ for the time of: 50-100 h, and finally x j =50~100µm；
The temperature of the boron pre-diffusion in step 9) is: 900-1000 ℃ and the time is as follows: 60-90 min, R □ =20~40Ω/□；
The temperature of boron re-diffusion in step 10) is: 1220 ℃ to 1260 ℃ for the following time: 6-15 h, final x j =20~40µm；
The temperature of phosphorus diffusion in step 12) is: 1000-1100 ℃ and the time is as follows: 60-120 min, R □ =1.0~2.0Ω/□；
The temperature of the concentrated phosphorus diffusion in step 13) is: 1050 ℃ -1150 ℃ and time: 3-8 hours.
4. The chip manufacturing process according to claim 2, wherein the depth of the groove in step 15) is 30-60 μm.
5. The chip fabrication process of claim 2, wherein step 16) the glass passivation temperature is: 450-720 ℃.
6. The chip manufacturing process according to claim 2, wherein the metal layer in the step 19) is titanium nickel silver, and the thickness is 1-2 μm.
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