CN113161291B - Array substrate manufacturing method and array substrate - Google Patents

Array substrate manufacturing method and array substrate Download PDF

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Publication number
CN113161291B
CN113161291B CN202110377208.5A CN202110377208A CN113161291B CN 113161291 B CN113161291 B CN 113161291B CN 202110377208 A CN202110377208 A CN 202110377208A CN 113161291 B CN113161291 B CN 113161291B
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layer
array substrate
gas
semiconductor layer
semiconductor
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CN113161291A (en
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刘凯军
周佑联
许哲豪
袁海江
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HKC Co Ltd
Beihai HKC Optoelectronics Technology Co Ltd
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HKC Co Ltd
Beihai HKC Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

The application belongs to the technical field of display panels and provides an array substrate manufacturing method and an array substrate, wherein the array substrate manufacturing method comprises the following steps: s1, sequentially manufacturing a semiconductor layer, a metal layer and a light resistance layer on a substrate; s2, processing the metal layer by adopting a wet etching method; s3, exposing and developing the photoresist layer by using the metal layer subjected to the first wet etching as a photomask; s4, removing the region of the semiconductor layer exposed outside the photoresist layer by adopting a dry etching method; s5, processing the metal layer again by adopting a wet etching method to form a data line and a semiconductor tail; the array substrate is manufactured by adopting an array substrate manufacturing method. According to the array substrate manufacturing method and the array substrate, the step S3 is added between the step S2 and the step S4, so that the coverage width of the photoresist layer is reduced, the coverage width of the semiconductor layer is reduced when the semiconductor layer is subjected to dry etching, and the length of a semiconductor tail is effectively shortened.

Description

Array substrate manufacturing method and array substrate
Technical Field
The application belongs to the technical field of display panels, and particularly relates to an array substrate manufacturing method and an array substrate.
Background
With the rapid development of the information age, the display device occupies a very important position in the development process of the information technology, and the display screens on various instruments and meters provide a great deal of information for the daily life and work of people, so that the information technology which is developed rapidly at present cannot exist without the display device. A TFT-LCD (Thin film transistor-liquid crystal display) is widely used in life and work of people due to its characteristics of good brightness, high contrast, strong layering, bright color, simple manufacture, stable performance, etc.
The TFT-LCD is generally formed by attaching an array substrate and a color filter substrate, and a 4Mask (photo Mask) process is usually used in the manufacturing process of the array substrate, and the current 4Mask process generally includes: the structure of the mask is shown in fig. 1, the structure of the mask after exposure and development is shown in fig. 2, the structure of the mask after first dry etching is shown in fig. 3, and the structure of the mask after last wet etching is shown in fig. 4. However, in the process of manufacturing the data line by using the 4Mask process, a small amount of As tail (semiconductor tail, 100 in fig. 4) is formed at the bottom of the data line, since the distance between the semiconductor tail and Acom (common electrode, 15 in fig. 5) cannot be too close, if the distance is too close, crosstalk may be caused, the distance between the data line and the common electrode is determined by the length of the semiconductor tail, and the longer the length of the semiconductor tail, the lower the light penetration rate of the TFT-LCD.
Disclosure of Invention
The present application aims to provide an array substrate manufacturing method and an array substrate, which include but are not limited to solving the technical problem of a long tail of a conventional semiconductor.
The application is realized in such a way, and provides an array substrate manufacturing method, which comprises the following steps:
s1, sequentially manufacturing a semiconductor layer, a metal layer and a light resistance layer on a substrate;
s2, removing the region of the metal layer exposed outside the photoresist layer by adopting a wet etching method;
s3, exposing and developing the photoresist layer by using the metal layer subjected to the first wet etching as a photomask, and removing the region of the photoresist layer exposed outside the metal layer;
s4, removing the region of the semiconductor layer exposed outside the photoresist layer by adopting a dry etching method;
and S5, removing the metal of the metal layer in the channel of the thin film transistor by adopting a wet etching method to form a data line and a semiconductor tail.
In one embodiment, between S3 and S4, there is further included the step of: and performing ashing treatment on the photoresist layer.
In one embodiment, the gas used in the ashing process is oxygen.
In one embodiment, nitrogen trifluoride gas or sulfur hexafluoride gas is mixed in the oxygen gas.
In one embodiment, the flow rate of the oxygen gas is 10000 to 20000sccm, and the flow rate of the nitrogen trifluoride gas or the sulfur hexafluoride gas is 200 to 600sccm.
In one embodiment, the S1 includes the following specific steps:
s11, sequentially depositing a gate insulating layer, an active layer, a doping layer and a metal layer on a substrate with a gate;
s12, coating a positive photoresist material on the metal layer;
and S13, exposing and developing the positive photoresist material by using a half-tone photomask to form a photoresist layer.
In one embodiment, the gas used in the dry etching process is chlorine.
In one embodiment, nitrogen trifluoride gas or sulfur hexafluoride gas is mixed with the chlorine gas.
In one embodiment, the flow rate of the chlorine gas is 4000 to 6000sccm, and the flow rate of the nitrogen trifluoride gas or the sulfur hexafluoride gas is 1000 to 2000sccm.
The application also provides an array substrate which is manufactured by adopting the manufacturing method of the array substrate, the array substrate comprises a substrate, a semiconductor layer, a public electrode and a data line, the semiconductor layer and the public electrode are arranged on the substrate, a gap is formed between the semiconductor layer and the public electrode, and the data line is arranged on the semiconductor layer.
The array substrate manufacturing method and the array substrate provided by the application have the beneficial effects that: by adding the step S3 between the step S2 and the step S4, the metal layer which completes the first wet etching is used as a photomask to expose and develop the photoresist layer, so that the coverage width of the photoresist layer is reduced, and further, the coverage width of the semiconductor layer is reduced when the semiconductor layer is subjected to dry etching, thereby effectively shortening the length of the semiconductor tail, solving the technical problem that the existing semiconductor tail is long, and being beneficial to reducing the distance between the data line and the common electrode and improving the light penetration rate of the display panel.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic view of a partial structure after an exposure and development process in a conventional 4Mask process;
fig. 2 is a schematic partial structure diagram after a first wet etching process in a conventional 4Mask process;
fig. 3 is a schematic view of a partial structure after a first dry etching process in a conventional 4Mask process;
fig. 4 is a schematic partial structure diagram after a second wet etching process in a conventional 4Mask process;
fig. 5 is a schematic partial structure diagram of a display panel according to an embodiment of the present disclosure;
fig. 6 is a process flow diagram of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 7 is a schematic partial structure diagram after a second exposure and development process in the method for manufacturing an array substrate according to the embodiment of the present application;
fig. 8 is a schematic view of a partial structure after ashing in a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 9 is a schematic partial structure diagram after a first dry etching process in the array substrate manufacturing method according to the embodiment of the present application;
fig. 10 is a schematic partial structure diagram after a second wet etching process in the array substrate manufacturing method according to the embodiment of the application.
Wherein, in the figures, the respective reference numerals:
1-array substrate, 2-color film substrate, 3-halftone mask, 11-substrate, 12-semiconductor layer, 13-metal layer, 14-photoresist layer, 15-common electrode, 21-shading area, 100-semiconductor tail, 130-data line.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.
It should be noted that: when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly connected to the other element. When an element is referred to as being "connected" to another element, it can be directly or indirectly connected to the other element. The terms "upper", "lower", "left", "right", and the like, indicate orientations or positional relationships based on those shown in the drawings, are merely for convenience of description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the patent, the specific meaning of which terms will be understood by those skilled in the art according to the particular circumstances. The term "plurality" means two or more unless specifically limited otherwise.
The array substrate manufacturing method provided by the application comprises the following steps:
s1, referring to fig. 1, a semiconductor layer 12, a metal layer 13 and a photoresist layer 14 are sequentially formed on a substrate 11;
s2, referring to fig. 2, the area of the metal layer 13 exposed outside the photoresist layer 14 is removed by wet etching;
s3, referring to fig. 7, exposing and developing the photoresist layer 14 by using the metal layer 13 subjected to the first wet etching as a mask, and removing the region of the photoresist layer 14 exposed outside the metal layer 13;
s4, referring to the graph of FIG. 9, the region of the semiconductor layer 12 exposed outside the photoresist layer 14 is removed by a dry etching method;
s5, referring to fig. 10, the metal layer 13 in the channel (not shown) of the thin film transistor is removed by wet etching to form the data line 130 and the semiconductor tail 100.
Specifically, referring to fig. 1, step S1 includes the following steps:
s11, sequentially depositing a gate insulating layer, an active layer, a doping layer and a metal layer 13 on the substrate 11 with the gate;
s12, coating a positive photoresist material on the metal layer 13;
s13, the positive photoresist material is exposed and developed by using the half-tone mask 3 to form a photoresist layer 14.
The selection of the substrate 11 and the materials and processes required to form the gate electrode, the gate insulating layer, the active layer and the doped layer thereon are conventional in the art, and include: the substrate 11 may be a glass substrate or the like, the gate electrode may be made of a stacked material of Mo (molybdenum) and Cu (copper) or a stacked material of Ti (titanium), mo, and Cu, and the gate insulating layer may be made of SiNx (silicon nitride); preferably, if the material of the gate electrode is a laminated material of Mo and Cu, the thickness of the Mo layer is controlled to be 100-300 angstroms, the thickness of the Cu layer is controlled to be 3000-6000 angstroms, and the thickness of the gate insulating layer is controlled to be 2000-5000 angstroms; the gate electrode can be formed by coating/exposing, developing, wet etching, stripping, etc., and the active layer and the doped layer are generally obtained by depositing a layer of amorphous silicon and doped amorphous silicon with a thickness of 1300 to 2000 angstroms on the gate insulating layer by PECVD method, which will not be described herein.
In the present application, when the positive photoresist material is exposed in step S13, the light source irradiates from top to bottom, and the light emitted from the light source irradiates the positive photoresist material after passing through the halftone mask 3; in step S3, the light source is irradiated from bottom to top, and the light emitted from the light source is irradiated on the positive photoresist material after passing through the substrate 11 and the semiconductor layer 12 in sequence, it can be understood that both the substrate 11 and the semiconductor layer 12 are made of a light-transmitting material; in the steps S2 and S5, namely the first wet etching and the second wet etching, adopted etching solutions are both copper acid; in step S4, the gas used in the dry etching process is chlorine gas, and nitrogen trifluoride gas or sulfur hexafluoride gas may be mixed into the chlorine gas, and since nitrogen trifluoride gas or sulfur hexafluoride gas has excellent etching rate, selectivity (to silicon oxide and silicon) and stability, no residue is left on the surface of the semiconductor layer 12 during etching, so that the surface of the etched semiconductor layer 12 may be more smooth, and in the actual manufacturing process, the flow rate of chlorine gas is 4000 to 6000sccm, and the flow rate of nitrogen trifluoride gas or sulfur hexafluoride gas is 1000 to 2000sccm.
In the array substrate manufacturing method provided by the application, step S3 is added between step S2 and step S4, the metal layer 13 which completes the first wet etching is used as a photomask to expose and develop the photoresist layer 14, so that the coverage width of the photoresist layer 14 is reduced, and further the coverage width of the semiconductor layer 12 is reduced when the semiconductor layer 12 is dry etched, thereby effectively shortening the length of the semiconductor tail 100, solving the technical problem of longer existing semiconductor tail, and being beneficial to reducing the distance between the data line 130 and the common electrode 15 (see fig. 5) and improving the light penetration rate of the display panel.
Optionally, referring to fig. 8, as a specific embodiment of the array substrate manufacturing method provided in the present application, a step between step S3 and step S4 is further included: the photoresist layer 14 is subjected to ashing treatment. Specifically, the gas used for the ashing treatment is oxygen, and nitrogen trifluoride gas or sulfur hexafluoride gas can be mixed into the oxygen, and in the actual process, the flow rate of the oxygen is 10000-20000sccm, the flow rate of the nitrogen trifluoride gas or sulfur hexafluoride gas is 200-600sccm, and the process flow and other process parameters involved in the ashing treatment are conventional technical means in the field, and are not described herein again. The ashing process for the photoresist layer 14 can further reduce the coverage width of the photoresist layer 14, so that the photoresist layer 14 does not block the etching gas to etch the semiconductor layer 14 when the dry etching of the semiconductor layer 12 is performed, thereby further shortening the length of the semiconductor tail 100.
Referring to fig. 5, fig. 6 and fig. 10, the array substrate 1 provided in the present application is manufactured by the above-mentioned manufacturing method of the array substrate, and the array substrate 1 includes a substrate 11, a semiconductor layer 12, a common electrode 15 and a data line 130, wherein the semiconductor layer 12 and the common electrode 15 are disposed on the substrate 11, a gap is formed between the semiconductor layer 12 and the common electrode 15, and the data line 130 is disposed on the semiconductor layer 12. Specifically, the array substrate 1 and the color filter substrate 2 are bonded to form a display panel, wherein a light-shielding region 21 is disposed on the color filter substrate 2, and the position of the light-shielding region 21 corresponds to the data line 130 and the gap between the data line 130 and the common electrode 15, and is used for shielding the data line 130 and preventing light leakage from the gap, the longer the length of the semiconductor tail 100 is, the larger the gap between the data line 130 and the common electrode 15 is, the larger the width of the light-shielding region 21 needs to be, and thus the light transmittance of the display panel is reduced.
The array substrate 1 provided by the application is manufactured by using an array substrate manufacturing method, the step S3 is added between the step S2 and the step S4, the metal layer 13 which completes the first wet etching is used as a photomask to expose and develop the photoresist layer 14, so that the coverage width of the photoresist layer 14 is reduced, the coverage width of the semiconductor layer 12 is reduced when the semiconductor layer 12 is subjected to dry etching, the length of the semiconductor tail 100 is effectively shortened, the technical problem that the existing semiconductor tail is long is solved, and the reduction of the distance between the data line 130 and the common electrode 15 and the improvement of the light penetration rate of the display panel are facilitated. In addition, for the Array substrate 1 manufactured by using the GOA (Gate Driver on Array) technology, the distance between the data lines 130 can be reduced due to the reduction of the length of the semiconductor tail 100, so that the layout space of the GOA circuit can be increased, the width of the frame of the Array substrate 1 can be reduced, and the design and development of a narrow-frame display panel can be facilitated.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (6)

1. The manufacturing method of the array substrate is characterized by comprising the following steps of:
s1, sequentially manufacturing a semiconductor layer, a metal layer and a light resistance layer on a substrate;
s2, removing the region of the metal layer exposed outside the light resistance layer by adopting a wet etching method;
s3, exposing and developing the photoresist layer by using the metal layer subjected to the first wet etching as a photomask, and removing the region of the photoresist layer exposed outside the metal layer;
s4, removing the region of the semiconductor layer exposed outside the photoresist layer by adopting a dry etching method;
s5, removing the metal of the metal layer in the channel of the thin film transistor by adopting a wet etching method to form a data line and a semiconductor tail;
the S1 comprises the following specific steps:
s11, sequentially depositing a gate insulating layer, an active layer, a doping layer and a metal layer on a substrate with a gate;
s12, coating a positive photoresist material on the metal layer;
s13, exposing and developing the positive photoresist material by adopting a half-tone photomask to form a photoresist layer;
in step S3, a light source irradiates from bottom to top, and light emitted by the light source irradiates on the positive photoresist material after passing through the substrate and the semiconductor layer in sequence; wherein, the substrate and the semiconductor layer are both made of light-transmitting materials;
in step S4, the gas used in the dry etching method is chlorine;
nitrogen trifluoride gas or sulfur hexafluoride gas is mixed in the chlorine;
the flow rate of the chlorine gas is 4000-6000sccm, and the flow rate of the nitrogen trifluoride gas or the sulfur hexafluoride gas is 1000-2000sccm.
2. The method for manufacturing the array substrate according to claim 1, further comprising between the step S3 and the step S4: and performing ashing treatment on the photoresist layer.
3. The method for manufacturing an array substrate according to claim 2, wherein the gas used in the ashing process is oxygen.
4. The method of claim 3, wherein nitrogen trifluoride gas or sulfur hexafluoride gas is mixed in the oxygen gas.
5. The method of claim 4, wherein the flow rate of the oxygen gas is 10000-20000sccm, and the flow rate of the nitrogen trifluoride gas or the sulfur hexafluoride gas is 200-600sccm.
6. An array substrate, characterized in that, the array substrate is manufactured by the method of any one of claims 1 to 5, the array substrate comprises a substrate, a semiconductor layer, a common electrode and a data line, the semiconductor layer and the common electrode are arranged on the substrate, a gap is arranged between the semiconductor layer and the common electrode, and the data line is arranged on the semiconductor layer.
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