CN113161244A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN113161244A
CN113161244A CN202110452914.1A CN202110452914A CN113161244A CN 113161244 A CN113161244 A CN 113161244A CN 202110452914 A CN202110452914 A CN 202110452914A CN 113161244 A CN113161244 A CN 113161244A
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layer
substrate
pad
bonding
semiconductor structure
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曹光龙
梁栋
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Chen Chen Technology Co ltd
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Chen Chen Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13562—On the entire exposed surface of the core
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13575—Plural coating layers
    • H01L2224/1358—Plural coating layers being stacked
    • H01L2224/13582—Two-layer coating
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13611—Tin [Sn] as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body

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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present disclosure provides a semiconductor device and a method of manufacturing the same. The manufacturing method comprises the following steps: providing a first semiconductor structure, the first semiconductor structure comprising: the semiconductor device comprises a first substrate, a first bonding pad layer on the first substrate and a passivation layer on the first substrate and exposing the first bonding pad layer; forming a sacrificial layer covering the passivation layer, wherein the sacrificial layer exposes the first pad layer; forming a first bonding layer covering the first semiconductor structure, the first bonding layer including a metal barrier layer on the first pad layer and an oxidation resistant layer on the metal barrier layer; removing the sacrificial layer and one part of the first bonding layer on the sacrificial layer, and reserving the other part of the first bonding layer on the first pad layer; providing a second semiconductor structure, the second semiconductor structure comprising: a second substrate and a second pad layer in the second substrate; forming a second bonding layer on the second pad layer; and bonding the first bonding layer to the second bonding layer to interface the first semiconductor structure to the second semiconductor structure.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor device and a method for manufacturing the same.
Background
In the conventional semiconductor process, during the process of forming a Flip Chip (Flip Chip), a solder ball (solder ball) or a copper pillar and a solder ball (solder pillar + solder ball) need to be grown on a wafer pad, and then a die is Flip-Chip mounted on a substrate to form a reliable solder joint by a reflow soldering method.
For the above welding process, to achieve the welding between the die pad and the substrate pad, a ball planting process is required to be performed on the die pad to form a solder ball or a copper pillar and a solder ball, and then the solder ball is welded with the substrate pad. The process has multiple steps and complicated process, and the production efficiency is low. And because of the defect problem of the ball planting process, the cost lost by manufacturers every year is huge. At this stage, the wafer process is completed, and the product cost is fully invested, so the reduction of the yield in ball-planting fabrication greatly increases the manufacturing cost.
Disclosure of Invention
The technical problem that this disclosure solved is: a method for manufacturing a semiconductor device is provided to improve production efficiency and reduce cost.
According to an aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: providing a first semiconductor structure, the first semiconductor structure comprising: the chip comprises a first substrate, a first bonding pad layer on the first substrate and a passivation layer which is arranged on the first substrate and exposes the first bonding pad layer; forming a sacrificial layer covering the passivation layer, wherein the sacrificial layer exposes the first pad layer; forming a first bonding layer overlying the first semiconductor structure after forming the sacrificial layer, wherein the first bonding layer includes a metal barrier layer on the first pad layer and an oxidation resistant layer on the metal barrier layer; after the first bonding layer is formed, removing the sacrificial layer and a part of the first bonding layer on the sacrificial layer, and remaining another part of the first bonding layer on the first pad layer; providing a second semiconductor structure, the second semiconductor structure comprising: a second substrate and a second pad layer in the second substrate; forming a second bonding layer on the second pad layer; and bonding the first bonding layer to the second bonding layer to interface the first semiconductor structure to the second semiconductor structure.
In some embodiments, the passivation layer covers a portion of the first pad layer and the first substrate, the passivation layer having an opening exposing another portion of the first pad layer, wherein a portion of the first bonding layer is formed in the opening in the step of forming the first bonding layer.
In some embodiments, a surface of the sacrifice layer on a side away from the first substrate is higher than a surface of the first pad layer on a side away from the first substrate.
In some embodiments, the first bonding layer is formed using an evaporation or plating process.
In some embodiments, the material of the first substrate comprises gallium arsenide; the material of the passivation layer comprises gallium nitride; the second substrate includes a printed circuit board or a ceramic substrate.
In some embodiments, the material of the first pad layer comprises gold; the material of the second pad layer comprises nickel and gold, or comprises nickel, palladium and gold; the material of the second bonding layer includes tin.
In some embodiments, the sacrificial layer comprises a photoresist layer; the metal barrier layer is a nickel layer; the anti-oxidation layer is a tin layer, or comprises a gold layer on the metal barrier layer and a tin layer on the gold layer.
In some embodiments, the metallic barrier layer has a thickness in the range of 4600 angstroms to 5000 angstroms.
In some embodiments, in the step of providing the first semiconductor structure, a plurality of first semiconductor structures are provided; the second semiconductor structure includes a plurality of second pad layers in the second substrate; in the step of butting the first semiconductor structure to the second semiconductor structure, the plurality of first semiconductor structures and the plurality of second pad layers are butted correspondingly.
In some embodiments, the method of manufacturing further comprises: forming an insulating layer covering the plurality of first semiconductor structures after the first semiconductor structure is butted with the second semiconductor structure; and performing a dicing process on the insulating layer and the second substrate to obtain a plurality of semiconductor devices, each semiconductor device including one first semiconductor structure and a portion of the second substrate.
According to another aspect of the present disclosure, there is provided a semiconductor device including: a first semiconductor structure, the first semiconductor structure comprising: a first substrate; a first pad layer on the first substrate; a passivation layer on the first substrate and exposing the first pad layer; and a first bonding layer on the first pad layer, the first bonding layer including a metal barrier layer on the first pad layer and an oxidation resistant layer on the metal barrier layer; and a second semiconductor structure interfacing with the first semiconductor structure, the second semiconductor structure comprising: a second substrate; a second pad layer in the second substrate; and a second bonding layer on the second pad layer; wherein the first bonding layer is bonded to the second bonding layer.
In some embodiments, the passivation layer covers a portion of the first pad layer and the first substrate, the passivation layer having an opening exposing another portion of the first pad layer, wherein a portion of the first bonding layer is located in the opening.
In some embodiments, the material of the first substrate comprises gallium arsenide; the material of the passivation layer comprises gallium nitride; the second substrate includes a printed circuit board or a ceramic substrate.
In some embodiments, the material of the first pad layer comprises gold; the material of the second pad layer comprises nickel and gold, or comprises nickel, palladium and gold; the material of the second bonding layer includes tin.
In some embodiments, the metal barrier layer is a nickel layer; the anti-oxidation layer is a tin layer, or comprises a gold layer on the metal barrier layer and a tin layer on the gold layer.
In some embodiments, the metallic barrier layer has a thickness in the range of 4600 angstroms to 5000 angstroms.
The manufacturing method does not adopt the ball planting process in the prior art and does not form the copper column and the solder ball, so the manufacturing method has simpler process, thereby improving the production efficiency and reducing the cost.
Other features of the present disclosure and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.
The present disclosure may be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:
fig. 1 is a flowchart illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure;
FIG. 2 is a cross-sectional schematic diagram illustrating a structure at one stage in the fabrication of a semiconductor device according to one embodiment of the present disclosure;
FIG. 3 is a schematic cross-sectional view illustrating a structure at another stage in the fabrication of a semiconductor device according to one embodiment of the present disclosure;
FIG. 4 is a cross-sectional schematic diagram illustrating a structure at another stage in the fabrication of a semiconductor device according to one embodiment of the present disclosure;
FIG. 5 is a schematic cross-sectional view illustrating a structure at another stage in the fabrication of a semiconductor device according to one embodiment of the present disclosure;
FIG. 6 is a cross-sectional schematic diagram illustrating a structure at another stage in the fabrication of a semiconductor device according to one embodiment of the present disclosure;
FIG. 7 is a cross-sectional schematic diagram illustrating a structure at another stage in the fabrication of a semiconductor device according to one embodiment of the present disclosure;
FIG. 8 is a schematic cross-sectional view illustrating a structure at another stage in the fabrication of a semiconductor device according to one embodiment of the present disclosure;
fig. 9 is a schematic cross-sectional view illustrating a structure at another stage in the fabrication process of a semiconductor device according to one embodiment of the present disclosure.
It should be understood that the dimensions of the various parts shown in the figures are not drawn to scale. Further, the same or similar reference numerals denote the same or similar components.
Detailed Description
Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the disclosure, its application, or uses. The present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that: the relative arrangement of parts and steps, the composition of materials, numerical expressions and numerical values set forth in these embodiments are to be construed as merely illustrative, and not as limitative, unless specifically stated otherwise.
The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element preceding the word covers the element listed after the word, and does not exclude the possibility that other elements are also covered. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
In the present disclosure, when a specific device is described as being located between a first device and a second device, there may or may not be intervening devices between the specific device and the first device or the second device. When a particular device is described as being coupled to other devices, that particular device may be directly coupled to the other devices without intervening devices or may be directly coupled to the other devices with intervening devices.
All terms (including technical or scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs unless specifically defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
Fig. 1 is a flowchart illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure. Fig. 2-9 are cross-sectional schematic diagrams illustrating structures at several stages in the fabrication of a semiconductor device according to some embodiments of the present disclosure. Methods of fabricating semiconductor devices according to some embodiments of the present disclosure are described in detail below in conjunction with fig. 1 and 2-9.
As shown in fig. 1, in step S102, a first semiconductor structure is provided, the first semiconductor structure including: the semiconductor device includes a first substrate, a first pad layer on the first substrate, and a passivation layer on the first substrate and exposing the first pad layer.
As shown in fig. 2, a first semiconductor structure 210 is provided. The first semiconductor structure 210 includes: the first substrate 211, the first pad layer 212 on the first substrate 211, and the passivation layer 213 on the first substrate 211 and exposing the first pad layer 212. For example, as shown in fig. 2, a passivation layer 210 covers a portion of the first pad layer 212 and the first substrate 211. The passivation layer 210 has an opening (may be referred to as a first opening) 2130 exposing another portion of the first pad layer 212. The passivation layer may function to protect circuitry or components on the first substrate.
Preferably, the material of the first substrate 211 includes gallium arsenide or the like. That is, the method of the present disclosure is applicable to processes in which gallium arsenide is used as a substrate. Of course, the material of the first substrate may also be other materials, such as silicon, as will be appreciated by those skilled in the art.
Preferably, the material of the passivation layer comprises gallium nitride. The gallium nitride material is used as a passivation layer to be formed on the first substrate made of gallium arsenide material, so that the passivation layer is matched with the first substrate.
In some embodiments, the material of the first pad layer 212 includes gold or the like.
It should be noted that, although fig. 2 shows 2 first pad layers 212, the scope of the present disclosure is not limited thereto. The number of the first pad layers may be 1 or more than 2. For example, the number of the first pad layers may be 3, 4, or more, and the number of the first pad layers may be determined as needed.
In some embodiments, an inspection may be performed on the first semiconductor structure to confirm whether the first semiconductor structure has an abnormality or defect.
Returning to fig. 1, in step S104, a sacrificial layer covering the passivation layer is formed, the sacrificial layer exposing the first pad layer.
As shown in fig. 3, a patterned sacrificial layer 214 covering the passivation layer 213 is formed, for example, by exposure and development, and the sacrificial layer 214 exposes the first pad layer 212. For example, the sacrificial layer 214 may comprise a photoresist layer. The sacrificial layer 214 has an opening (may be referred to as a second opening) 2140 exposing the first pad layer 212.
In some embodiments, a surface of the sacrificial layer 214 on a side away from the first substrate 211 is higher than a surface of the first pad layer 212 on a side away from the first substrate 211.
Returning to fig. 1, after forming the sacrificial layer, a first bonding layer covering the first semiconductor structure is formed, wherein the first bonding layer includes a metal barrier layer on the first pad layer and an oxidation resistant layer on the metal barrier layer, at step S106.
For example, as shown in fig. 4, the first bonding layer 311 covering the first semiconductor structure 210 is formed using an evaporation or plating process. The first bonding layer 311 includes a metal barrier layer 215 on the first pad layer 212 and an oxidation resistant layer 216 on the metal barrier layer 215. In the step of forming the first bonding layer, a part of the first bonding layer 311 is formed in the opening 2130.
For example, the metal barrier layer 215 may be a nickel layer. For example, the oxidation resistant layer 216 may be a tin layer, or the oxidation resistant layer 216 may include a gold layer on a metal barrier layer and a tin layer on the gold layer. The metal barrier layer can prevent tin materials from replacing gold materials used as the first pad layer, and prevent tin from flowing along gold lines. The anti-oxidation layer can prevent the nickel layer from being oxidized, thereby preventing the subsequent tin coating process from being influenced. Moreover, tin is used as an oxidation resistant layer, so that the nickel layer can be well prevented from being oxidized, and the tin can also be used as a welding bonding layer to achieve a good welding effect in a subsequent bonding process.
In some embodiments, metallic barrier layer 215 has a thickness in the range of 4600 angstroms to 5000 angstroms. The metal barrier layer with the thickness range can well prevent tin from replacing gold, and has good conduction effect due to relatively low resistance.
Returning to fig. 1, after the first bonding layer is formed, the sacrificial layer and a portion of the first bonding layer on the sacrificial layer are removed, and another portion of the first bonding layer on the first pad layer remains at step S108.
For example, as shown in fig. 5, after the first bonding layer is formed, the sacrificial layer 214 and a portion of the first bonding layer 311 on the sacrificial layer 214 are removed, and a portion of the first bonding layer 311 on the first pad layer 212 remains.
Returning to fig. 1, in step S110, a second semiconductor structure is provided, the second semiconductor structure comprising: a second substrate and a second pad layer in the second substrate.
For example, as shown in fig. 6, a second semiconductor structure 220 is provided, the second semiconductor structure 220 comprising: a second substrate 221 and a second pad layer 222 in the second substrate 221. For example, the second substrate 221 may include a Printed Circuit Board (PCB). For another example, the second substrate may include a ceramic base plate.
In some embodiments, the material of the second pad layer 222 includes nickel and gold, or nickel, palladium, and gold. For example, the second pad layer 222 may include a nickel layer and a gold layer on the nickel layer; alternatively, the second pad layer 222 may include a nickel layer, a palladium layer on the nickel layer, and a gold layer on the palladium layer. Here, the gold layer serves as the uppermost layer of the second pad layer.
Returning to fig. 1, in step S112, a second bonding layer is formed on the second pad layer.
For example, as shown in fig. 6, a second bonding layer 223 is formed on the second pad layer 222 using a steel screen printing process. For example, the material of the second bonding layer 223 includes tin. Using tin as the second bonding layer can serve to connect the first semiconductor structure and the second semiconductor structure and form conduction.
In some embodiments, the second bonding layer may have a thickness in a range from 37 micrometers to 75 micrometers.
Returning to fig. 1, at step S114, the first bonding layer is bonded to the second bonding layer to interface the first semiconductor structure to the second semiconductor structure.
For example, as shown in fig. 7, a solder reflow process may be employed to join the first bonding layer 311 and the second bonding layer 223, thereby interfacing the first semiconductor structure 210 with the second semiconductor structure 220. This realizes SMT (Surface Mounted Technology) mounting Technology.
Thus, methods of fabricating semiconductor devices according to some embodiments of the present disclosure are provided. The manufacturing method comprises the following steps: providing a first semiconductor structure, the first semiconductor structure comprising: the semiconductor device comprises a first substrate, a first bonding pad layer on the first substrate and a passivation layer on the first substrate and exposing the first bonding pad layer; forming a sacrificial layer covering the passivation layer, the sacrificial layer exposing the first pad layer; forming a first bonding layer covering the first semiconductor structure after forming the sacrificial layer, wherein the first bonding layer includes a metal barrier layer on the first pad layer and an oxidation resistant layer on the metal barrier layer; after the first bonding layer is formed, removing the sacrificial layer and one part of the first bonding layer, which is positioned on the sacrificial layer, and reserving the other part of the first bonding layer, which is positioned on the first pad layer; providing a second semiconductor structure, the second semiconductor structure comprising: a second substrate and a second pad layer in the second substrate; forming a second bonding layer on the second pad layer; and bonding the first bonding layer to the second bonding layer to interface the first semiconductor structure to the second semiconductor structure. The manufacturing method is a simple and optimized wafer processing and packaging method. The manufacturing method does not adopt the ball planting process in the prior art, and does not form the copper column and the solder ball, so that the process steps of the solder medium between the crystal grain bonding pad (namely the first bonding pad layer) and the substrate bonding pad (namely the second bonding pad layer) can be reduced, therefore, the process of the manufacturing method is simpler, and the production efficiency can be improved and the cost can be reduced.
In some embodiments, in the step of providing a first semiconductor structure, a plurality of first semiconductor structures are provided. The plurality of first semiconductor structures are a plurality of independent first semiconductor structures spaced apart from each other. In some embodiments, as shown in fig. 6, the second semiconductor structure may include a plurality of second pad layers 222 in the second substrate 221. In the step of butting the first semiconductor structure with the second semiconductor structure, the plurality of first semiconductor structures and the plurality of second pad layers are correspondingly butted respectively, as shown in fig. 7.
In some embodiments, the manufacturing method may further include: as shown in fig. 8, after the first semiconductor structure is butted with the second semiconductor structure, an insulating layer 410 covering the plurality of first semiconductor structures 210 is formed. For example, the insulating layer 410 may be an organic insulating layer (e.g., resin, etc.). The insulating layer 410 may function as a seal. The insulating layer 410 may be formed, for example, using a molding process.
In some embodiments, the manufacturing method may further include: as shown in fig. 9, a dicing process is performed on the insulating layer and the second substrate to obtain a plurality of semiconductor devices each including one of the first semiconductor structures 210 and a portion of the second substrate 221.
Thus, methods of fabricating semiconductor devices according to other embodiments of the present disclosure are provided. By the manufacturing method, a plurality of semiconductor devices can be formed at the same time, the production efficiency is improved, and the reliability of the packaged product can be ensured.
A semiconductor device is formed by the above manufacturing method. Semiconductor devices according to some embodiments of the present disclosure are described below in conjunction with fig. 9.
As shown in fig. 9, the semiconductor device includes a first semiconductor structure 210 and a second semiconductor structure 220 interfacing with the first semiconductor structure 210.
The first semiconductor structure 210 includes: a first substrate 211; a first pad layer 212 on the first substrate 211; a passivation layer 213 on the first substrate 212 and exposing the first pad layer 212; and a first bonding layer 311 on the first pad layer 212. The first bonding layer 311 includes a metal barrier layer 215 on the first pad layer 212 and an oxidation resistant layer 216 on the metal barrier layer 215.
The second semiconductor structure 220 includes: a second substrate 221; a second pad layer 222 in the second substrate 221; and a second bonding layer 223 on the second pad layer 222. Here, the first bonding layer 311 is bonded to the second bonding layer 223.
Thus, a semiconductor device according to some embodiments of the present disclosure is provided. The semiconductor device has a simple structure, and can improve production efficiency and reduce cost.
In some embodiments, the passivation layer 213 covers a portion of the first pad layer 212 and the first substrate 211. The passivation layer 213 has an opening 2130 exposing another portion of the first pad layer 212. A part of the first bonding layer 311 is located in the opening.
Preferably, the material of the first substrate 211 may include gallium arsenide.
Preferably, the material of the passivation layer 213 may include gallium nitride.
Preferably, the second substrate 221 may include a printed circuit board or a ceramic substrate.
In some embodiments, the material of the first pad layer 212 includes gold.
In some embodiments, the material of the second pad layer 222 includes nickel and gold, or includes nickel, palladium, and gold.
In some embodiments, the material of the second bonding layer 223 includes tin.
In some embodiments, the metallic barrier layer 215 may be a nickel layer.
In some embodiments, the oxidation barrier layer 216 may be a tin layer, or may include a gold layer on the metallic barrier layer 215 and a tin layer on the gold layer.
In some embodiments, the metallic barrier layer 215 may range in thickness from 4600 angstroms to 5000 angstroms.
In some embodiments, as shown in fig. 9, the semiconductor device may further include an insulating layer 410 covering the first semiconductor structure 210.
Thus, various embodiments of the present disclosure have been described in detail. Some details that are well known in the art have not been described in order to avoid obscuring the concepts of the present disclosure. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.
Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. It will be understood by those skilled in the art that various changes may be made in the above embodiments or equivalents may be substituted for elements thereof without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims (16)

1. A method of manufacturing a semiconductor device, comprising:
providing a first semiconductor structure, the first semiconductor structure comprising: the chip comprises a first substrate, a first bonding pad layer on the first substrate and a passivation layer which is arranged on the first substrate and exposes the first bonding pad layer;
forming a sacrificial layer covering the passivation layer, wherein the sacrificial layer exposes the first pad layer;
forming a first bonding layer overlying the first semiconductor structure after forming the sacrificial layer, wherein the first bonding layer includes a metal barrier layer on the first pad layer and an oxidation resistant layer on the metal barrier layer;
after the first bonding layer is formed, removing the sacrificial layer and a part of the first bonding layer on the sacrificial layer, and remaining another part of the first bonding layer on the first pad layer;
providing a second semiconductor structure, the second semiconductor structure comprising: a second substrate and a second pad layer in the second substrate;
forming a second bonding layer on the second pad layer; and
bonding the first bonding layer to the second bonding layer to interface the first semiconductor structure to the second semiconductor structure.
2. The manufacturing method according to claim 1,
the passivation layer covering a portion of the first pad layer and the first substrate, the passivation layer having an opening exposing another portion of the first pad layer,
wherein in the step of forming the first bonding layer, a part of the first bonding layer is formed in the opening.
3. The manufacturing method according to claim 2,
the surface of the sacrifice layer at the side far away from the first substrate is higher than the surface of the first pad layer at the side far away from the first substrate.
4. The manufacturing method according to claim 1, wherein the first bonding layer is formed by an evaporation or plating process.
5. The manufacturing method according to claim 1,
the material of the first substrate comprises gallium arsenide;
the material of the passivation layer comprises gallium nitride;
the second substrate includes a printed circuit board or a ceramic substrate.
6. The manufacturing method according to claim 1,
the material of the first pad layer comprises gold;
the material of the second pad layer comprises nickel and gold, or comprises nickel, palladium and gold;
the material of the second bonding layer includes tin.
7. The manufacturing method according to claim 1,
the sacrificial layer comprises a light resistance layer;
the metal barrier layer is a nickel layer;
the anti-oxidation layer is a tin layer, or comprises a gold layer on the metal barrier layer and a tin layer on the gold layer.
8. The method of manufacturing of claim 1, wherein the metallic barrier layer has a thickness ranging from 4600 to 5000 angstroms.
9. The manufacturing method according to claim 1,
in the step of providing the first semiconductor structure, providing a plurality of first semiconductor structures;
the second semiconductor structure includes a plurality of second pad layers in the second substrate;
in the step of butting the first semiconductor structure to the second semiconductor structure, the plurality of first semiconductor structures and the plurality of second pad layers are butted correspondingly.
10. The manufacturing method according to claim 9, further comprising:
forming an insulating layer covering the plurality of first semiconductor structures after the first semiconductor structure is butted with the second semiconductor structure; and
performing a dicing process on the insulating layer and the second substrate to obtain a plurality of semiconductor devices, each semiconductor device including one first semiconductor structure and a portion of the second substrate.
11. A semiconductor device, comprising:
a first semiconductor structure, the first semiconductor structure comprising:
a first substrate;
a first pad layer on the first substrate;
a passivation layer on the first substrate and exposing the first pad layer; and
a first bonding layer on the first pad layer, the first bonding layer comprising
A metal barrier layer on the first pad layer and an anti-oxidation layer on the metal barrier layer; and
a second semiconductor structure interfaced with the first semiconductor structure, the second semiconductor structure comprising:
a second substrate;
a second pad layer in the second substrate; and
a second bonding layer on the second pad layer;
wherein the first bonding layer is bonded to the second bonding layer.
12. The semiconductor device of claim 11,
the passivation layer covers a portion of the first pad layer and the first substrate, and has an opening exposing another portion of the first pad layer, wherein a portion of the first bonding layer is in the opening.
13. The semiconductor device of claim 11,
the material of the first substrate comprises gallium arsenide;
the material of the passivation layer comprises gallium nitride;
the second substrate includes a printed circuit board or a ceramic substrate.
14. The semiconductor device of claim 11,
the material of the first pad layer comprises gold;
the material of the second pad layer comprises nickel and gold, or comprises nickel, palladium and gold;
the material of the second bonding layer includes tin.
15. The semiconductor device of claim 11,
the metal barrier layer is a nickel layer;
the anti-oxidation layer is a tin layer, or comprises a gold layer on the metal barrier layer and a tin layer on the gold layer.
16. The semiconductor device of claim 11, wherein the metallic barrier layer has a thickness ranging from 4600 angstroms to 5000 angstroms.
CN202110452914.1A 2021-04-26 2021-04-26 Semiconductor device and method for manufacturing the same Withdrawn CN113161244A (en)

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Citations (4)

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Publication number Priority date Publication date Assignee Title
US4706377A (en) * 1986-01-30 1987-11-17 United Technologies Corporation Passivation of gallium arsenide by nitrogen implantation
JP2000022027A (en) * 1998-06-29 2000-01-21 Sony Corp Semiconductor device, manufacture thereof, and package board
CN101645407A (en) * 2008-08-04 2010-02-10 中芯国际集成电路制造(上海)有限公司 Under bump metal layer, wafer level chip scale package structure and forming method thereof
US20190006312A1 (en) * 2017-07-01 2019-01-03 International Business Machines Corporation Lead-free solder joining of electronic structures

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4706377A (en) * 1986-01-30 1987-11-17 United Technologies Corporation Passivation of gallium arsenide by nitrogen implantation
JP2000022027A (en) * 1998-06-29 2000-01-21 Sony Corp Semiconductor device, manufacture thereof, and package board
CN101645407A (en) * 2008-08-04 2010-02-10 中芯国际集成电路制造(上海)有限公司 Under bump metal layer, wafer level chip scale package structure and forming method thereof
US20190006312A1 (en) * 2017-07-01 2019-01-03 International Business Machines Corporation Lead-free solder joining of electronic structures

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