CN113158604B

CN113158604B - Time sequence analysis method and device based on physical routing division, equipment and medium

Info

Publication number: CN113158604B
Application number: CN202110482164.2A
Authority: CN
Inventors: 赵凯; 杜华斌; 王鑫鑫; 周彪
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2021-04-30
Filing date: 2021-04-30
Publication date: 2023-11-17
Anticipated expiration: 2041-04-30
Also published as: CN113158604A

Abstract

The present disclosure provides a time sequence analysis method and apparatus, and a device and medium based on physical routing division, the method includes: acquiring a clock path structure based on the gate-level netlist, wherein the clock path structure comprises a clock interconnection line, a target clock driving unit and at least two target clock end point units; performing physical routing division on the clock interconnection line to obtain a plurality of physical sub-nodes and physical sub-line segments so as to obtain physical connection relation data; based on the physical connection relation data and logic connection data included in the gate-level netlist, clock delay data corresponding to a plurality of physical segments and physical nodes respectively are generated through simulation; based on the clock delay data of the common physical segment and the common physical segment, an excess pessimistic amount generated by the common physical path is removed to obtain the clock delay data of the clock path structure. The method can remove the excessive pessimistic quantity generated by the common physical path, reduce clock deviation and improve the accuracy of timing sequence convergence.

Description

Time sequence analysis method and device based on physical routing division, equipment and medium

Technical Field

The embodiment of the disclosure relates to a time sequence analysis method and device based on physical routing division, equipment and medium.

Background

The digital integrated circuit is divided into two stages of front end design and back end design according to a design flow, the front end design completes circuit system top layer framework selection and main function module division according to user requirements and product function index definition, circuit design is completed through a high-level circuit modeling language, and circuit logic synthesis is completed through an integrated circuit front end design tool in combination with circuit design constraint, so that a gate level netlist is obtained. In addition to code design, front-end design also requires behavior-level verification and gate-level verification of the code to be completed, and design for testability, power consumption control optimization, etc. of the circuit to be completed according to requirements.

The back-end design of the integrated circuit is also called physical design, and is based on the gate-level netlist obtained by the front-end design, the layout and the wiring of the circuit are completed, the circuit layout is realized, and the verification of the layout is completed. For example, back-end (physical) design is a process of creating a physical circuit representation corresponding to a netlist, and the design results need to satisfy: first, various limitations of chip processing; second, acceptable design cycles; thirdly, verification and simulation of the result after layout design are required to meet the requirements (such as time sequence) on design performance indexes.

Back-end (physical) designs can be considered as physical representations (topologies) of a circuit netlist, i.e., a complex set of structures of transistors, interconnect lines, and other circuit basic cells that are built and connected together on a chip. Major variables for backend design include, but are not limited to: how to solve the time delay problem of chip interconnection lines and a method for controlling the time delay of the interconnection lines. The time delay of the interconnect lines has become an important factor affecting the chip performance.

Disclosure of Invention

At least one embodiment of the present disclosure provides a timing analysis method based on physical routing division, including: acquiring a clock path structure to be analyzed based on a gate-level netlist for integrated circuit design, wherein the clock path structure comprises a clock interconnection line, a target clock driving unit and at least two target clock end units, wherein the target clock driving unit and the at least two target clock end units are connected through the clock interconnection line; performing physical routing division on the clock interconnection line to obtain a plurality of physical sub-nodes and a plurality of physical sub-segments separated by the physical sub-nodes so as to obtain physical connection relation data between the target clock driving unit and the at least two target clock end units, wherein the physical sub-segments and the physical sub-nodes respectively comprise a common physical sub-segment and a common physical sub-node corresponding to a common physical path of the at least two target clock end units; based on the physical connection relation data and logic connection data included in the gate-level netlist, clock delay data respectively corresponding to the physical segments and the physical nodes are generated through simulation; based on the common physical segment and the clock delay data of the common physical segment, an excess pessimistic amount generated by the common physical path is removed to obtain the clock delay data of the clock path structure.

For example, in a timing analysis method provided in at least one embodiment of the present disclosure, the target clock driving unit includes: one or more of the plurality of clock driving units in series and/or parallel.

For example, in a timing analysis method provided in at least one embodiment of the present disclosure, generating clock delay data corresponding to the plurality of physical segments and the plurality of physical nodes, respectively, by simulation includes: respectively extracting parasitic resistance data and parasitic capacitance data of the plurality of physical branch lines and parasitic resistance data and parasitic capacitance data of the plurality of physical branch nodes to obtain parasitic parameter data; based on the logic connection line data, the physical connection relation data and the parasitic parameter data, clock delay data corresponding to the physical segments and the physical nodes respectively are generated in a simulation mode under different excitation.

For example, in one timing analysis method provided by at least one embodiment of the present disclosure, the different stimuli include: input signals from low level to high level based on different signal transition times, or input signals from high level to low level based on different signal transition times.

For example, in a timing analysis method provided by at least one embodiment of the present disclosure, removing an excessive pessimistic amount P generated by the common physical path based on clock delay data of the common physical segment and the common physical segment to obtain clock delay data of the clock path structure includes: acquiring the logic connection line data, the physical connection relation data and clock delay data which are generated by simulation and respectively correspond to the physical segments and the physical nodes; calculating clock delay data corresponding to the common physical path by using the clock delay data of the common physical branch line segment and the common physical branch node based on the logic connection line data and the physical connection relation data according to the different excitations; acquiring the excessive pessimistic amount P based on clock delay data corresponding to the common physical path; clock delay data for the clock path structure is obtained by removing the excess pessimistic amount P.

For example, in a timing analysis method provided in at least one embodiment of the present disclosure, calculating clock delay data corresponding to the common physical path using the clock delay data of the common physical segment and the common physical segment includes: multiplying clock delay data corresponding to each common physical segment of the common physical path by a corresponding increase and decrease factor to obtain a first clock delay result D1; multiplying the clock delay data of each common physical node corresponding to the common physical path by a corresponding increase and decrease factor to obtain a second clock delay result D2; and summing each first clock delay result D1 and each second clock delay result D2 to obtain clock delay data corresponding to the common physical path.

For example, in a timing analysis method provided in at least one embodiment of the present disclosure, calculating clock delay data corresponding to the common physical path using the clock delay data of the common physical segment and the common physical segment includes: summing each third clock delay result D3 obtained by multiplying clock delay data corresponding to each of the common physical sub-segments of the common physical path by an increase/decrease factor corresponding to a reception path, and each fourth clock delay result D4 obtained by multiplying clock delay data corresponding to each of the common physical sub-nodes of the common physical path by an increase/decrease factor corresponding to a reception path, to obtain first clock delay data D01, wherein the first clock delay data D01 represents clock delay data corresponding to the common physical path for the reception path, the reception path being a clock interconnect line of at least a part between the target clock driving unit and a first one of the at least two target clock end units; and summing each fifth clock delay result D5 obtained by multiplying clock delay data corresponding to each common physical segment of the common physical path by an increase/decrease factor corresponding to the transmission path, and each sixth clock delay result D6 obtained by multiplying clock delay data corresponding to each common physical segment of the common physical path by an increase/decrease factor corresponding to the transmission path, to obtain second clock delay data D02, wherein the second clock delay data D02 represents clock delay data corresponding to the common physical path for the transmission path, and the transmission path is a clock interconnection line between at least one part of the target clock driving unit and a second one of the at least two target clock end units.

For example, in a timing analysis method provided in at least one embodiment of the present disclosure, for each of the common physical segment and each of the common physical node corresponding to the common physical path, the corresponding increase/decrease factor when receiving the path is the same; and/or, for each of the common physical segments and each of the common physical nodes corresponding to the common physical path, the corresponding increase and decrease factors when used for the transmit path are the same.

For example, in a timing analysis method provided by at least one embodiment of the present disclosure, acquiring the excessive pessimistic amount P based on clock delay data corresponding to the common physical path includes: the difference obtained by subtracting the first clock delay data D01 and the second clock delay data D02 is taken as an excessive pessimistic amount P corresponding to the common physical path.

For example, in a timing analysis method provided in at least one embodiment of the present disclosure, by removing the excessive pessimistic amount P to obtain clock delay data of the clock path structure, the method includes: acquiring third clock delay data D03 of the receiving path and fourth clock delay data D04 of the transmitting path; configuring clock delay data of the clock path structure to be equal to: the third clock delay data D03- (the fourth clock delay data D04-the excessive pessimistic amount P); wherein, each seventh clock delay result D7 obtained by multiplying clock delay data of each physical segment corresponding to the reception path by an increase/decrease factor corresponding to the reception path and each eighth clock delay result D8 obtained by multiplying clock delay data of each physical segment corresponding to the reception path by an increase/decrease factor corresponding to the reception path are summed to obtain third clock delay data D03 of the reception path; and summing each ninth clock delay result D9 obtained by multiplying clock delay data corresponding to each physical segment of the transmission path by an increase/decrease factor corresponding to the transmission path and each tenth clock delay result D10 obtained by multiplying clock delay data corresponding to each physical segment of the transmission path by an increase/decrease factor corresponding to the transmission path to obtain fourth clock delay data D04 of the transmission path.

For example, in a time sequence analysis method provided in at least one embodiment of the present disclosure, for each of the physical segments and each of the physical nodes corresponding to the reception path, the corresponding increase/decrease factors are the same when the physical segments and each of the physical nodes are used for the reception path; and/or for each physical segment and each physical node corresponding to the transmission path, the corresponding increase and decrease factors are the same when the physical segments and the physical nodes are used for the transmission path.

At least one embodiment of the present disclosure provides a timing analysis device based on physical routing division, including: a receiving module configured to obtain a clock path structure to be analyzed based on a gate level netlist for an integrated circuit design, wherein the clock path structure comprises a clock interconnection line, and a target clock driving unit and at least two target clock end units which are connected through the clock interconnection line; the physical routing dividing module is configured to: performing physical routing division on the clock interconnection line to obtain a plurality of physical sub-nodes and a plurality of physical sub-segments separated by the physical sub-nodes so as to obtain physical connection relation data between the target clock driving unit and the at least two target clock end units, wherein the physical sub-segments and the physical sub-nodes respectively comprise a common physical sub-segment and a common physical sub-node corresponding to a common physical path of the at least two target clock end units; a simulation module configured to: based on the physical connection relation data and logic connection data included in the gate-level netlist, clock delay data respectively corresponding to the physical segments and the physical nodes are generated through simulation; a timing computation module configured to: based on the common physical segment and the clock delay data of the common physical segment, an excess pessimistic amount generated by the common physical path is removed to obtain the clock delay data of the clock path structure.

The present disclosure also provides, in at least one embodiment, an electronic device including: a processor and a memory, wherein the memory has stored thereon a computer executable program which, when executed by the processor, implements a time sequence analysis method as described in any of the above.

At least one embodiment of the present disclosure further provides a computer-readable storage medium having a computer-executable program stored therein, which when executed by a processor, implements a timing analysis method as described in any one of the above.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.

FIG. 1 is a schematic diagram of a clock path architecture;

FIG. 2 is a flow chart of a timing analysis method based on physical routing according to some embodiments of the present disclosure;

FIG. 3 is a schematic diagram of a clock path structure A100 provided in some embodiments of the present disclosure;

FIG. 4 is a schematic diagram of a clock path structure provided by further embodiments of the present disclosure;

FIG. 5 is a flow chart of a method for generating clock delay data for a plurality of physical segments and a plurality of physical nodes in a simulation provided by some embodiments of the present disclosure;

FIG. 6 is a flow chart of obtaining clock delay data for a clock path structure by removing excess pessimistic amounts generated by a common physical path provided by some embodiments of the present disclosure;

FIG. 7 is a flow chart of calculating clock delay data corresponding to a common physical path using clock delay data of a common physical segment and a common physical segment node provided by some embodiments of the present disclosure;

FIG. 8 is a flow chart of calculating clock delay data corresponding to a common physical path using clock delay data of a common physical segment and a common physical segment node provided in further embodiments of the present disclosure;

FIG. 9 is a flow chart of obtaining clock delay data for a clock path structure by removing excess pessimistic amounts provided by further embodiments of the present disclosure;

FIG. 10 is a schematic block diagram of a timing analysis device based on physical routing provided by some embodiments of the present disclosure; and

Fig. 11 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure.

Detailed Description

The following description of the technical solutions in the embodiments of the present disclosure will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.

Unless defined otherwise, all terms (including technical and scientific terms) used in the embodiments of the disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined by the presently disclosed embodiments.

The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Nor does the terms "a," "an," or "the" or similar terms mean a limitation of quantity, but rather that at least one is present. Likewise, the word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. A flowchart is used in the embodiments of the present disclosure to illustrate the steps of a method according to embodiments of the present disclosure. It should be understood that the steps that follow or before do not have to be performed in exact order. Rather, the various steps may be processed in reverse order or simultaneously. Also, other operations may be added to or removed from these processes.

The inventor researches and discovers that for the identical logic units On the same integrated circuit Chip, the process deviation is caused by different positions, so that the time sequence delay is different, namely On-Chip Variation (OCV). In order to calculate such deviation, the timing calculation tool uses different increase and decrease factors (de rates) when calculating the delays of the clock transmit path and the clock receive path, and when the transmit path and the receive path have a common path, it is necessary to remove an excessive pessimistic amount caused by different calculation modes of the transmit path and the receive path, which is called clock convergence pessimistic removal (Clock Reconvergence Pessimism Removal, CRPR), that is, the excessive pessimistic amount of the clock refers to the deviation caused by using different increase and decrease factors when the transmit path and the receive path respectively use different increase and decrease factors to calculate the path delay, and when the two paths have corresponding common physical paths.

FIG. 1 is a schematic diagram of a clock path structure. For example, as shown in fig. 1, the clock path structure includes a first clock driving unit 401, a second clock driving unit 402, and a third clock driving unit 403, and a first clock end unit 501, a second clock end unit 502, and a third clock end unit 503. The clock path structure further includes clock interconnect lines, such as lines 300, 301, 302, and 303, for connecting the clock drive unit and the clock end unit. 100, 101, 102, 103, 104, 105 shown in fig. 1 are physical segments of the connection 303, respectively, the connection 300, 301, 302 is a logically-defined path concept, and the connection 303 is also a logically-defined connection, i.e. the arrow of the connection 303 in fig. 1 is merely an abstract indication.

For example, in the example of fig. 1, there is a timing check between any two of the first clock end unit 501, the second clock end unit 502, and the third clock end unit 503, and this may be specific according to the actual situation, which is not limited. For example, there is a timing check between the first clock end unit 501 and the third clock end unit 503, and if the first clock end unit 501 is a clock end unit corresponding to the transmit path, the third clock end unit 503 is a clock end unit corresponding to the receive path. The path taken by the clock 601 (clock) to the first clock end unit 501 is in turn: 300. 401, 301, 402, 302, 403, and 303, and physical segments 100 and 101, respectively. The paths traversed by clocks 601 through 503 are, in order: 300. 401, 301, 402, 302, 403, and 303, and physical segments 100, 102, 104, and 105, respectively.

For example, the delay (delay 1) from the clock 601 to the first clock end unit 501 is calculated by: the delays from 300, 401, 301, 402, 302, 403, 303 to the first clock end point unit 501 are multiplied by the corresponding increase/decrease factors to obtain respective sum values, and finally the sum value is added to obtain a value as a first delay (delay 1). The delay (delay 2) from the clock 601 to the third clock end unit 503 is calculated by: the delays 300, 401, 301, 402, 302, 403, 303 to the third clock end unit 503 are multiplied by the corresponding increase/decrease factors to obtain sum values, and the sum value is finally added to obtain a second delay (delay 2). As one of the clock delay data of the clock path structure, for example, a difference (Skew) of the clock delays of the first clock end unit 501 and the third clock end unit 503, the difference of the clock delays is equal to the first delay (delay 1) minus the second delay (delay 2).

Because clock 601 to first clock endpoint unit 501 and clock 601 to third clock endpoint unit 503 each employ different add/drop factors in view of on-chip errors, clock convergence pessimistic removal (CRPR) removes deviations in the logic sense that common paths 300, 401, 301, 402, 302, and 403 employ different add/drop factors due to on-chip errors. However, the logic paths 303 of the clock 601 to the first clock end unit 501 and the third clock end unit 503 respectively have a common physical path (e.g. comprising a common physical segment 100), and the physical segment 100 uses different increase and decrease factors due to on-chip errors, which causes a delay deviation, and the clock convergence pessimistic removal (CRPR) above does not remove the deviation. If there is a timing check between the first clock end unit 501, the second clock end unit 502, and the third clock end unit 503, the following problems exist in practical applications if the common physical paths corresponding to the clock interconnections (also referred to as clock traces) are not considered:

for example, the common physical path (e.g., including common physical line segment 100) of the first clock endpoint unit 501 and the third clock endpoint unit 503 shown in fig. 1 results in an excessive amount of pessimism due to the on-chip error taking different increase and decrease factors; as another example, the common physical path (e.g., including common physical segments 100 and 102) of the second clock endpoint unit 502 and the third clock endpoint unit 503 shown in fig. 1 may result in an excessive amount of pessimism due to on-chip errors taking different increase and decrease factors; as another example, the common physical path (e.g., including common physical line segment 100) of the first clock endpoint unit 501 and the second clock endpoint unit 502 shown in fig. 1 may result in an excessive amount of pessimism due to on-chip errors taking different increase and decrease factors.

At least one embodiment of the present disclosure provides a timing analysis method based on physical routing, the method including:

acquiring a clock path structure to be analyzed based on a gate-level netlist for integrated circuit design, wherein the clock path structure comprises a clock interconnection line, a target clock driving unit and at least two target clock end units, wherein the target clock driving unit and the at least two target clock end units are connected through the clock interconnection line;

performing physical routing division on the clock interconnection line to obtain a plurality of physical sub-nodes and a plurality of physical sub-nodes separated by the plurality of physical sub-nodes so as to acquire physical connection relation data between the target clock driving unit and at least two target clock end units, wherein the plurality of physical sub-nodes respectively comprise a common physical sub-node and a common physical sub-node corresponding to a common physical path of the at least two target clock end units;

based on the physical connection relation data and logic connection data included in the gate-level netlist, clock delay data corresponding to a plurality of physical segments and a plurality of physical nodes respectively are generated through simulation;

based on the clock delay data of the common physical segment and the common physical segment, an excess pessimistic amount generated by the common physical path is removed to obtain the clock delay data of the clock path structure.

At least one embodiment of the present disclosure further provides an apparatus corresponding to the above-mentioned timing analysis method.

The time sequence analysis method or the time sequence analysis device of the embodiment of the disclosure can remove the excessive pessimistic quantity generated by the common physical path based on the physical routing division of the clock interconnection line so as to acquire the clock delay data of the clock path structure, reduce clock deviation and improve the accuracy of time sequence convergence.

Fig. 2 is a flowchart of a timing analysis method based on physical routing according to some embodiments of the present disclosure. For example, as shown in fig. 2, the timing analysis method provided in at least one embodiment of the present disclosure includes steps S1 to S4.

Step S1, acquiring a clock path structure to be analyzed based on a gate-level netlist for integrated circuit design, wherein the clock path structure comprises a clock interconnection line, a target clock driving unit and at least two target clock end units, and the target clock driving unit and the at least two target clock end units are connected through the clock interconnection line.

And S2, carrying out physical routing division on the clock interconnection line to obtain a plurality of physical sub-nodes and a plurality of physical sub-segments separated by the plurality of physical sub-nodes so as to acquire physical connection relation data between the target clock driving unit and at least two target clock end units, wherein the plurality of physical sub-segments and the plurality of physical sub-nodes respectively comprise a common physical sub-segment and a common physical sub-node corresponding to a common physical path of at least two target clock end units.

And S3, generating clock delay data corresponding to the physical segments and the physical nodes respectively through simulation based on the physical connection relation data and logic connection data included in the gate-level netlist.

Step S4, based on the clock delay data of the common physical segment and the common physical segment, removing the excessive pessimistic quantity generated by the common physical path to obtain the clock delay data of the clock path structure.

Fig. 3 is a schematic diagram of a clock path structure a100 according to some embodiments of the present disclosure. Fig. 4 is a schematic diagram of a clock path structure according to further embodiments of the present disclosure.

As shown in fig. 3, the clock path structure a100 to be analyzed includes a clock interconnect line (e.g., line 303) and a target clock driving unit (e.g., clock driving unit 403) and at least two target clock end units (e.g., any two of target clock end units 501, 502, and 503) connected by the clock interconnect line (e.g., line 303). It should be noted that the clock path structure a10 is a logical concept, not a physical concept, and the connection 303 is a connection in a logical sense, that is, an arrow of the connection 303 in fig. 3 is merely an indication in an abstract sense, and is not limited to fig. 3. This means that the connection 303 physically includes nodes in a physical sense (e.g., 200, 201, 202, 203, 204, 205, and 206) and segments in a physical sense (e.g., 100, 101, 102, 103, 104, and 105), as described in detail below.

For example, in some examples, the target clock drive unit includes at least one of a plurality of clock drive units connected in series with each other. For example, the target clock driving unit is one of the clock driving unit 403 and the clock driving unit 402 in fig. 4, for example, the target clock driving unit is the clock driving unit 403 in fig. 4. Of course, the target clock driving unit may be the clock driving unit 402 in fig. 4, for example, in a case where the inventor studies that paths from the clock driving unit 402 to the target clock end unit 501 and another target clock end unit (not shown, for example, denoted as a fourth target clock end unit) are taken as a transmitting path and an accepting path (i.e., a common physical path exists between the target clock end unit 501 and the fourth target clock end unit), the clock driving unit 402 is taken as the target clock driving unit, which will not be described herein in detail. It should be noted that the meaning of a physical path in the embodiments of the present disclosure may be understood as a physical trace in a chip.

For another example, in some examples, the target clock drive unit may also include at least one of a plurality of clock drive units (not shown) in parallel. Therefore, the position, the number, etc. of the target clock driving units are not limited in the embodiments of the present disclosure, and are specifically determined according to different processes and projects, which are not described herein.

For example, in some examples, at least two target clock end units refer to at least two clock end units, and in particular, which clock end units, there are timing checks, and embodiments of the present disclosure are not limited in this regard, and in particular, require adjustment for different processes and projects.

For example, in some examples, the at least two clock end units include one clock end unit corresponding to the transmit path and one clock end unit corresponding to the receive path, e.g., the two target clock end units are any two of the clock end units 501, 502, and 503 in fig. 3 and 4. For example, in some examples, each clock end unit includes a register and a latch, that is, the timing check existing between two target clock end units may also be understood as the timing check between two different registers, which is not the focus of the embodiments of the present disclosure, and is not repeated herein for the sake of clarity and brevity.

It should be noted that, each of the clock driving units included in the clock path structure may correspond to one clock end unit, or each of the clock driving units included in the clock path structure may correspond to a plurality of clock end units, which is not limited by the implementation of the present disclosure, and may be specifically adjusted according to the actual situation, which is not described herein.

The method for analyzing the timing sequence based on the physical routing division is further described below on the basis of the clock path structure illustrated in fig. 3, but the embodiment of the disclosure is not limited to the specific form of the clock path structure, and the method for analyzing the timing sequence based on the other form of the clock path structure is not described herein.

For example, in some examples, for step S1, during the design of an integrated circuit, a gate level netlist is used to describe circuit element interconnections, such as a gate level netlist as a text file, and the front-end design of the integrated circuit is aimed at deriving the gate level netlist to provide some necessary files for the back-end design. In view of the fact that the gate-level netlist is not an emphasis instead of the embodiments of the present disclosure, the embodiments of the present disclosure are not described in detail herein in order to ensure that their description is clear and concise.

For example, in some examples, for step S2, physical routing is performed on a clock interconnect line (for example, a connection line 303) in the clock path structure a100 for connecting a target clock driving unit (for example, the clock driving unit 403) and a target clock destination unit (for example, any two of the clock destination units 501, 502 and 503) according to actual needs, so as to obtain a plurality of physical sub-nodes and a plurality of physical sub-segments separated by the plurality of physical sub-nodes, so as to obtain physical connection relationship data between the target clock driving unit and the target clock destination unit, that is, obtain physical connection relationship data corresponding to the corresponding physical sub-segments and the physical sub-nodes, as shown in fig. 3, for example, the physical sub-segments obtained by dividing include at least a part of the physical sub-nodes 200, 201, 202, 203, 204, 205 and 206, and the physical sub-segments obtained by dividing include at least a part of the physical sub-segments 100, 101, 102, 103, 104 and 105.

For example, specific physical routing manners include: with a physical jumper as a standard, physical routing before and after the jumper is a physical split line segment (for example, a line segment made of different metals), and a through hole (Via) used by the jumper is recorded as a physical split node, for example, the through hole is used for electrically connecting lines in different conductive layers in an integrated circuit, so that the wiring with higher integration level can be realized. Of course, this is merely exemplary and is not a limitation of the present disclosure.

For example, for physical connection relationship data, examples are as follows: the physical connection relationship between the clock driving unit 403 and the clock end unit 501 in fig. 3 is the clock driving unit 403, the physical minute node 200, the physical minute segment 100, the physical minute node 201, the physical minute segment 101, the physical minute node 202, and the clock end unit 501 in this order. Of course, this is merely exemplary, and is not a limitation of the present disclosure, and physical connection relationships in other cases are not described herein.

For example, in some examples, for step S2, when the target clock driving unit is the clock driving unit 403 and the target clock end units are the clock end units 501 and 502, the common physical path is the path 100a, as shown in fig. 3, and thus, the physical segments and the physical nodes obtained after the physical routing division include the common physical segments 100 and the common physical segments 200 and 201 corresponding to the common physical path 100 a. Of course, this is merely exemplary and is not a limitation of the present disclosure, and common physical paths in other cases are not described in detail herein.

For example, in some examples, for step S3, the gate-level netlist includes logic wiring data, and the logic wiring data includes the clock path structure described above. For example, the logic connection data is a netlist (for example, verilog netlist or Spice netlist) generated by an EDA tool, and the clock driving unit 403 and the clock end units 501, 502 and 503 are all connected through interconnection lines 303 in a logic sense. In view of the fact that front-end design is not an emphasis set forth in the embodiments of the present disclosure, embodiments of the present disclosure omit the relevant contents of the front-end design and its gate level netlist in order to ensure clarity and conciseness of the description of the present disclosure.

For example, in some examples, after the layout and the wiring, the timing analysis method based on the physical routing division in any of the above embodiments is performed, which is not described herein in detail.

FIG. 5 is a flow chart of a method for generating clock delay data for a plurality of physical segments and a plurality of physical nodes in a simulation provided in some embodiments of the present disclosure.

For example, as shown in fig. 5, for step S3, clock delay data corresponding to a plurality of physical segments and a plurality of physical nodes, respectively, is generated by simulation, specifically including step S31 and step S32.

Step S31, parasitic resistance data and parasitic capacitance data of a plurality of physical segments and parasitic resistance data and parasitic capacitance data of a plurality of physical nodes are extracted respectively to obtain parasitic parameter data.

Step S32, based on the logic connection line data, the physical connection relation data and the parasitic parameter data, under different excitation, clock delay data corresponding to a plurality of physical segments and a plurality of physical nodes respectively are generated in a simulation mode.

For example, in some examples, for step S31, simulation of clock delay data corresponding to the plurality of physical segments and the plurality of physical segments is implemented by a simulation tool (e.g., EDA tool). For example, the simulation tool includes an EDA tool. For example, in some examples, the EDA tool employs ICC, where ICC is a new generation of backend design tools for Synopsys. Of course, this is merely exemplary and is not a limitation of the present disclosure.

For example, in some examples, for step S31, the EDA tool is tightly matched with the Starrc tool or the like to achieve accurate design optimization of the signing driving, wherein the parasitic resistance data and the parasitic capacitance data are extracted by the Starrc tool, each physical branch segment has its own parasitic resistance and parasitic capacitance, and each physical branch node has its own parasitic resistance and parasitic capacitance, respectively.

For example, in some examples, the parasitic resistance R and parasitic capacitance C of the physical segments and the physical nodes, respectively, are extracted by a Starrc tool from the physical topology shown in fig. 3 (i.e., the physical topology formed by the physical routing divisions). Of course, the embodiments of the present disclosure do not limit the extraction manner of the parasitic resistance data and the parasitic capacitance data, and are not described herein.

For example, in some examples, for step S32, the different stimuli include: input signals from low level to high level based on different signal transition times (transitiontimes), or input signals from high level to low level based on different signal transition times.

For example, in some examples, for step S32, logic wiring data, physical connection relationship data, and parasitic parameter data are read in by a simulation tool, and corresponding clock delay data are generated with subsequent simulations.

For example, regarding the meaning of clock delay data, examples are as follows: for the physical segment 100 shown in fig. 3, when the output of the target clock driving unit 403 goes from low level to high level, and in the case where the signal transition time is 20ps, the delay generated on the physical segment 100 after EDA simulation is 1ps, which means that the clock delay data of the corresponding physical segment 100 generated by simulation is 1ps. Of course, this is merely exemplary to facilitate an understanding of embodiments of the present disclosure and is not intended to limit the present disclosure.

FIG. 6 is a flow chart of obtaining clock delay data for a clock path structure by removing excess pessimistic amounts generated by a common physical path, provided by some embodiments of the present disclosure.

For example, as shown in fig. 6, for step S4, based on the clock delay data of the common physical segment and the common physical segment, the excessive pessimistic amount generated by the common physical path is removed to obtain the clock delay data of the clock path structure, specifically including steps S41 to S44.

Step S41, obtaining logic connection data, physical connection relation data and clock delay data which are generated by simulation and respectively correspond to a plurality of physical segments and a plurality of physical nodes.

Step S42, according to different excitation, based on the logic connection line data and the physical connection relation data, clock delay data corresponding to the common physical path is calculated by using the clock delay data of the common physical segment and the common physical segment.

Step S43, obtaining the excessive pessimistic amount P based on the clock delay data corresponding to the common physical path.

Step S44, the clock delay data of the clock path structure is obtained by removing the excessive pessimistic amount P.

For example, in some examples, for step S41, logic wiring data, physical connection relationship data, and simulation-generated clock delay data are read in by a timing calculation tool for subsequent removal of the excessive pessimistic amount P generated by the common physical path. For example, the timing computation tool is a Primetime tool, wherein the ICC also mates with the Primetime tool to achieve accurate signature driven design optimization.

For example, in some examples, for step S44, the overspessimistic amount P refers to a deviation caused by using different increase or decrease factors when the transmit path and the receive path respectively use different increase or decrease factors to calculate the path delay, and when the two paths have corresponding common physical paths, wherein the receive path is at least a portion of a clock interconnect line between the target clock drive unit and a first one of the at least two target clock end units, and the transmit path is at least a portion of a clock interconnect line between the target clock drive unit and a second one of the at least two target clock end units.

For example, when calculating the clock delay data of the clock path structure, the paths from the target clock driving unit 403 to the target clock end units 501 and 502 are the transmitting path and the receiving path, and the physical segment 100 and the physical nodes 200 and 201 of the common physical path of the two paths deviate due to the different increasing and decreasing factors adopted by the transmitting path and the receiving path respectively, so that the excessive pessimistic amount P is generated. Of course, this is merely exemplary in order to facilitate an understanding of embodiments of the present disclosure and is not intended to limit the present disclosure, as other conditions that may exist are not described in detail herein.

Fig. 7 is a flow chart of calculating clock delay data corresponding to a common physical path using clock delay data of a common physical segment and a common physical segment node, provided in some embodiments of the present disclosure.

For example, as shown in fig. 7, for step S42, clock delay data corresponding to the common physical path is calculated using the clock delay data of the common physical segment and the common physical segment, and steps S421 to S423 are included.

Step S421, the clock delay data corresponding to each common physical segment of the common physical path is multiplied by a corresponding increase/decrease factor to obtain a first clock delay result D1.

Step S422, multiplying the clock delay data corresponding to each common physical node of the common physical path by a corresponding increase/decrease factor to obtain a second clock delay result D2.

Step S423, sums each first clock delay result D1 and each second clock delay result D2 to obtain clock delay data Dx corresponding to the common physical path.

For example, in some examples, when the common physical path is the common physical path 100a shown in fig. 3, the common physical split line segment corresponding to the common physical path 100a is 100 and the common physical split nodes are 200 and 201, if the increase and decrease factors adopted by the common physical split line segment 100 and the common physical split nodes are 200 and 201 are d1, d2, and d3, respectively, for example, the clock delay data generated by simulation and corresponding to 100, 200, and 201 are 3ps, 2ps, and 1ps, respectively, then the clock delay data corresponding to the common physical path 100a is equal to: 3ps×d1+2ps×d2+1ps×d3, wherein the first clock delay result is 3ps×d1, and the second clock delay result is 2ps×d2 and 1ps×d3, respectively.

For example, in some examples, the increase and decrease factors d1, d2, d3 may be the same as each other, such as, for the common physical path 100a owned on the receiving path alone, all the common physical segments and the increase and decrease factors of the common physical nodes may be the same, that is, d1=d2=d3=d, and then the above-mentioned clock delay data corresponding to the common physical path 100a is equal to (3ps+2ps+1ps) ×d. Of course, in specific cases, the increasing/decreasing factors d1, d2, d3 may be different from each other, which is not limited in the embodiments of the present disclosure, and the increasing/decreasing factors d1, d2, d3 need to be determined according to actual situations, and are not described herein.

Fig. 8 is a flow chart of calculating clock delay data corresponding to a common physical path using clock delay data of a common physical segment and a common physical segment node, according to further embodiments of the present disclosure.

For example, as shown in fig. 8, for step S42, clock delay data corresponding to the common physical path is calculated using the clock delay data of the common physical segment and the common physical segment, specifically including step S4201 and step S4202.

Step S4201 sums each third clock delay result D3 obtained by multiplying the clock delay data corresponding to each common physical segment of the common physical path by the increase/decrease factor corresponding to the reception path, and each fourth clock delay result D4 obtained by multiplying the clock delay data corresponding to each common physical segment of the common physical path by the increase/decrease factor corresponding to the reception path, to obtain first clock delay data D01, wherein the first clock delay data D01 represents the clock delay data corresponding to the common physical path when the path is received.

Step S4202 sums each fifth clock delay result D5 obtained by multiplying the clock delay data corresponding to each common physical segment of the common physical path by the increase/decrease factor corresponding to the time for transmitting the path, and each sixth clock delay result D6 obtained by multiplying the clock delay data corresponding to each common physical segment of the common physical path by the increase/decrease factor corresponding to the time for transmitting the path, to obtain second clock delay data D02, wherein the second clock delay data D02 represents the clock delay data corresponding to the common physical path when transmitting the path.

It should be noted that, there is no step in the order of step S4201 and step S4202, for example, the order of step may be from step S4201 to step S4202, from step S4202 to step S4201, or both steps may be processed simultaneously, which is not limited in the embodiments of the present disclosure.

For example, in the examples of fig. 7 and 8, the corresponding increase and decrease factors are the same for each common physical segment and each common physical segment corresponding to a common physical path for accepting the path, and/or the corresponding increase and decrease factors are the same for each common physical segment and each common physical segment corresponding to a common physical path for transmitting the path.

For another example, in the examples of fig. 7 and 8, the corresponding increase and decrease factors may be different for accepting paths with respect to at least two of each common physical segment and each common physical segment corresponding to a common physical path, and/or the corresponding increase and decrease factors may be different for transmitting paths with respect to at least two of each common physical segment and each common physical segment corresponding to a common physical path. The embodiments of the present disclosure are not limited thereto, and may be specifically adjusted according to actual needs, which are not described herein.

For example, in some examples, when the common physical path is the common physical path 100a shown in fig. 3, the common physical partition line segment corresponding to the common physical path 100a is 100, and the common physical partition nodes are 200 and 201, if the increase and decrease factors adopted by the common physical partition line segment 100 and the common physical partition nodes 200 and 201 when used for the transmission paths are equal, for example, denoted as D, and further, for example, the clock delay data generated by simulation corresponding to 100, 200 and 201 are 3ps, 2ps and 1ps, respectively, then the second clock delay data D02 is equal to (2ps+3ps+1ps) ×d. Similarly, if the increase and decrease factors adopted by the common physical segment 100 and the common physical segments 200 and 201 when they are used for the reception paths are equal, for example, denoted as D ', and further, if the clock delay data generated by simulation corresponding to 100, 200 and 201 are 3ps, 2ps and 1ps, respectively, the first clock delay data D01 is equal to (2ps+3ps+1ps) ×d'. Of course, this is merely exemplary in order to facilitate an understanding of embodiments of the present disclosure and is not intended to limit the present disclosure, as other conditions that may exist are not described in detail herein.

For example, in some examples, for step S43, the obtaining the excessive pessimistic amount P based on the clock delay data corresponding to the common physical path specifically includes: the difference obtained by subtracting the first clock delay data D01 and the second clock delay data D02 is taken as the excessive pessimistic amount P corresponding to the common physical path.

FIG. 9 is a flow chart of obtaining clock delay data for a clock path structure by removing excess pessimistic amounts provided by further embodiments of the present disclosure.

For example, as shown in fig. 9, for step S44, the clock delay data Dy of the clock path structure a100 is obtained by removing the excessive pessimistic amount P, specifically including step S441 and step S442.

Step S441 acquires third clock delay data D03 of the reception path and fourth clock delay data D04 of the transmission path.

Step S442, configuring the clock delay data Dy of the clock path structure to be equal to: third clock delay data D03- (fourth clock delay data D04-excessive pessimistic amount P).

For example, in some examples, the third clock delay data D03 of the reception path is obtained by summing each seventh clock delay result D7 obtained by multiplying the clock delay data of each physical segment of the reception path by the corresponding increase/decrease factor for the reception path, and each eighth clock delay result D8 obtained by multiplying the clock delay data of each physical segment of the reception path by the corresponding increase/decrease factor for the reception path; similarly, fourth clock delay data D04 of the transmission path is obtained by summing each ninth clock delay result D9 obtained by multiplying clock delay data of each physical segment of the corresponding transmission path by the increase/decrease factor corresponding to when used in the transmission path, and each tenth clock delay result D10 obtained by multiplying clock delay data of each physical segment of the corresponding transmission path by the increase/decrease factor corresponding to when used in the transmission path.

For example, in some examples, for the fourth clock delay data D04 of the transmission path from the target clock driving unit 403 to the target clock end unit 501 in fig. 3, the total delay of the physical traces passing through the physical sub-node 200, the physical sub-line segment 100, the physical sub-node 201, the physical sub-line segment 101 and the physical sub-node 202 is equal to 2ps, 3ps, 1ps, 4ps, 3.5ps, if the increase/decrease factors adopted by the physical sub-nodes 200, 100, 201, 101, 202 are D1, D2, D3, D4, D5, respectively, and then the clock delay data corresponding to the physical sub-nodes 200, 100, 201, 101, 202 generated by simulation are 2ps, 3ps, 1ps, 4ps, 3.5ps, then D04 is equal to 2ps×1+3ps×d2+1ps×4+3.5ps×5, where the ninth clock delay result D9 is 3ps×2 and 4ps×4, respectively, and the tenth clock delay result D10 is 2ps×1, 1ps×3.5ps, respectively.

For example, in some examples, for the third clock delay data D03 of the receiving path from the target clock driving unit 403 to the target clock end unit 502 in fig. 3, which is equal to the total delay of the physical routes through the physical division node 200, the physical division node 100, the physical division node 201, the physical division node 102, the physical division node 203, the physical division node 103, and the physical division node 204, the increasing and decreasing factors adopted by the factors of 200, 100, 201, 102, 203, 103, 204 are D1', D2', D3', D4', D5', D6', D7', respectively, and then, for example, the clock delay data generated by the simulation and corresponding to 200, 100, 201, 102, 203, 103, 204 are 2ps, 3ps, 1ps, 4.2ps, 3.2ps, 4.5ps, 3.5ps, and 3.5ps, respectively, D03 is equal to 2ps D1' +3ps D2' +1ps D3' +4.2ps, 4' +3.2ps, 5' and the result is seven of the clock delay data generated by simulation is 2ps, 3ps, 1, 3ps, 3, 5', and 4' 4, 5ps, 7', and 4' 7, 3, 5, 4' respectively.

The increasing and decreasing factors d1, d2, d3, d4, and d5 for the transmit paths may be the same or different from each other, and similarly, d1', d2', d3', d4', d5', d6', and d7' for the receive paths may be the same or different from each other, which are not described herein.

For example, in some examples, if the increase and decrease factors D1, D2, D3, D4, D5 for the transmit paths are the same, i.e., d1=d2=d3=d4=d5=d, if d=1.1, then the fourth clock delay data D04 for the transmit paths is equal to (2ps+3ps+1ps+4ps+3.5ps) ×1.1=14.85 ps, and likewise, if the increase and decrease factors D1', D2', D3', D4', D5', D6', D7 'for the receive paths are the same, i.e., D1' =d2 '=d3' =d4 '=d5' =d6 '=d7' =d ', if D' =0.9, then the third clock delay data D03 for the receive paths is equal to (2ps+3ps+1ps+4.2ps+4.5ps+3.5ps+3.5ps) ×0.9=19.26 ps, and, according to the above-a method corresponding to the total sad-1+2ps=2ps+1.6ps+2ps+2ps+2ps+2ps+2ps+2ps+2ps+1.5ps+an excessive amount calculated from the above. Of course, this is merely exemplary in order to facilitate an understanding of embodiments of the present disclosure and is not intended to limit the present disclosure, as other conditions that may exist are not described in detail herein.

Thus, the embodiment of the present disclosure can avoid the excessive pessimistic amount P caused by the different increasing/decreasing factors of the common physical paths of the first clock end unit 501 and the third clock end unit 503, the excessive pessimistic amount P caused by the different increasing/decreasing factors of the common physical paths of the second clock end unit 502 and the third clock end unit 503, and the excessive pessimistic amount P caused by the different increasing/decreasing factors of the common physical paths of the first clock end unit 501 and the second clock end unit 502.

According to the time sequence analysis method, the corresponding physical line segments and physical node segments are obtained through physical line distribution of the clock interconnection lines, and when the time sequence is calculated, delay deviation caused by different increase and decrease of the physical line segments and the physical node segments corresponding to the common physical paths is removed, so that clock deviation is reduced, time sequence convergence accuracy is improved, power consumption is reduced, and performance of a chip is improved.

Fig. 10 is a schematic block diagram of a timing analysis device based on physical routing according to some embodiments of the present disclosure.

For example, as shown in fig. 10, the timing analysis apparatus 600 includes a receiving module 610, a physical routing module 620, a simulation module 630, and a timing calculation module 640. The receiving module 610 is configured to: a clock path structure to be analyzed is obtained based on a gate level netlist for an integrated circuit design, wherein the clock path structure comprises a clock interconnect line, and a target clock driving unit and at least two target clock end units which are connected through the clock interconnect line. The physical routing partition module 620 is configured to: and carrying out physical routing division on the clock interconnection line to obtain a plurality of physical sub-nodes and a plurality of physical sub-nodes separated by the plurality of physical sub-nodes so as to acquire physical connection relation data between the target clock driving unit and at least two target clock end units, wherein the plurality of physical sub-nodes and the plurality of physical sub-nodes respectively comprise a common physical sub-node and a common physical sub-node corresponding to a common physical path of at least two target clock end units. The simulation module 630 is configured to: based on the physical connection relation data and logic connection data included in the gate-level netlist, clock delay data corresponding to the physical segments and the physical nodes are generated through simulation. The timing calculation module 640 is configured to: based on the clock delay data of the common physical segment and the common physical segment, an excess pessimistic amount generated by the common physical path is removed to obtain the clock delay data of the clock path structure.

For example, in some examples, the target clock drive unit includes: one or more clock driving units of the plurality of clock driving units connected in series and/or parallel may be specifically referred to the description of the above time sequence analysis method, and will not be repeated herein.

For example, in some examples, the simulation module 630 is further configured to: respectively extracting parasitic resistance data and parasitic capacitance data of a plurality of physical branch lines and parasitic resistance data and parasitic capacitance data of a plurality of physical branch nodes to obtain parasitic parameter data; based on the logic connection line data, the physical connection relation data and the parasitic parameter data, under different excitation, clock delay data corresponding to a plurality of physical branch lines and a plurality of physical branch nodes are generated in a simulation mode.

For example, in some examples, the different stimuli include: input signals from low level to high level based on different signal transition times, or input signals from high level to low level based on different signal transition times.

For example, in some examples, the simulation module 630 includes an EDA tool. Of course, this is merely exemplary and is not a limitation of the present disclosure.

For example, in some examples, the timing computation module 640 is further configured to: acquiring logic connection data, physical connection relation data and clock delay data which are generated by simulation and respectively correspond to a plurality of physical segments and a plurality of physical nodes; according to different excitations, clock delay data corresponding to a common physical path is calculated by utilizing clock delay data of a common physical segment and a common physical segment based on logic connection data and physical connection relation data; acquiring an excessive pessimistic amount P based on clock delay data corresponding to the common physical path; clock delay data of the clock path structure is obtained by removing the excessive pessimistic amount P.

For example, the timing computation module 640 includes a Primetime tool, wherein the ICC also mates with the Primetime tool to achieve accurate signature driven design optimization.

For example, in some examples, the timing computation module 640 is further configured to: multiplying the clock delay data of each common physical segment corresponding to the common physical path by a corresponding increase and decrease factor to obtain a first clock delay result D1; multiplying the clock delay data of each common physical node corresponding to the common physical path by a corresponding increase and decrease factor to obtain a second clock delay result D2; each first clock delay result D1 and each second clock delay result D2 are summed to obtain clock delay data corresponding to the common physical path.

For example, in some examples, the timing computation module 640 is further configured to: summing each third clock delay result D3 obtained by multiplying clock delay data corresponding to each common physical segment of the common physical path by an increase/decrease factor corresponding to the reception path, and each fourth clock delay result D4 obtained by multiplying clock delay data corresponding to each common physical segment of the common physical path by an increase/decrease factor corresponding to the reception path, to obtain first clock delay data D01, wherein the first clock delay data D01 represents clock delay data corresponding to the common physical path when the path is received, and the reception path is a clock interconnection line between at least a part of the target clock driving unit and a first one of the at least two target clock end units; and summing each fifth clock delay result D5 obtained by multiplying clock delay data corresponding to each common physical segment of the common physical path by an increase/decrease factor corresponding to the time of the transmission path, and each sixth clock delay result D6 obtained by multiplying clock delay data corresponding to each common physical segment of the common physical path by an increase/decrease factor corresponding to the time of the transmission path, to obtain second clock delay data D02, wherein the second clock delay data D02 represents clock delay data corresponding to the common physical path for the time of the transmission path, and the transmission path is a clock interconnection line of at least a part between the target clock driving unit and a second one of the at least two target clock end units.

For example, in some examples, for each common physical segment and each common physical node that corresponds to a common physical path, the corresponding increase and decrease factor when accepting the path is the same; and/or, for each common physical segment and each common physical node corresponding to a common physical path, the corresponding increase and decrease factors are the same when used to transmit the path, as embodiments of the present disclosure are not limited in this regard.

For example, in some examples, the timing computation module 640 is further configured to: the difference obtained by subtracting the first clock delay data D01 and the second clock delay data D02 is taken as the excessive pessimistic amount P corresponding to the common physical path.

For example, in some examples, the timing computation module 640 is further configured to: acquiring third clock delay data D03 of the receiving path and fourth clock delay data D04 of the transmitting path; the clock delay data of the clock path structure is configured to be equal to: third clock delay data D03- (fourth clock delay data D04-excessive pessimistic amount P). For example, the third clock delay data D03 of the reception path is obtained by summing each seventh clock delay result D7 obtained by multiplying the clock delay data of each physical segment of the reception path by the increase/decrease factor corresponding to the reception path, and each eighth clock delay result D8 obtained by multiplying the clock delay data of each physical segment of the reception path by the increase/decrease factor corresponding to the reception path; the fourth clock delay data D04 of the transmission path is obtained by summing each ninth clock delay result D9 obtained by multiplying the clock delay data of each physical segment of the corresponding transmission path by the increase/decrease factor corresponding to the time for the transmission path, and each tenth clock delay result D10 obtained by multiplying the clock delay data of each physical segment of the corresponding transmission path by the increase/decrease factor corresponding to the time for the transmission path.

For example, in some examples, for each physical segment and each physical node of the corresponding accept path, the corresponding increase and decrease factor is the same for the accept path; and/or, for each physical segment and each physical node of the corresponding transmit path, the corresponding increase and decrease factors are the same when used for the transmit path, which embodiments of the present disclosure do not limit.

It should be noted that, in the embodiment of the present disclosure, the timing analysis apparatus 600 may include more or less modules, and the connection relationship between the respective modules is not limited and may be determined according to actual requirements. The specific constitution of each module is not limited. Regarding the technical effects of the timing analysis device 600, reference may be made to the technical effects of the timing analysis method in the above-described embodiments of the present disclosure, and the description thereof will not be repeated here.

Each module in the above embodiments may be configured as software, hardware, firmware, or any combination thereof, respectively, that performs a specific function. For example, these modules may correspond to application specific integrated circuits, to pure software code, or to a combination of software and hardware.

It should be noted that, although the timing analysis apparatus is described above as being divided into modules for executing the respective processes, it is clear to those skilled in the art that the processes executed by the respective modules may be executed without any specific division of the modules or without explicit demarcation between the respective modules.

For example, in some examples, the timing analysis method of the embodiments of the present disclosure may be recorded in a computer-readable recording medium. In particular, embodiments of the present disclosure may provide a computer-readable recording medium storing computer-executable instructions that, when executed by a processor of the computer, may cause the computer processor to perform the timing analysis method as described above. Examples of the computer-readable recording medium may include magnetic media (e.g., hard disk, floppy disk, and magnetic tape); optical media (e.g., CD-ROM and DVD); magneto-optical media (e.g., optical disks); and hardware devices that are specially formulated for storing and performing the program instructions (e.g., read only memory, ROM), random Access Memory (RAM), flash memory, etc.).

For example, as shown in fig. 11, at least one embodiment of the present disclosure may also provide an electronic device 700, the electronic device 700 including a processor 710 and a memory 720. Memory 720 is used to store non-transitory computer readable instructions (e.g., one or more computer program modules) that processor 710 is configured to execute non-transitory computer readable instructions that when executed by processor 710 may perform one or more of the steps of the timing analysis method above. It should be noted that, in the embodiments of the present disclosure, specific functions and technical effects of the electronic device 700 may refer to the description of the time sequence analysis method above, which is not repeated herein.

The following points need to be described:

(1) The drawings of the embodiments of the present disclosure relate only to the structures to which the embodiments of the present disclosure relate, and reference may be made to the general design for other structures.

(2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

The foregoing is merely specific embodiments of the disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the claims.

Claims

1. A time sequence analysis method based on physical routing division comprises the following steps:

obtaining a clock path structure to be analyzed based on a gate level netlist for an integrated circuit design, wherein the clock path structure comprises a clock interconnection line, a target clock driving unit and at least two target clock end units which are connected through the clock interconnection line,

performing physical routing division on the clock interconnection line to obtain a plurality of physical sub-nodes and a plurality of physical sub-nodes separated by the physical sub-nodes so as to obtain physical connection relation data between the target clock driving unit and the at least two target clock end units, wherein the physical sub-nodes and the physical sub-nodes respectively comprise a common physical sub-node and a common physical sub-node corresponding to a common physical path of the at least two target clock end units,

Based on the physical connection relation data and logic connection data included in the gate-level netlist, generating clock delay data corresponding to the physical segments and the physical nodes respectively through simulation,

removing an excess pessimistic amount generated by the common physical path equal to a difference between first clock delay data D01 and second clock delay data D02 based on the common physical segment and the clock delay data of the common physical segment to obtain clock delay data of the clock path structure;

the first clock delay data D01 represents clock delay data for the common physical path when receiving a path, the receiving path being a clock interconnect line of at least a part between the target clock driving unit and a first one of the at least two target clock end units; the first clock delay data D01 is configured to: each third clock delay result D3 obtained by multiplying clock delay data corresponding to each of the common physical branch segments of the common physical path by an increase/decrease factor corresponding to the reception path, and each fourth clock delay result D4 obtained by multiplying clock delay data corresponding to each of the common physical branch nodes of the common physical path by an increase/decrease factor corresponding to the reception path;

The second clock delay data D02 represents clock delay data for the common physical path when used in a transmit path, the transmit path being a clock interconnect line between the target clock driving unit and a second one of the at least two target clock end units; the second clock delay data D02 is configured to: each fifth clock delay result D5 obtained by multiplying clock delay data corresponding to each of the common physical segments of the common physical path by an increase/decrease factor corresponding to the time for the transmission path, and each sixth clock delay result D6 obtained by multiplying clock delay data corresponding to each of the common physical segments of the common physical path by an increase/decrease factor corresponding to the time for the transmission path.

2. The timing analysis method as claimed in claim 1, wherein the target clock driving unit comprises: one or more of the plurality of clock driving units in series and/or parallel.

3. The timing analysis method of claim 1, wherein generating clock delay data corresponding to the plurality of physical segments and the plurality of physical nodes, respectively, by simulation comprises:

Respectively extracting parasitic resistance data and parasitic capacitance data of the plurality of physical branch lines and parasitic resistance data and parasitic capacitance data of the plurality of physical branch nodes to obtain parasitic parameter data,

based on the logic connection line data, the physical connection relation data and the parasitic parameter data, clock delay data corresponding to the physical segments and the physical nodes respectively are generated in a simulation mode under different excitation.

4. A timing analysis method as claimed in claim 3, wherein said different stimuli comprises: input signals from low level to high level based on different signal transition times, or input signals from high level to low level based on different signal transition times.

5. The timing analysis method of claim 3, wherein removing the excess pessimistic amount P generated by the common physical path based on the clock delay data of the common physical partition segment and the common physical partition node to obtain the clock delay data of the clock path structure comprises:

obtaining the logic connection line data, the physical connection relation data and clock delay data which are generated by simulation and respectively correspond to the physical segments and the physical nodes,

Calculating clock delay data corresponding to the common physical path by using the clock delay data of the common physical branch line segment and the common physical branch node based on the logic connection line data and the physical connection relation data according to the different stimuli, wherein the clock delay data corresponding to the common physical path comprises the first clock delay data D01 and the second clock delay data D02,

the excess pessimistic amount P is obtained based on clock delay data corresponding to the common physical path, and clock delay data of the clock path structure is obtained by removing the excess pessimistic amount P.

6. The timing analysis method of claim 5, wherein calculating clock delay data corresponding to the common physical path using the clock delay data of the common physical segment and the common physical segment node comprises:

multiplying the clock delay data corresponding to each of said common physical segments of said common physical path with a corresponding increase and decrease factor to obtain a first clock delay result D1,

multiplying the clock delay data corresponding to each of said common physical nodes of said common physical path with a corresponding increase and decrease factor to obtain a second clock delay result D2,

And summing each first clock delay result D1 and each second clock delay result D2 to obtain clock delay data corresponding to the common physical path.

7. The timing analysis method according to claim 6, wherein,

for each common physical segment corresponding to the common physical path and each common physical node, the corresponding increase and decrease factors are the same when the path is accepted;

and/or, for each of the common physical segments and each of the common physical nodes corresponding to the common physical path, the corresponding increase and decrease factors when used for the transmit path are the same.

8. The timing analysis method as set forth in claim 5, wherein obtaining clock delay data of the clock path structure by removing the excessive pessimistic amount P comprises:

the third clock delay data D03 of the accept path and the fourth clock delay data D04 of the transmit path are acquired,

configuring clock delay data of the clock path structure to be equal to: the third clock delay data D03- (the fourth clock delay data D04-the excessive pessimistic amount P),

wherein each seventh clock delay result D7 obtained by multiplying clock delay data of each of the physical segment corresponding to the reception path by an increase/decrease factor corresponding to the reception path and each eighth clock delay result D8 obtained by multiplying clock delay data of each of the physical segment corresponding to the reception path by an increase/decrease factor corresponding to the reception path are summed to obtain third clock delay data D03 of the reception path,

And summing each ninth clock delay result D9 obtained by multiplying clock delay data corresponding to each physical segment of the transmission path by an increase/decrease factor corresponding to the transmission path and each tenth clock delay result D10 obtained by multiplying clock delay data corresponding to each physical segment of the transmission path by an increase/decrease factor corresponding to the transmission path to obtain fourth clock delay data D04 of the transmission path.

9. The timing analysis method according to claim 8, wherein,

for each physical segment and each physical node corresponding to the receiving path, the corresponding increase and decrease factors are the same when the physical segments and the physical nodes are used for the receiving path;

and/or for each physical segment and each physical node corresponding to the transmission path, the corresponding increase and decrease factors are the same when the physical segments and the physical nodes are used for the transmission path.

10. A timing analysis device based on physical routing, comprising:

a receiving module configured to obtain a clock path structure to be analyzed based on a gate level netlist for an integrated circuit design, wherein the clock path structure comprises a clock interconnect line and a target clock driving unit and at least two target clock end units connected by the clock interconnect line,

The physical routing dividing module is configured to: performing physical routing division on the clock interconnection line to obtain a plurality of physical sub-nodes and a plurality of physical sub-nodes separated by the physical sub-nodes so as to obtain physical connection relation data between the target clock driving unit and the at least two target clock end units, wherein the physical sub-nodes and the physical sub-nodes respectively comprise a common physical sub-node and a common physical sub-node corresponding to a common physical path of the at least two target clock end units,

a simulation module configured to: based on the physical connection relation data and logic connection data included in the gate-level netlist, generating clock delay data corresponding to the physical segments and the physical nodes respectively through simulation,

a timing computation module configured to: removing an excess pessimistic amount generated by the common physical path equal to a difference between first clock delay data D01 and second clock delay data D02 based on the common physical segment and the clock delay data of the common physical segment to obtain clock delay data of the clock path structure;

The first clock delay data D01 represents clock delay data for the common physical path when receiving a path, the receiving path being a clock interconnect line of at least a part between the target clock driving unit and a first one of the at least two target clock end units; the first clock delay data D01 is configured to: each third clock delay result D3 obtained by multiplying clock delay data corresponding to each of the common physical segments of the common physical path by an increase/decrease factor corresponding to the reception path, and each fourth clock delay result D4 obtained by multiplying clock delay data corresponding to each of the common physical segments of the common physical path by an increase/decrease factor corresponding to the reception path;

the second clock delay data D02 represents clock delay data for the common physical path when used in a transmit path, the transmit path being a clock interconnect line between the target clock driving unit and a second one of the at least two target clock end units; the second clock delay data D02 is configured to: each fifth clock delay result D5 obtained by multiplying clock delay data corresponding to each of the common physical segments of the common physical path by an increase/decrease factor corresponding to the time of use in the transmission path, and each sixth clock delay result D6 obtained by multiplying clock delay data corresponding to each of the common physical segments of the common physical path by an increase/decrease factor corresponding to the time of use in the transmission path.

11. An electronic device, comprising: a processor and a memory are provided for the processor,

wherein the memory has stored thereon a computer executable program which, when executed by the processor, implements the timing analysis method of any of claims 1 to 9.

12. A computer-readable storage medium having stored therein a computer-executable program which, when executed by a processor, implements the timing analysis method of any one of claims 1 to 9.