CN113156726A - Panel pixel arrangement structure and driving method thereof - Google Patents

Panel pixel arrangement structure and driving method thereof Download PDF

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Publication number
CN113156726A
CN113156726A CN202110338708.8A CN202110338708A CN113156726A CN 113156726 A CN113156726 A CN 113156726A CN 202110338708 A CN202110338708 A CN 202110338708A CN 113156726 A CN113156726 A CN 113156726A
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demux
data
trace
pixel
wire
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熊克
谢建峰
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Fujian Huajiacai Co Ltd
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Fujian Huajiacai Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention relates to the technical field of panel pixel arrangement structures, in particular to a panel pixel arrangement structure and a driving method thereof.

Description

Panel pixel arrangement structure and driving method thereof
Technical Field
The present invention relates to a panel pixel arrangement structure, and more particularly, to a panel pixel arrangement structure and a driving method thereof.
Background
In the manufacturing process of the Demux (demultiplexing) liquid crystal display screen, due to the instability and uncontrollable performance of the manufacturing process, Ion (starting current when the TFT is opened) of a Demux TFT switch is different, so that the charging rates of sub-pixels (R/G/B) on Source lines (Source wiring lines) connected with some Demux TFT switches are different, the display brightness of the sub-pixels on each Source Line is different, bright and dark vertical lines are generated, and the display quality of the Demux liquid crystal display screen is influenced.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: a panel pixel arrangement structure and a driving method thereof are provided, which can integrate the display brightness of pixels, thereby eliminating the generation of bright and dark vertical lines of a panel.
In order to solve the above technical problems, a first technical solution adopted by the present invention is:
a panel pixel arrangement structure comprises more than two pixel units, a first Demux routing, a second Demux routing, a third Demux routing, a plurality of data routing and a plurality of gate routing, wherein one pixel unit is provided with two gate routing and is positioned between the two gate routing;
each pixel unit comprises six rows of sub-pixel pairs and seven data wires which are sequentially arranged from left to right, wherein two data wires are configured on one row of sub-pixel pairs and are positioned between the two data wires, and two adjacent rows of sub-pixel pairs share one data wire;
a second data wire to a seventh data wire which are sequentially arranged from left to right in one pixel unit are respectively connected with a TFT switch, the grid electrodes of the TFT switches connected with the second data wire and the third data wire which are sequentially arranged from left to right in one pixel unit are respectively electrically connected with a first Demux wire, the grid electrodes of the TFT switches connected with the fourth data wire and the fifth data wire which are sequentially arranged from left to right in one pixel unit are respectively electrically connected with a second Demux wire, and the grid electrodes of the TFT switches connected with the sixth data wire and the seventh data wire which are sequentially arranged from left to right in one pixel unit are respectively electrically connected with a third Demux wire;
the input end of each TFT switch is connected with a source wire, the TFT switches connected with a second data wire, a fourth data wire and a sixth data wire which are sequentially arranged from left to right in one pixel unit share one source wire, and the TFT switches connected with a third data wire, a fifth data wire and a seventh data wire which are sequentially arranged from left to right in one pixel unit share one source wire.
The second technical scheme adopted by the invention is as follows:
a driving method of a panel pixel arrangement structure comprises the following steps:
step S1, in a pixel unit, controlling one of two grid wires to be opened;
step S2, during the period of starting one grid wire, sequentially controlling the first Demux wire, the second Demux wire and the third Demux wire to be started; during the starting period of the first Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a second data trace and a third data trace which are sequentially arranged from left to right in one pixel unit; during the starting period of the second Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a fourth data trace and a fifth data trace which are sequentially arranged from left to right in one pixel unit; during the starting period of the third Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a sixth data trace and a seventh data trace which are sequentially arranged from left to right in one pixel unit;
step S3, controlling the other grid wire of the two grid wires to be opened;
step S4, during the period of starting another grid wire, sequentially controlling the first Demux wire, the second Demux wire and the third Demux wire to be started; during the starting period of the first Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a second data trace and a third data trace which are sequentially arranged from left to right in one pixel unit; during the starting period of the second Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a fourth data trace and a fifth data trace which are sequentially arranged from left to right in one pixel unit; during the starting period of the third Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a sixth data trace and a seventh data trace which are sequentially arranged from left to right in one pixel unit;
step S5, loop through steps S1-S4, drives each pixel cell.
The invention has the beneficial effects that:
the first Demux trace controls the signal input condition of the TFT switches connected with the second data trace and the third data trace which are sequentially arranged from left to right in one pixel unit by arranging the first Demux trace, the second Demux trace and the third Demux trace to be respectively and correspondingly connected with the TFT switches in the pixel units, the second Demux trace controls the signal input condition of the TFT switches connected to the fourth data trace and the fifth data trace arranged in sequence from left to right in one pixel unit, the third Demux trace controls the signal input condition of the TFT switch connected with the sixth data trace and the seventh data trace which are sequentially arranged from left to right in one pixel unit, thus the arrangement mode of pixels in the pixel unit can be changed, therefore, the problem of poor display of the Demux liquid crystal display screen is solved, and the phenomenon of poor display of the Demux liquid crystal display screen caused by poor manufacturing process is improved; and the process cost of the process optimization is saved, the utilization rate of materials is increased, the defects caused by neglecting the process difference can be achieved, the display quality of the Demux liquid crystal display screen is improved, and the development prospect is good.
Drawings
FIG. 1 is a schematic structural diagram of a pixel arrangement structure of a panel according to the present invention;
FIG. 2 is a schematic diagram of a properly displayed solid color display of a panel pixel arrangement according to the present invention;
FIG. 3 is a schematic diagram of an abnormal pure color display of a pixel arrangement structure of a panel according to the present invention;
FIG. 4 is a waveform diagram illustrating data mapping of odd source traces for an optimized pixel arrangement of a panel pixel arrangement structure according to the present invention;
FIG. 5 is a waveform diagram illustrating even source trace data mapping for an optimized pixel arrangement of a panel pixel arrangement structure according to the present invention;
FIG. 6 is a flowchart illustrating a method for driving a pixel arrangement structure of a panel according to the present invention;
description of reference numerals:
1. a pixel unit.
Detailed Description
In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
Referring to fig. 1, a technical solution provided by the present invention:
a panel pixel arrangement structure comprises more than two pixel units, a first Demux routing, a second Demux routing, a third Demux routing, a plurality of data routing and a plurality of gate routing, wherein one pixel unit is provided with two gate routing and is positioned between the two gate routing;
each pixel unit comprises six rows of sub-pixel pairs and seven data wires which are sequentially arranged from left to right, wherein two data wires are configured on one row of sub-pixel pairs and are positioned between the two data wires, and two adjacent rows of sub-pixel pairs share one data wire;
a second data wire to a seventh data wire which are sequentially arranged from left to right in one pixel unit are respectively connected with a TFT switch, the grid electrodes of the TFT switches connected with the second data wire and the third data wire which are sequentially arranged from left to right in one pixel unit are respectively electrically connected with a first Demux wire, the grid electrodes of the TFT switches connected with the fourth data wire and the fifth data wire which are sequentially arranged from left to right in one pixel unit are respectively electrically connected with a second Demux wire, and the grid electrodes of the TFT switches connected with the sixth data wire and the seventh data wire which are sequentially arranged from left to right in one pixel unit are respectively electrically connected with a third Demux wire;
the input end of each TFT switch is connected with a source wire, the TFT switches connected with a second data wire, a fourth data wire and a sixth data wire which are sequentially arranged from left to right in one pixel unit share one source wire, and the TFT switches connected with a third data wire, a fifth data wire and a seventh data wire which are sequentially arranged from left to right in one pixel unit share one source wire.
From the above description, the beneficial effects of the present invention are:
the first Demux trace controls the signal input condition of the TFT switches connected with the second data trace and the third data trace which are sequentially arranged from left to right in one pixel unit by arranging the first Demux trace, the second Demux trace and the third Demux trace to be respectively and correspondingly connected with the TFT switches in the pixel units, the second Demux trace controls the signal input condition of the TFT switches connected to the fourth data trace and the fifth data trace arranged in sequence from left to right in one pixel unit, the third Demux trace controls the signal input condition of the TFT switch connected with the sixth data trace and the seventh data trace which are sequentially arranged from left to right in one pixel unit, thus the arrangement mode of pixels in the pixel unit can be changed, therefore, the problem of poor display of the Demux liquid crystal display screen is solved, and the phenomenon of poor display of the Demux liquid crystal display screen caused by poor manufacturing process is improved; and the process cost of the process optimization is saved, the utilization rate of materials is increased, the defects caused by neglecting the process difference can be achieved, the display quality of the Demux liquid crystal display screen is improved, and the development prospect is good.
Furthermore, a first data trace sequentially arranged from left to right in one pixel unit is independently connected with a source trace.
Further, one of the sub-pixel pairs includes one sub-pixel, and all the sub-pixels in the pixel unit are sequentially arranged in an array manner of R, G and B.
Furthermore, one sub-pixel in one pixel pair is correspondingly connected with a data wire and a grid wire respectively.
Referring to fig. 2, another technical solution provided by the present invention:
a driving method of a panel pixel arrangement structure comprises the following steps:
step S1, in a pixel unit, controlling one of two grid wires to be opened;
step S2, during the period of starting one grid wire, sequentially controlling the first Demux wire, the second Demux wire and the third Demux wire to be started; during the starting period of the first Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a second data trace and a third data trace which are sequentially arranged from left to right in one pixel unit; during the starting period of the second Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a fourth data trace and a fifth data trace which are sequentially arranged from left to right in one pixel unit; during the starting period of the third Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a sixth data trace and a seventh data trace which are sequentially arranged from left to right in one pixel unit;
step S3, controlling the other grid wire of the two grid wires to be opened;
step S4, during the period of starting another grid wire, sequentially controlling the first Demux wire, the second Demux wire and the third Demux wire to be started; during the starting period of the first Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a second data trace and a third data trace which are sequentially arranged from left to right in one pixel unit; during the starting period of the second Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a fourth data trace and a fifth data trace which are sequentially arranged from left to right in one pixel unit; during the starting period of the third Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a sixth data trace and a seventh data trace which are sequentially arranged from left to right in one pixel unit;
step S5, loop through steps S1-S4, drives each pixel cell.
From the above description, the beneficial effects of the present invention are:
the first Demux trace controls the signal input condition of the TFT switches connected with the second data trace and the third data trace which are sequentially arranged from left to right in one pixel unit by arranging the first Demux trace, the second Demux trace and the third Demux trace to be respectively and correspondingly connected with the TFT switches in the pixel units, the second Demux trace controls the signal input condition of the TFT switches connected to the fourth data trace and the fifth data trace arranged in sequence from left to right in one pixel unit, the third Demux trace controls the signal input condition of the TFT switch connected with the sixth data trace and the seventh data trace which are sequentially arranged from left to right in one pixel unit, thus the arrangement mode of pixels in the pixel unit can be changed, therefore, the problem of poor display of the Demux liquid crystal display screen is solved, and the phenomenon of poor display of the Demux liquid crystal display screen caused by poor manufacturing process is improved; and the process cost of the process optimization is saved, the utilization rate of materials is increased, the defects caused by neglecting the process difference can be achieved, the display quality of the Demux liquid crystal display screen is improved, and the development prospect is good.
Referring to fig. 1 to 5, a first embodiment of the present invention is:
referring to fig. 1, a panel pixel arrangement structure includes more than two pixel units 11, a first Demux trace, a second Demux trace, a third Demux trace, a plurality of data traces (e.g., D1-D6 in fig. 1), and a plurality of gate traces (e.g., G1-G6 in fig. 1), where one of the pixel units 11 is configured with two gate traces and located between the two gate traces;
each pixel unit 1 comprises six rows of sub-pixel pairs and seven data wires which are sequentially arranged from left to right, wherein two data wires are configured on one row of sub-pixel pairs and are positioned between the two data wires, and two adjacent rows of sub-pixel pairs share one data wire;
a second data wire to a seventh data wire which are sequentially arranged from left to right in one pixel unit 1 are respectively connected with a TFT switch, the grid electrodes of the TFT switches connected with the second data wire and the third data wire which are sequentially arranged from left to right in one pixel unit 1 are respectively electrically connected with a first Demux wire, the grid electrodes of the TFT switches connected with the fourth data wire and the fifth data wire which are sequentially arranged from left to right in one pixel unit 1 are respectively electrically connected with a second Demux wire, and the grid electrodes of the TFT switches connected with the sixth data wire and the seventh data wire which are sequentially arranged from left to right in one pixel unit 1 are respectively electrically connected with a third Demux wire;
the input end of each TFT switch is connected with a source wire, the TFT switches connected with a second data wire, a fourth data wire and a sixth data wire which are sequentially arranged from left to right in one pixel unit 1 share one source wire, and the TFT switches connected with a third data wire, a fifth data wire and a seventh data wire which are sequentially arranged from left to right in one pixel unit 1 share one source wire.
The first data wire arranged in sequence from left to right in one pixel unit 1 is independently connected with a source wire.
One of the sub-pixel pairs includes one sub-pixel, and all the sub-pixels in the pixel unit 11 are sequentially arranged in an array manner of R, G and B.
And one sub-pixel in one pixel pair is correspondingly connected with a data wire and a grid wire respectively.
And the output end of the TFT switch is connected with the data routing.
Referring to FIG. 1, Demux S2 and Demux S3 are Source lines drawn from ICs, and real Source lines in panels are named D1, D2, etc.
In a pure color picture or a gray-scale picture (the two cases are easily distinguished by human eyes, and actually, a color picture also exists, but human eyes are not easy to find bright and dark vertical lines in the color picture, so the pure color picture and the gray-scale are taken as an example for explanation), for example, in the green picture, a TFT T1 controls a G pixel (green pixel) in a first row to be bright, and a TFT T2 controls a G pixel in a second row to be bright, but due to instability in the manufacturing process, the on-currents of T1 and T2 are different, and when the on-current of T1 is smaller and the on-current of T2 is larger, the G pixel in the first row (the first row of the G pixel, which is not the first row of the sub-pixels) is darker, and the G pixel in the second row is brighter.
Therefore, it is clear that what is desired is that the G pixels on the two G-Source lines are as bright as possible, that is, the G pixels on the first column are brighter than the G pixels on the second column, and that human eyes can find the G pixels on the G-Source lines well because human eyes are sensitive to green and have different brightness. In other G pixels, the opening current of each Demux TFT switch is not the same due to the difference in the manufacturing process of the Demux TFT switches in the manufacturing process, so that the Demux lcd panel will generate the phenomenon shown in fig. 3. The principle of generating bright and dark vertical lines in other pure color pictures and gray scale pictures is the same as that of generating bright and dark vertical lines in green pictures.
In a gray-scale picture, due to the fact that the opening currents of the Demux TFT switches are different, the display brightness of sub-pixels on each Source Line is different, bright and dark vertical lines are generated, and the display quality of the Demux liquid crystal display screen is affected.
In FIG. 1, due to the different SW1/SW2/SW3 switching sequences, the corresponding data mapping is also different, and there are 36 SW switching sequences, and only one SW switching sequence and the corresponding data mapping are listed here.
Fig. 2 shows a correctly displayed pure color picture (G picture), which shows no bright and dark lines, and G pixels on each Source Line can be fully charged, and the display brightness of the G pixels is consistent, so that the display effect is good.
FIG. 3 is a pure color image (G image) displayed abnormally, because the opening currents of the Demux TFT switches (such as T1/T2 in FIG. 1, there are many Demux TFT switches, and here, only the Demux TFT switch for controlling G pixels is taken as an example) are different, in FIG. 3, the darker vertical line is caused by the lower opening current of the Demux TFT switch, which makes the G pixels of the dark line not be charged to saturation, so that the displayed brightness is lower, and the dark line can be seen by human eyes; in fig. 3, the brighter vertical line is because the on-current of the Demux TFT switch is higher, so that the G pixels in the row of bright lines can be charged to saturation, and the brightness of the displayed G pixels is higher than that of the G pixels with lower on-current of the Demux TFT switch, and the bright dark line can be seen by human eyes compared with the dark line with lower brightness nearby;
referring to fig. 1, the present disclosure is directed to a phenomenon of bright and dark vertical lines appearing on a Demux lcd, and more particularly, to a pixel arrangement designed for a Demux lcd, in which S1 and Sn are not required to be connected to a Demux-Source Line (e.g., Demux S2/Demux S3), and are not required to be controlled by Demux trace (SWn), and are directly pulled from an IC into the Demux lcd. For Demux even stripes Source Line, as S2, S2 interfaces with in-plane D1/D3/D5; for the Demux odd stripe Source Line, as S3, S3 meets with in-plane D2/D4/D6. Taking a green frame as an example, the Demux lcd displays a green frame, wherein both S2 and S3 send Source voltages, and G1 is turned on, so that G pixels on D1 and D2 are driven to charge, and G pixels are bright. If the on-current of the Demux TFT switch controlling D1 is low, the charging of the G pixel on D1 is affected, and the display brightness of the G pixel cannot reach the ideal value (the display brightness of the pixel is low by X). If the on-current of the Demux TFT switch controlling D2 is normal, the G pixel charge on D2 can be saturated, and the display brightness can reach the ideal state (the display brightness of the pixel is normal by V). Thus, it is found that a rule appears in the G pixels between D1 and D2, that is, the display brightness of the previous G pixel is not ideal (x represents that the pixel has a lower display brightness), the next G pixel is displayed normally, the next G pixel is not ideal, and the display brightness of the next G pixel is ideal (v represents that the pixel has a normal display brightness), so that the G pixels with poor display and the G pixels with normal display appear repeatedly and adjacently one another, the Demux liquid crystal display displays the effect (as shown in fig. 5), the G pixels with better display brightness and the G pixels with poor display brightness are combined, and the brightness difference of the high-frequency change cannot be identified by human eyes, so that the phenomenon of bright and dark lines cannot be seen by human eyes.
The optimized pixels are matched with the Demux structure to display, so that the Dot display effect can be realized by the Source drive of Column, bright and dark lines caused by inconsistent pixel charging due to difference of process conditions of the Demux switch TFT can be avoided, and the Demux display effect is optimized.
Referring to fig. 4, in order to optimize odd Source Line mapping for pixel arrangement, the leftmost and rightmost Source lines in the Demux lcd are directly connected to S1 and Sn at the IC side, and do not need Demux trace (SW) for control. For even number of pieces of Demux Source Line (such as S2) pulled out by the Demux IC, the Demux Source Line is connected with D2/D4/D6 (such as FIG. 1) in the Demux LCD screen through a Demux TFT switch and Demux S2, and data display output from the IC to the Demux LCD screen is controlled by a Demux wire (SW); for odd strips of Demux Source Line (e.g., S3), D3/D5/D7 in the Demux lcd panel interface with Demux S3 via Demux TFT switches, and data display from the IC to the Demux lcd panel is controlled by Demux trace (SW).
As can be seen from the pixel arrangement shown in the schematic structural diagram of fig. 1, when G1 and SW1 are turned on, data of Demux S3 on the odd-numbered strip pulled out by the IC is a G pixel, and when G1 and SW2 are turned on, data of Demux S3 on the odd-numbered strip pulled out by the IC is an R pixel; when G1 and SW3 are turned on, the data of the Demux S3 on the odd tone pulled out by the IC is B pixel;
when G2 and SW1 are turned on, the data of the Demux S3 on the odd tone pulled out by the IC is B pixel; when G2 and SW2 are turned on, the data of Demux S3 on the odd tone pulled out by the IC is G pixels, and when G2 and SW3 are turned on, the data of Demux S3 on the odd strip pulled out by the IC is R pixels; when G3 is turned on, datamapping repeats the data transfer when G1 is turned on, and when G4 is turned on, datamapping repeats the data transfer when G2 is turned on. Then G isNData and G transmitted by odd Demux-Source Line when being openedN+2The same when opened; gN+1Data and G transmitted by odd Demux-Source Line when being openedN+3The same when opened; N-N +1, N-0, 1, 2 … N-1.
Referring to fig. 5, an even number of Source Line mapping for optimizing pixel arrangement is shown. For even Demux-Source lines pulled from the IC (S2). When G1 and SW1 are turned on, the data of Demux S2 on the even number strips pulled out by the IC is R pixels; when G1 and SW2 are turned on, the data of Demux S2 on the even number strips pulled out by the IC is B pixel; when G1 and SW3 are turned on, the data of Demux S2 on the even number strips pulled out by the IC is G pixels; when G2 and SW1 are turned on, the data of Demux S2 on the even number strips pulled out by the IC is G pixels; when G1 and SW2 are turned on, the data of Demux S2 on the even number strips pulled out by the IC is R pixels; when G1 and SW3 are turned on, the data of Demux S2 on the even number strips pulled out by the IC is B pixel; when G3 is turned on, datamapping repeats the data transfer when G1 is turned on, and when G4 is turned on, datamapping repeats the data transfer when G2 is turned on. Then G isNData and G transmitted by odd Demux-Source Line when being openedN+2The same when opened; gN+1Odd strips of Demu when openData and G transmitted by x-Source LineN+3The same when opened; N-N +1, N-0, 1, 2 … N-1.
Referring to fig. 1 to 6, a second embodiment of the present invention is:
referring to fig. 6, a driving method of a panel pixel arrangement structure includes the following steps:
step S1, in a pixel unit 1, controlling one of the two gate lines to open;
step S2, during the period of starting one grid wire, sequentially controlling the first Demux wire, the second Demux wire and the third Demux wire to be started; during the starting period of the first Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a second data trace and a third data trace which are sequentially arranged from left to right in one pixel unit 1; during the starting period of the second Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a fourth data trace and a fifth data trace which are sequentially arranged from left to right in one pixel unit 1; during the starting period of the third Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a sixth data trace and a seventh data trace which are sequentially arranged from left to right in one pixel unit 1;
step S3, controlling the other grid wire of the two grid wires to be opened;
step S4, during the period of starting another grid wire, sequentially controlling the first Demux wire, the second Demux wire and the third Demux wire to be started; during the starting period of the first Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a second data trace and a third data trace which are sequentially arranged from left to right in one pixel unit 1; during the starting period of the second Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a fourth data trace and a fifth data trace which are sequentially arranged from left to right in one pixel unit 1; during the starting period of the third Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a sixth data trace and a seventh data trace which are sequentially arranged from left to right in one pixel unit 1;
step S5, loop through steps S1-S4, drives each pixel cell 1.
Referring to FIG. 1, Demux S2 and Demux S3 are Source lines drawn from ICs, and real Source lines in panels are named D1, D2, etc.
In a pure color picture or a gray-scale picture (the two cases are easily distinguished by human eyes, and actually, a color picture also exists, but human eyes are not easy to find bright and dark vertical lines in the color picture, so the pure color picture and the gray-scale are taken as an example for explanation), for example, in the green picture, a TFT T1 controls a G pixel (green pixel) in a first row to be bright, and a TFT T2 controls a G pixel in a second row to be bright, but due to instability in the manufacturing process, the on-currents of T1 and T2 are different, and when the on-current of T1 is smaller and the on-current of T2 is larger, the G pixel in the first row (the first row of the G pixel, which is not the first row of the sub-pixels) is darker, and the G pixel in the second row is brighter.
Therefore, it is clear that what is desired is that the G pixels on the two G-Source lines are as bright as possible, that is, the G pixels on the first column are brighter than the G pixels on the second column, and that human eyes can find the G pixels on the G-Source lines well because human eyes are sensitive to green and have different brightness. In other G pixels, the opening current of each Demux TFT switch is not the same due to the difference in the manufacturing process of the Demux TFT switches in the manufacturing process, so that the Demux lcd panel will generate the phenomenon shown in fig. 3. The principle of generating bright and dark vertical lines in other pure color pictures and gray scale pictures is the same as that of generating bright and dark vertical lines in green pictures.
In a gray-scale picture, due to the fact that the opening currents of the Demux TFT switches are different, the display brightness of sub-pixels on each Source Line is different, bright and dark vertical lines are generated, and the display quality of the Demux liquid crystal display screen is affected.
In FIG. 1, due to the different SW1/SW2/SW3 switching sequences, the corresponding data mapping is also different, and there are 36 SW switching sequences, and only one SW switching sequence and the corresponding data mapping are listed here.
Fig. 2 shows a correctly displayed pure color picture (G picture), which shows no bright and dark lines, and G pixels on each Source Line can be fully charged, and the display brightness of the G pixels is consistent, so that the display effect is good.
FIG. 3 is a pure color image (G image) displayed abnormally, because the opening currents of the Demux TFT switches (such as T1/T2 in FIG. 1, there are many Demux TFT switches, and here, only the Demux TFT switch for controlling G pixels is taken as an example) are different, in FIG. 3, the darker vertical line is caused by the lower opening current of the Demux TFT switch, which makes the G pixels of the dark line not be charged to saturation, so that the displayed brightness is lower, and the dark line can be seen by human eyes; in fig. 3, the brighter vertical line is because the on-current of the Demux TFT switch is higher, so that the G pixels in the row of bright lines can be charged to saturation, and the brightness of the displayed G pixels is higher than that of the G pixels with lower on-current of the Demux TFT switch, and the bright dark line can be seen by human eyes compared with the dark line with lower brightness nearby;
referring to fig. 1, the present disclosure is directed to a phenomenon of bright and dark vertical lines appearing on a Demux lcd, and more particularly, to a pixel arrangement designed for a Demux lcd, in which S1 and Sn are not required to be connected to a Demux-Source Line (e.g., Demux S2/Demux S3), and are not required to be controlled by Demux trace (SWn), and are directly pulled from an IC into the Demux lcd. For Demux even stripes Source Line, as S2, S2 interfaces with in-plane D1/D3/D5; for the Demux odd stripe Source Line, as S3, S3 meets with in-plane D2/D4/D6. Taking a green frame as an example, the Demux lcd displays a green frame, wherein both S2 and S3 send Source voltages, and G1 is turned on, so that G pixels on D1 and D2 are driven to charge, and G pixels are bright. If the on-current of the Demux TFT switch controlling D1 is low, the charging of the G pixel on D1 is affected, and the display brightness of the G pixel cannot reach the ideal value (the display brightness of the pixel is low by X). If the on-current of the Demux TFT switch controlling D2 is normal, the G pixel charge on D2 can be saturated, and the display brightness can reach the ideal state (the display brightness of the pixel is normal by V). Thus, it is found that a rule appears in the G pixels between D1 and D2, that is, the display brightness of the previous G pixel is not ideal (x represents that the pixel has a lower display brightness), the next G pixel is displayed normally, the next G pixel is not ideal, and the display brightness of the next G pixel is ideal (v represents that the pixel has a normal display brightness), so that the G pixels with poor display and the G pixels with normal display appear repeatedly and adjacently one another, the Demux liquid crystal display displays the effect (as shown in fig. 5), the G pixels with better display brightness and the G pixels with poor display brightness are combined, and the brightness difference of the high-frequency change cannot be identified by human eyes, so that the phenomenon of bright and dark lines cannot be seen by human eyes.
The optimized pixels are matched with the Demux structure to display, so that the Dot display effect can be realized by the Source drive of Column, bright and dark lines caused by inconsistent pixel charging due to difference of process conditions of the Demux switch TFT can be avoided, and the Demux display effect is optimized.
Referring to fig. 4, in order to optimize odd Source Line mapping for pixel arrangement, the leftmost and rightmost Source lines in the Demux lcd are directly connected to S1 and Sn at the IC side, and do not need Demux trace (SW) for control. For even number of pieces of Demux Source Line (such as S2) pulled out by the Demux IC, the Demux Source Line is connected with D2/D4/D6 (such as FIG. 1) in the Demux LCD screen through a Demux TFT switch and Demux S2, and data display output from the IC to the Demux LCD screen is controlled by a Demux wire (SW); for odd strips of Demux Source Line (e.g., S3), D3/D5/D7 in the Demux lcd panel interface with Demux S3 via Demux TFT switches, and data display from the IC to the Demux lcd panel is controlled by Demux trace (SW).
As can be seen from the pixel arrangement shown in the schematic structural diagram of fig. 1, when G1 and SW1 are turned on, data of Demux S3 on the odd-numbered strip pulled out by the IC is a G pixel, and when G1 and SW2 are turned on, data of Demux S3 on the odd-numbered strip pulled out by the IC is an R pixel; when G1 and SW3 are turned on, the data of the Demux S3 on the odd tone pulled out by the IC is B pixel;
when G2 and SW1 are turned on, the data of the Demux S3 on the odd tone pulled out by the IC is B pixel; when G2 and SW2 are turned on, the data of Demux S3 on the odd tone pulled out by the IC is G pixels, and when G2 and SW3 are turned on, the data of Demux S3 on the odd strip pulled out by the IC is R pixels; when G3 is open, datamapping is heavyAnd repeating the data transmission when G1 is turned on, and when G4 is turned on, datamapping repeats the data transmission when G2 is turned on. Then G isNData and G transmitted by odd Demux-Source Line when being openedN+2The same when opened; gN+1Data and G transmitted by odd Demux-Source Line when being openedN+3The same when opened; N-N +1, N-0, 1, 2 … N-1.
Referring to fig. 5, an even number of Source Line mapping for optimizing pixel arrangement is shown. For even Demux-Source lines pulled from the IC (S2). When G1 and SW1 are turned on, the data of Demux S2 on the even number strips pulled out by the IC is R pixels; when G1 and SW2 are turned on, the data of Demux S2 on the even number strips pulled out by the IC is B pixel; when G1 and SW3 are turned on, the data of Demux S2 on the even number strips pulled out by the IC is G pixels; when G2 and SW1 are turned on, the data of Demux S2 on the even number strips pulled out by the IC is G pixels; when G1 and SW2 are turned on, the data of Demux S2 on the even number strips pulled out by the IC is R pixels; when G1 and SW3 are turned on, the data of Demux S2 on the even number strips pulled out by the IC is B pixel; when G3 is turned on, datamapping repeats the data transfer when G1 is turned on, and when G4 is turned on, datamapping repeats the data transfer when G2 is turned on. Then G isNData and G transmitted by odd Demux-Source Line when being openedN+2The same when opened; gN+1Data and G transmitted by odd Demux-Source Line when being openedN+3The same when opened; N-N +1, N-0, 1, 2 … N-1.
In summary, according to the panel pixel arrangement structure and the driving method thereof provided by the present invention, by setting the first Demux trace, the second Demux trace and the third Demux trace to be respectively and correspondingly connected to the TFT switches in the pixel units, the first Demux trace controls the signal input condition of the TFT switches connected to the second data trace and the third data trace sequentially arranged from left to right in one pixel unit, the second Demux trace controls the signal input condition of the TFT switches connected to the fourth data trace and the fifth data trace sequentially arranged from left to right in one pixel unit, the third Demux trace controls the signal input condition of the TFT switches connected to the sixth data trace and the seventh data trace sequentially arranged from left to right in one pixel unit, so that the arrangement manner in the pixel units can be changed, thereby improving the problem of poor pixel display of the Demux liquid crystal display screen, the phenomenon of poor display of the Demux liquid crystal display screen caused by poor manufacturing process is improved; and the process cost of the process optimization is saved, the utilization rate of materials is increased, the defects caused by neglecting the process difference can be achieved, the display quality of the Demux liquid crystal display screen is improved, and the development prospect is good.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.

Claims (6)

1. A panel pixel arrangement structure is characterized by comprising more than two pixel units, a first Demux routing, a second Demux routing, a third Demux routing, a plurality of data routing and a plurality of gate routing, wherein one pixel unit is provided with two gate routing and is positioned between the two gate routing;
each pixel unit comprises six rows of sub-pixel pairs and seven data wires which are sequentially arranged from left to right, wherein two data wires are configured on one row of sub-pixel pairs and are positioned between the two data wires, and two adjacent rows of sub-pixel pairs share one data wire;
a second data wire to a seventh data wire which are sequentially arranged from left to right in one pixel unit are respectively connected with a TFT switch, the grid electrodes of the TFT switches connected with the second data wire and the third data wire which are sequentially arranged from left to right in one pixel unit are respectively electrically connected with a first Demux wire, the grid electrodes of the TFT switches connected with the fourth data wire and the fifth data wire which are sequentially arranged from left to right in one pixel unit are respectively electrically connected with a second Demux wire, and the grid electrodes of the TFT switches connected with the sixth data wire and the seventh data wire which are sequentially arranged from left to right in one pixel unit are respectively electrically connected with a third Demux wire;
the input end of each TFT switch is connected with a source wire, the TFT switches connected with a second data wire, a fourth data wire and a sixth data wire which are sequentially arranged from left to right in one pixel unit share one source wire, and the TFT switches connected with a third data wire, a fifth data wire and a seventh data wire which are sequentially arranged from left to right in one pixel unit share one source wire.
2. The panel pixel arrangement structure of claim 1, wherein a first data trace sequentially arranged from left to right in one pixel unit is individually connected to a source trace.
3. The panel pixel arrangement structure of claim 1, wherein one of the sub-pixel pairs comprises one sub-pixel, and all sub-pixels in the pixel unit are sequentially arranged in an array of R, G and B.
4. The panel pixel arrangement structure of claim 1, wherein one sub-pixel of one pixel pair is correspondingly connected to a data trace and a gate trace, respectively.
5. The panel pixel arrangement structure of claim 1, wherein the output terminal of the TFT switch is connected to the data trace.
6. A driving method of a panel pixel arrangement structure, applied to the panel pixel arrangement structure of any one of claims 1 to 5, comprising the steps of:
step S1, in a pixel unit, controlling one of two grid wires to be opened;
step S2, during the period of starting one grid wire, sequentially controlling the first Demux wire, the second Demux wire and the third Demux wire to be started; during the starting period of the first Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a second data trace and a third data trace which are sequentially arranged from left to right in one pixel unit; during the starting period of the second Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a fourth data trace and a fifth data trace which are sequentially arranged from left to right in one pixel unit; during the starting period of the third Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a sixth data trace and a seventh data trace which are sequentially arranged from left to right in one pixel unit;
step S3, controlling the other grid wire of the two grid wires to be opened;
step S4, during the period of starting another grid wire, sequentially controlling the first Demux wire, the second Demux wire and the third Demux wire to be started; during the starting period of the first Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a second data trace and a third data trace which are sequentially arranged from left to right in one pixel unit; during the starting period of the second Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a fourth data trace and a fifth data trace which are sequentially arranged from left to right in one pixel unit; during the starting period of the third Demux trace, controlling the source trace to transmit signals to a pixel pair connected with a sixth data trace and a seventh data trace which are sequentially arranged from left to right in one pixel unit;
step S5, loop through steps S1-S4, drives each pixel cell.
CN202110338708.8A 2021-03-30 2021-03-30 Panel pixel arrangement structure and driving method thereof Pending CN113156726A (en)

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Publication number Priority date Publication date Assignee Title
KR20050003753A (en) * 2003-07-04 2005-01-12 엘지.필립스 엘시디 주식회사 Liquid crystal display and method of driving the same
KR20170031323A (en) * 2015-09-10 2017-03-21 삼성디스플레이 주식회사 Display device
CN112309260A (en) * 2020-11-09 2021-02-02 福建华佳彩有限公司 Display screen structure and driving method thereof
CN215219384U (en) * 2021-03-30 2021-12-17 福建华佳彩有限公司 Panel pixel arrangement structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050003753A (en) * 2003-07-04 2005-01-12 엘지.필립스 엘시디 주식회사 Liquid crystal display and method of driving the same
KR20170031323A (en) * 2015-09-10 2017-03-21 삼성디스플레이 주식회사 Display device
CN112309260A (en) * 2020-11-09 2021-02-02 福建华佳彩有限公司 Display screen structure and driving method thereof
CN215219384U (en) * 2021-03-30 2021-12-17 福建华佳彩有限公司 Panel pixel arrangement structure

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