CN113141185A - Construction method and device of LDPC code check matrix - Google Patents
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
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Abstract
The invention discloses a construction method of an LDPC code check matrix, which comprises the following steps: setting at least one of a row weight λ and a column weight γ of the LDPC check matrix as a fixed value (constant); setting z of dimension z × z of the cyclic permutation matrix CPM to a predetermined value; calculating to obtain a base matrix of a corresponding LDPC code check matrix based on the LDPC code length, the code rate, the row weight lambda, the column weight gamma and the dimension zxz of the cyclic permutation matrix CPM; and obtaining the LDPC check matrix through the expansion of the base matrix. According to the technical scheme provided by the invention, the code length of the LDPC code is shortened, so that the transmission of small data volume can be carried out in less OFDM symbols (as low as 1 symbol), thereby effectively reducing time delay and overhead. The regular/quasi-regular LDPC code has a very low error code platform, and the transmission reliability is improved.
Description
Technical Field
The invention belongs to the technical field of mobile communication, and particularly relates to a construction method and a device of an LDPC code check matrix for mobile communication.
Background
The ITU has established three major application scenarios of 5G, namely eMBB (enhanced Mobile Broadband), mtc (large Machine Type Communication), and URLLC (Ultra-Reliable and Low Latency Communication). At present, the 5G initial construction of operators is mainly oriented to the eMBB service.
With the rise of Industrial Internet of Things (IIoT) and the proposal of industry 4.0, the application of uRLLC in the field of IIoT is obtainedThere is an increasing interest. The method has the advantages that the demands of various scenes in the IIoT field on time delay and reliability are provided, specifically, in the 5G initial stage, the uRLLC is mainly applied to the fields of Virtual Reality (VR), Augmented Reality (AR) and the like, and the requirements of 1ms user interface time delay and less than 10 packet error rate are met-5The reliability requirements of. With the further development of IIoT, the URLLC service will be more applied to the fields of factory automation (motion control, control-to-control communication), transmission industry (remote driving), and power distribution (smart grid), which place higher demands on time delay and reliability, and in particular, the requirement of remote driving is to realize 10 ms user plane time delay-5The power distribution system requires a 2ms user plane delay to achieve 10-6Reliability of (1 ms), and a factory automation scenario requiring 10 implementation with 1ms user plane delay-6The reliability of (2).
With respect to the development of reliability and bottom delay research of URLLC application scenarios, the delay reduction scheme proposed in 3GPP Rel-15 stage includes:
(1) more flexible frame structures are supported: 4G LTE only supports a subcarrier spacing of 15kHz, each subframe (fixed length 1ms) contains two slots, each slot containing 7 OFDM symbols. The 5G/NR supports various subcarrier intervals, the frequency band below sub-6GHz can support subcarrier interval configuration such as 15kHz/30kHz/60kHz, and each subframe (with the fixed length of 1ms) comprises 2 mu time slots, so that the transmission time of each Slot on an air interface is reduced.
(2) Supporting more flexible scheduling units: the minimum scheduling unit of 4G scheduling is a time slot, and 5G supports mini-slot (minimum 2 symbols) scheduling, which is a micro-slot.
(3) Support URLLC high priority transmission: in order to guarantee the requirement of the URLLC service with high priority, 5G/NR provides that the URLLC service can occupy eMBB service resources to reduce time delay.
(4) The Mobile Edge Computing (MEC) technology is introduced, and a general server is deployed on the wireless Access side, so that a wireless Access Network (RAN) has IT and cloud Computing capabilities, thereby realizing service localization and reducing the transmission delay of data from a base station to a core Network.
In order to further meet the requirements of high reliability and ultra-low delay of URLLC, more technical solutions and means need to be proposed.
Disclosure of Invention
In view of the above, the technical problem to be solved by the present invention is to provide a method and an apparatus for constructing an LDPC code in mobile communication, so as to adapt to new application scenarios and requirements.
The construction method of the LDPC code check matrix provided by the embodiment of the invention comprises the following steps:
setting at least one of a row weight λ and a column weight γ of the LDPC check matrix as a fixed value (constant);
setting z of dimension z × z of the cyclic permutation matrix CPM to a predetermined value;
calculating to obtain a base matrix of a corresponding LDPC code check matrix based on the LDPC code length, the code rate, the row weight lambda, the column weight gamma and the dimension zxz of the cyclic permutation matrix CPM;
and obtaining the LDPC check matrix through the expansion of the base matrix.
Preferably, the LDPC code length is 448; and/or
When the code rate is 1/2, the corresponding code is a (448,224) LDPC code.
When the code rate is 4/7, the corresponding code is a (448,256) LDPC code.
Preferably, z is 28, the dimension corresponding to CPM is 28 × 28, and the method is characterized in that the row weight λ is 6, the column weight γ is 3, and the code is a regular LDPC code; or
Preferably, z is 32, corresponding to CPM with dimension 32 × 32, characterized by row weight λ of 8 and column weight γ of 3 or 4, which is a quasi-regular LDPC code.
In this embodiment, preferably, when the LDPC code length is 448 and the code rate is 1/2, the base matrix of the check matrix of the corresponding (448,224) LDPC code is:
| -1 | -1 | 6 | -1 | 27 | -1 | -1 | 20 | -1 | -1 | 22 | -1 | -1 | 7 | 13 | -1 |
| -1 | -1 | -1 | 6 | -1 | 27 | 0 | -1 | -1 | -1 | -1 | 22 | 21 | -1 | -1 | 13 |
| 19 | -1 | -1 | -1 | -1 | 9 | 27 | -1 | -1 | 20 | -1 | -1 | 22 | -1 | -1 | 7 |
| -1 | 19 | -1 | -1 | 10 | -1 | -1 | 27 | 0 | -1 | -1 | -1 | -1 | 22 | 21 | -1 |
| -1 | 25 | -1 | 3 | -1 | -1 | 6 | -1 | 27 | -1 | -1 | 20 | -1 | -1 | -1 | 21 |
| 10 | -1 | 25 | -1 | -1 | -1 | -1 | 6 | -1 | 27 | 0 | -1 | -1 | -1 | 3 | -1 |
| -1 | 10 | -1 | 25 | 19 | -1 | -1 | -1 | 6 | -1 | -1 | 0 | -1 | 20 | -1 | -1 |
| 2 | -1 | 10 | -1 | -1 | 19 | -1 | -1 | -1 | 6 | 9 | -1 | 0 | -1 | -1 | -1 |
in the specific embodiment, preferably, when the LDPC code length is 448 and the code rate is 4/7, the base matrix of the check matrix of the corresponding (448,256) LDPC code is:
| 4 | 14 | 13 | -1 | 5 | 21 | -1 | 15 | -1 | 11 | -1 | -1 | 7 | -1 |
| -1 | 1 | 15 | 2 | -1 | 6 | -1 | 4 | 0 | -1 | 11 | -1 | -1 | 8 |
| 9 | -1 | 2 | 14 | 3 | -1 | 7 | -1 | 5 | 13 | -1 | 12 | -1 | -1 |
| -1 | 10 | -1 | 10 | 15 | 4 | -1 | -1 | -1 | 14 | 6 | -1 | 13 | 5 |
| 6 | -1 | 11 | -1 | 10 | -1 | 5 | 12 | -1 | -1 | 13 | 7 | -1 | 14 |
| 15 | 7 | -1 | 3 | -1 | -1 | 20 | -1 | 13 | -1 | -1 | 14 | 8 | 4 |
the LDPC check matrix is obtained by expanding a base matrix, and specifically comprises the following steps:
each element of the base matrix is replaced by a cyclic permutation matrix CPM, and the dimension of the CPM is z multiplied by z; when the element value of the base matrix is more than or equal to 0, the CPM is the row cyclic shift of the unit matrix of z multiplied by z, and the element value represents the right shift number of 1 in the first row of the CPM; when the element value of the base matrix is less than 0, the CPM is a z multiplied by z all-zero matrix; the rule of the row cyclic shift is: assuming that the element value of the base matrix is s, each row of the unit matrix of z × z is cyclically shifted by the number of times of s.
An embodiment of the present invention further provides a device for constructing an LDPC code check matrix, including:
a setting unit configured to set at least one of a row weight λ and a column weight γ of the LDPC check matrix as a fixed value (constant);
the device comprises a presetting unit, a processing unit and a processing unit, wherein the presetting unit is used for setting z of dimension z multiplied by z of a cyclic permutation matrix CPM as a preset value;
the processing unit is used for calculating a base matrix of the LDPC code check matrix based on the LDPC code length, the code rate, the row weight lambda, the column weight gamma and the dimension zxz cyclic permutation matrix CPM;
and the generating unit is used for obtaining the LDPC check matrix through base matrix expansion.
Preferably, the LDPC code length is 448; and/or
When the code rate is 1/2, the corresponding code is a (448,224) LDPC code;
when the code rate is 4/7, the corresponding code is a (448,256) LDPC code.
Preferably, z is 28, the dimension corresponding to CPM is 28 × 28, and the LDPC code is characterized in that the row weight λ is 6 and the column weight γ is 3, and is a regular LDPC code; or
Preferably, z is 32, corresponding to CPM with dimension 32 × 32, characterized by row weight λ of 8 and column weight γ of 3 or 4, and is a quasi-regular LDPC code.
Preferably, when the LDPC code length is 448 and the code rate is 1/2, the base matrix of the check matrix of the corresponding (448,224) LDPC code is:
| -1 | -1 | 6 | -1 | 27 | -1 | -1 | 20 | -1 | -1 | 22 | -1 | -1 | 7 | 13 | -1 |
| -1 | -1 | -1 | 6 | -1 | 27 | 0 | -1 | -1 | -1 | -1 | 22 | 21 | -1 | -1 | 13 |
| 19 | -1 | -1 | -1 | -1 | 9 | 27 | -1 | -1 | 20 | -1 | -1 | 22 | -1 | -1 | 7 |
| -1 | 19 | -1 | -1 | 10 | -1 | -1 | 27 | 0 | -1 | -1 | -1 | -1 | 22 | 21 | -1 |
| -1 | 25 | -1 | 3 | -1 | -1 | 6 | -1 | 27 | -1 | -1 | 20 | -1 | -1 | -1 | 21 |
| 10 | -1 | 25 | -1 | -1 | -1 | -1 | 6 | -1 | 27 | 0 | -1 | -1 | -1 | 3 | -1 |
| -1 | 10 | -1 | 25 | 19 | -1 | -1 | -1 | 6 | -1 | -1 | 0 | -1 | 20 | -1 | -1 |
| 2 | -1 | 10 | -1 | -1 | 19 | -1 | -1 | -1 | 6 | 9 | -1 | 0 | -1 | -1 | -1 |
preferably, when the LDPC code length is 448 and the code rate is 4/7, a base matrix of a check matrix of the corresponding (448,256) LDPC code:
according to the technical scheme provided by the invention, the code length of the LDPC code is shortened, so that the transmission of small data volume can be carried out in less OFDM symbols (as low as 1 symbol), thereby effectively reducing time delay and overhead. The regular/quasi-regular LDPC code has a very low error code platform, and the transmission reliability is improved.
For the purposes of the foregoing and related ends, the one or more embodiments include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects and are indicative of but a few of the various ways in which the principles of the various embodiments may be employed. Other benefits and novel features will become apparent from the following detailed description when considered in conjunction with the drawings and the disclosed embodiments are intended to include all such aspects and their equivalents.
Drawings
FIG. 1 is a flow chart of a method for constructing an LDPC code check matrix provided by the present invention;
fig. 2 is a schematic diagram of an apparatus for constructing an LDPC code check matrix according to an embodiment of the present invention.
Detailed Description
The following description and the drawings sufficiently illustrate specific embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. The scope of embodiments of the invention encompasses the full ambit of the claims, as well as all available equivalents of the claims. Embodiments of the invention may be referred to herein, individually or collectively, by the term "invention" merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed.
The technical solution and characteristics of the present invention are described below.
In channel coding, the data bit sequence output by scrambling is processed
FEC protection is carried out, and two forward error correction codes of convolution coding and LDPC coding are supported.
In order to meet the requirement of ultra-low time delay of URLLC, a better solution is provided, and the time delay is effectively reduced.
Under the scenes of URLLC, mMTC and the like, the transmission data bytes are very small (within 32-byte), 1344/2688/5376 code lengths of LDPC are adopted to cause larger redundancy overhead, and in the scheme provided by the invention, the LDPC design of increasing 448 code lengths is adopted to meet the requirements of low time delay and low overhead.
The LDPC code is a packet error correcting code with excellent performance, and has the characteristics of sparse check matrix and easy parallel decoding. When N denotes a code length of an LDPC code, K denotes an information bit length, M denotes a check bit length, γ denotes a column length, λ denotes a row weight, and R denotes a code rate, the LDPC code may be expressed as an (N, K) LDPC code, and the corresponding code rate R is K/N. If γ and λ are constants, the LDPC code is a Regular LDPC code (Regular LDPC), otherwise, it is an Irregular LDPC code (Irregular LDPC). If only one of γ and λ is constant, the LDPC code is a Quasi-Regular LDPC code (Quasi Regular LDPC).
Referring to fig. 1, the method for constructing an LDPC code check matrix provided by the present invention includes:
s101, setting at least one of row weight lambda and column weight gamma of the LDPC check matrix as a fixed value (constant);
s102, setting the dimension z multiplied by z of the cyclic permutation matrix CPM as a preset value;
s103, calculating to obtain a base matrix of a corresponding LDPC code check matrix based on the LDPC code length, code rate, row weight lambda, column weight gamma and dimension zxz cyclic permutation matrix CPM;
and S104, obtaining the LDPC check matrix through the expansion of the base matrix.
In a specific embodiment, in step S104, the LDPC check matrix is obtained through base matrix extension, specifically:
each element of the base matrix is replaced by a cyclic permutation matrix CPM, and the dimension of the CPM is z multiplied by z; when the element value of the base matrix is more than or equal to 0, the CPM is the row cyclic shift of the unit matrix of z multiplied by z, and the element value represents the right shift number of 1 in the first row of the CPM; when the element value of the base matrix is less than 0, the CPM is a z multiplied by z all-zero matrix;
the rule of the row cyclic shift is: assuming that the element value of the base matrix is s, each row of the unit matrix of z × z is cyclically shifted by the number of times of s.
In the technical scheme of the invention, the LDPC code length is 448, the code rates are 1/2 and 4/7, and the corresponding (448,224) LDPC code and (448,256) LDPC code are compared. Both check matrices have a QC (quasi-cyclic) structure. (448,224) the LDPC code is a regular code, and (448,256) the LDPC code is a quasi-regular code.
For example, when z is 5 and s is 2, the matrix obtained by cyclically shifting the unit matrix and the rows is as follows:
5 × 5 identity matrix:
matrix after cyclic shift of rows 2 times:
when the LDPC code length is 448 and the code rate is 1/2, a base matrix of a check matrix of the corresponding (448,224) LDPC code is as shown in table 1, z is 28, and a dimension corresponding to CPM is 28 × 28. The method is characterized in that the row weight lambda is 6, the column weight gamma is 3, and the code is a regular LDPC code.
TABLE 1(448,224) base matrix of check matrix for LDPC codes
| -1 | -1 | 6 | -1 | 27 | -1 | -1 | 20 | -1 | -1 | 22 | -1 | -1 | 7 | 13 | -1 |
| -1 | -1 | -1 | 6 | -1 | 27 | 0 | -1 | -1 | -1 | -1 | 22 | 21 | -1 | -1 | 13 |
| 19 | -1 | -1 | -1 | -1 | 9 | 27 | -1 | -1 | 20 | -1 | -1 | 22 | -1 | -1 | 7 |
| -1 | 19 | -1 | -1 | 10 | -1 | -1 | 27 | 0 | -1 | -1 | -1 | -1 | 22 | 21 | -1 |
| -1 | 25 | -1 | 3 | -1 | -1 | 6 | -1 | 27 | -1 | -1 | 20 | -1 | -1 | -1 | 21 |
| 10 | -1 | 25 | -1 | -1 | -1 | -1 | 6 | -1 | 27 | 0 | -1 | -1 | -1 | 3 | -1 |
| -1 | 10 | -1 | 25 | 19 | -1 | -1 | -1 | 6 | -1 | -1 | 0 | -1 | 20 | -1 | -1 |
| 2 | -1 | 10 | -1 | -1 | 19 | -1 | -1 | -1 | 6 | 9 | -1 | 0 | -1 | -1 | -1 |
When the LDPC code length is 448 and the code rate is 4/7, a base matrix of a check matrix of the corresponding (448,256) LDPC code is as shown in table 2, z is 32, and a dimension corresponding to CPM is 32 × 32. The method is characterized in that the row weight lambda is 8, the column weight gamma is 3 or 4, and the LDPC code is a quasi-regular LDPC code.
TABLE 2(448,256) base matrix of check matrix for LDPC codes
An embodiment of the present invention further provides an apparatus 20 for constructing an LDPC code check matrix, as shown in fig. 2, including:
a setting unit 210 configured to set at least one of a row weight λ and a column weight γ of the LDPC check matrix as a fixed value (constant);
a presetting unit 220, configured to set z of a dimension z × z of the cyclic permutation matrix CPM to a predetermined value;
the processing unit 230 is configured to obtain a base matrix of the LDPC code check matrix through calculation based on the LDPC code length, the code rate, the row weight λ, the column weight γ, and the dimension zxz cyclic permutation matrix CPM;
and the generating unit 240 obtains the LDPC check matrix through base matrix expansion.
In the embodiment, the length of the LDPC code is 448; and/or
When the code rate is 1/2, the corresponding code is a (448,224) LDPC code;
when the code rate is 4/7, the corresponding code is a (448,256) LDPC code.
In a specific embodiment, the preferred parameters are as follows:
z is 28, the dimensionality corresponding to CPM is 28 multiplied by 28, the method is characterized in that the row weight lambda is 6, the column weight gamma is 3, and the obtained LDPC code is a regular LDPC code; or
And z is 32, the dimension corresponding to CPM is 32 multiplied by 32, the row weight lambda is 8, the column weight gamma is 3 or 4, and the obtained LDPC code is a quasi-regular LDPC code.
In summary, in the technical solution provided by the present invention, the code length of the LDPC code is shortened, so that the transmission of a small data amount can be performed in fewer OFDM symbols (as low as 1 symbol), thereby effectively reducing the delay and the overhead.
Those of skill in the art will understand that the various exemplary method steps and apparatus elements described in connection with the embodiments disclosed herein can be implemented as electronic hardware, software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative steps and elements have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method described in connection with the embodiments disclosed above may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a subscriber station. In the alternative, the processor and the storage medium may reside as discrete components in a subscriber station.
The disclosed embodiments are provided to enable those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the scope or spirit of the invention. The above-described embodiments are merely preferred embodiments of the present invention, which should not be construed as limiting the invention, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (11)
1. A construction method of an LDPC code check matrix is characterized by comprising the following steps:
setting at least one of a row weight λ and a column weight γ of the LDPC check matrix as a fixed value (constant);
setting z of dimension z × z of the cyclic permutation matrix CPM to a predetermined value;
calculating to obtain a base matrix of a corresponding LDPC code check matrix based on the LDPC code length, the code rate, the row weight lambda, the column weight gamma and the dimension zxz of the cyclic permutation matrix CPM;
and obtaining the LDPC check matrix through the expansion of the base matrix.
2. The method of constructing an LDPC code check matrix according to claim 1, wherein the LDPC code length is 448; and/or
When the code rate is 1/2, the corresponding code is a (448,224) LDPC code;
when the code rate is 4/7, the corresponding code is a (448,256) LDPC code.
3. The method of claim 1, wherein z is 28, the dimension of CPM is 28 × 28, and the LDPC check matrix is a regular LDPC code with a row weight λ of 6 and a column weight γ of 3; or
And z is 32, the dimension of the corresponding CPM is 32 multiplied by 32, the characteristic is that the row weight lambda is 8, the column weight gamma is 3 or 4, and the LDPC code is quasi-regular.
4. The method of constructing a check matrix of an LDPC code according to claim 2 or 3, wherein when the LDPC code has a length of 448 and a code rate of 1/2, the base matrix of the check matrix of the corresponding (448,224) LDPC code is:
5. the method of constructing a check matrix of an LDPC code according to claim 2 or 3, wherein when the LDPC code has a length of 448 and a code rate of 4/7, the base matrix of the check matrix of the corresponding (448,256) LDPC code is:
6. the method for constructing the LDPC check matrix according to claim 1, wherein the obtaining of the LDPC check matrix through the base matrix extension comprises:
each element of the base matrix is replaced by a cyclic permutation matrix CPM, and the dimension of the CPM is z multiplied by z; when the element value of the base matrix is more than or equal to 0, the CPM is the row cyclic shift of the unit matrix of z multiplied by z, and the element value represents the right shift number of 1 in the first row of the CPM; when the element value of the base matrix is less than 0, the CPM is a z multiplied by z all-zero matrix; the rule of the row cyclic shift is: assuming that the element value of the base matrix is s, each row of the unit matrix of z × z is cyclically shifted by the number of times of s.
7. An apparatus for constructing a check matrix for an LDPC code, comprising:
a setting unit configured to set at least one of a row weight λ and a column weight γ of the LDPC check matrix as a fixed value (constant);
the device comprises a presetting unit, a processing unit and a processing unit, wherein the presetting unit is used for setting z of dimension z multiplied by z of a cyclic permutation matrix CPM as a preset value;
the processing unit is used for calculating a base matrix of the LDPC code check matrix based on the LDPC code length, the code rate, the row weight lambda, the column weight gamma and the dimension zxz cyclic permutation matrix CPM;
and the generating unit is used for obtaining the LDPC check matrix through base matrix expansion.
8. The apparatus for constructing an LDPC code check matrix according to claim 7, wherein the LDPC code length is 448; and/or
When the code rate is 1/2, the corresponding code is a (448,224) LDPC code;
when the code rate is 4/7, the corresponding code is a (448,256) LDPC code.
9. The apparatus of claim 7, wherein z is 28, corresponding to CPM with dimension 28 x 28, and is characterized by row weight λ of 6 and column weight γ of 3, which is a regular LDPC code; or
And z is 32, the dimension of the corresponding CPM is 32 multiplied by 32, the characteristic is that the row weight lambda is 8, the column weight gamma is 3 or 4, and the LDPC code is quasi-regular.
10. The apparatus for constructing a check matrix of an LDPC code as claimed in claim 7, wherein when the LDPC code length is 448 and the code rate is 1/2, a base matrix of the check matrix of the corresponding (448,224) LDPC code is:
when the LDPC code length is 448 and the code rate is 4/7, a base matrix of a check matrix of a corresponding (448,256) LDPC code:
11. the apparatus for constructing an LDPC code check matrix as claimed in claim 9, wherein the generating unit obtains the LDPC check matrix by base matrix expansion, comprising:
each element of the base matrix is replaced by a cyclic permutation matrix CPM, and the dimension of the CPM is z multiplied by z; when the element value of the base matrix is more than or equal to 0, the CPM is the row cyclic shift of the unit matrix of z multiplied by z, and the element value represents the right shift number of 1 in the first row of the CPM; when the element value of the base matrix is less than 0, the CPM is a z multiplied by z all-zero matrix; the rule of the row cyclic shift is: assuming that the element value of the base matrix is s, each row of the unit matrix of z × z is right-circularly shifted by the number of times of s.
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| CN114362764B (en) * | 2022-01-06 | 2024-05-28 | 清华大学 | Construction method and device of channel coding check matrix in URLLC scene |
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