CN113131933A

CN113131933A - Successive approximation register analog-to-digital converter with correction function and correction method

Info

Publication number: CN113131933A
Application number: CN201911412669.0A
Authority: CN
Inventors: 锺勇辉; 曾启峰
Original assignee: Industrial Technology Research Institute ITRI
Current assignee: Industrial Technology Research Institute ITRI
Priority date: 2019-12-31
Filing date: 2019-12-31
Publication date: 2021-07-16

Abstract

A successive approximation register analog-to-digital converter with correction function and a correction method thereof. The successive approximation register analog-to-digital converter comprises at least one capacitive digital-to-analog converter and a controller. The at least one capacitive digital-to-analog converter includes Nd capacitors corresponding to the Nd bits, wherein Nd is a positive integer. The correction method comprises the following steps: coupling capacitors from the ith bit to the (Nd-1) th bit to a first reference voltage, and generating a first digital code according to the operation of the capacitors from the (i-1) th bit to the 0 th bit, wherein i is an integer smaller than Nd; coupling the capacitors from (i +1) th bit to (Nd-1) th bit to the first reference voltage, coupling the capacitor from the ith bit to a second reference voltage, and generating a second digital code according to the operation of the capacitors from (i-1) th bit to 0 th bit; generating capacitance weight of capacitance of the ith bit according to the first digital code and the second digital code; and correcting the successive approximation register analog-to-digital converter according to the capacitance weight of the capacitance of the ith bit.

Description

Successive approximation register analog-to-digital converter with correction function and correction method

Technical Field

The present disclosure relates to a calibration method for an analog-to-digital converter, and more particularly, to a calibration method for an analog-to-digital converter with successive approximation register and a circuit thereof.

Background

The performance of the adc may affect the accuracy of the measurement, and the adc linearity is required for this application. The foundry provides mismatch parameters for all devices under each process, and capacitive Digital to Analog converters (CDACs) in a Successive Approximation Analog-to-Digital Converter (SAR ADC) affect the overall linearity. How to achieve a certain linearity without excessively amplifying the unit capacitance of the capacitance-to-digital-to-analog converter is one of the problems to be solved in the art.

Disclosure of Invention

According to one embodiment of the present disclosure, a method for calibrating a successive approximation register analog-to-digital converter is provided. The successive approximation register analog-to-digital converter includes at least one capacitive digital-to-analog converter including Nd capacitors corresponding to Nd bits, where Nd is a positive integer, and a controller. The capacitance correction method of the successive approximation buffer analog-to-digital converter comprises the following steps: coupling the capacitors from the z-th bit to the (Nd-1) -th bit to a first reference voltage, generating a first digital code according to the operation of the capacitors from the (z-1) -th bit to the 0-th bit, wherein z is an integer less than Nd; coupling the capacitors from (i +1) th bit to (Nd-1) th bit to the first reference voltage, coupling the capacitor from the i-th bit to a second reference voltage, and generating a second digital code according to the operation of the capacitors from (i-1) th bit to the 0 th bit, wherein i is an integer less than Nd, and z is less than i; generating a capacitance weight of the capacitance of the ith bit from the first digital code and the second digital code; and correcting the successive approximation buffer analog-to-digital converter according to the capacitance weight of the capacitance of the ith bit.

According to an embodiment, a calibration method for a sequential approximation register analog-to-digital converter is provided, wherein the sequential approximation register analog-to-digital converter includes at least one capacitive digital-to-analog converter and a controller. The at least one capacitive digital-to-analog converter includes Nd capacitors corresponding to the Nd bits, wherein Nd is a positive integer. The capacitance correction method of the successive approximation register analog-to-digital converter comprises the following steps: coupling capacitors from the ith bit to the (Nd-1) th bit to a first reference voltage, and generating a first digital code according to the operation of the capacitors from the (i-1) th bit to the 0 th bit, wherein i is an integer smaller than Nd; coupling the capacitors from (i +1) th bit to (Nd-1) th bit to the first reference voltage, coupling the capacitor from the ith bit to a second reference voltage, and generating a second digital code according to the operation of the capacitors from (i-1) th bit to 0 th bit; generating capacitance weight of capacitance of the ith bit according to the first digital code and the second digital code; and correcting the successive approximation register analog-to-digital converter according to the capacitance weight of the capacitance of the ith bit.

According to another embodiment, the present disclosure provides a successive approximation register analog-to-digital converter with calibration function, comprising: at least one capacitive digital-to-analog converter controlled by a plurality of control signals to respectively control the switching operation of Nd switching capacitors of the at least one capacitive digital-to-analog converter, wherein Nd is a positive integer; a comparator coupled to the at least one capacitive DAC for comparing an output of the at least one capacitive DAC with a comparison voltage; and a controller coupled to the comparator and the at least one capacitive digital-to-analog converter for generating a control signal and a digital output signal according to an output of the comparator. The controller obtains a capacitance weight of an ith bit of the at least one capacitive DAC by a result of (Nd +1) operations of the comparator in a calibration mode, wherein i is an integer less than Nd.

According to another embodiment of the present disclosure, there is provided a successive approximation buffer analog-to-digital converter with correction function, including: at least one Nd-bit capacitive digital-to-analog converter having a Nd-bit capacitor, wherein Nd is a positive integer; a controller coupled to the at least one capacitive digital-to-analog converter. The controller is used for executing the following capacitance correction programs: coupling the capacitors from the z-th bit to the (Nd-1) -th bit to a first reference voltage, generating a first digital code according to the operation of the capacitors from the (z-1) -th bit to the 0-th bit, wherein z is an integer less than Nd; coupling the capacitors of the (i +1) th bit to the (Nd-1) th bit to the first reference voltage, coupling the capacitor of the ith bit to a second reference voltage, and generating a second digital code according to the operation of the capacitors of the (i-1) th bit to the 0 th bit, wherein i is an integer less than Nd, and z is less than i; generating a capacitance weight of the capacitance of the ith bit from the first digital code and the second digital code; and correcting the successive approximation buffer analog-to-digital converter according to the capacitance weight of the capacitance of the ith bit.

According to another embodiment, the present disclosure provides a successive approximation register analog-to-digital converter with calibration function, comprising: at least one Nd-bit capacitive digital-to-analog converter having a capacitor with Nd bits; and the controller is coupled with the output of the comparator and the at least one capacitive digital-to-analog converter. The controller performs the following capacitance correction procedure: coupling capacitors from the ith bit to the (Nd-1) th bit to a first reference voltage, and generating a first digital code according to the operation of the capacitors from the (i-1) th bit to the 0 th bit, wherein i is an integer smaller than Nd; coupling the capacitors from (i +1) th bit to (Nd-1) th bit to the first reference voltage, coupling the capacitor from the ith bit to a second reference voltage, and generating a second digital code according to the operation of the capacitors from (i-1) th bit to 0 th bit; generating capacitance weight of capacitance of the ith bit according to the first digital code and the second digital code; and correcting the successive approximation register analog-to-digital converter according to the capacitance weight of the capacitance of the ith bit.

Based on the above, the present disclosure combines the advantages of window switching without adding other circuits on the signal path to affect the corrected comparator offset and flicker noise information. In addition, the capacitance weight deviation accumulated by correction can be improved, so that the integration nonlinearity of the capacitance digital-to-analog converter is further improved.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

Fig. 1 is a block diagram of a successive approximation register analog-to-digital converter according to an embodiment of the disclosure.

Fig. 2 is a schematic diagram illustrating a switching mechanism of a single-ended input successive approximation register analog-to-digital converter according to an embodiment of the disclosure.

Fig. 3 is a block diagram of a successive approximation register analog-to-digital converter according to another embodiment of the disclosure.

Fig. 4 is a schematic diagram illustrating a switching mechanism of a differential-input successive approximation register analog-to-digital converter according to another embodiment of the disclosure.

Fig. 5 is a timing diagram illustrating calibration according to an embodiment of the disclosure.

Fig. 6 is a schematic diagram illustrating correction of flicker noise and offset of a comparator according to an embodiment of the disclosure.

Fig. 7 is a schematic diagram of capacitance calibration according to an embodiment of the disclosure.

Fig. 8 is a schematic diagram of capacitance calibration according to an embodiment of the disclosure.

Fig. 9A is a schematic diagram illustrating a circuit block variation according to an embodiment of the disclosure.

Fig. 9B is a schematic diagram illustrating a circuit block variation according to an embodiment of the disclosure.

Fig. 10A and 10B are schematic diagrams illustrating clock signal reduction according to an embodiment of the disclosure.

FIG. 11 is a flow chart illustrating a calibration method of the successive approximation register ADC according to the present disclosure.

FIG. 12 is a flowchart illustrating a calibration method for a successive approximation register analog-to-digital converter according to an embodiment of the invention.

FIG. 13 is a flowchart illustrating a calibration method for a successive approximation register analog-to-digital converter according to an embodiment of the invention.

Description of the reference numerals

100. 200: successive approximation register analog-to-digital converter

120. 220, and (2) a step of: first capacitive digital-to-analog converter

121. 281: sampling switch

140. 240: comparator with a comparator circuit

160. 260: controller

280: second capacitive digital-to-analog converter

300: successive approximation register analog-to-digital converter

310: first capacitive digital-to-analog converter

320: second capacitive digital-to-analog converter

340: comparator with a comparator circuit

345: clock reduction circuit

360: controller

380: encoder for encoding a video signal

400: correction processor

CP1-CP 11, CN1-CN 11: capacitor with a capacitor element

WP1～WP11、WN1～WN11、SW_TOP1、SW_TOP2: switch with a switch body

Vcm: first reference voltage (common mode voltage)

Vref-second reference Voltage

GND: third reference voltage

CQ: comparison result input terminal

CQ 1: first comparison result

CQ2_ 1-CQ 2_10, CQ2_ k: second comparison result

D: input terminal

GND: ground voltage

RDY: ready signal

RST: reset signal

SCP 1-SCP 10, SCN 1-SCN 10: switched capacitor bank

SDO: digital output signal

SP 1-SP 10: a first control signal

SN 1-SN 10: the second control signal

VDD: supply voltage

VIP: a first analog input signal

VIN: second analog input signal

VP 0: first voltage

VP 1-VPk: second voltage

VN 0: third voltage

VN 1-VNk: a fourth voltage

Vr: comparing reference voltages

Vref: reference voltage

WIN 1-WINk: window area

CLKS: sampling clock signal

CLKC: comparing clock signals

RCLKC: reduced comparison clock

Detailed Description

An embodiment of the present invention provides a calibration technique for a window-switching-architecture-based successive approximation analog-to-digital converter (SAR ADC), which can effectively reduce the device size of a digital-to-analog converter (DAC) that is required to achieve higher linearity due to process limitations, and can further achieve dynamic power consumed by switching the ADC. The present technology combines the advantages of window switching, and can improve the weight deviation accumulated by correction to further improve the Integral Non-Linearity (INL) of the analog-to-digital converter without adding other circuits on the signal path to obtain the information of comparator offset and flicker noise which can affect the correction.

Analog to digital conversion operation

Fig. 1 is a block diagram of a successive approximation register analog-to-digital converter 100 according to an embodiment of the disclosure. A Successive Approximation Register Analog-to-Digital Converter (SAR ADC)100 is configured to convert the first Analog input signal VIP into a Digital output signal SDO, wherein the Digital output signal SDO has N bits calculated from a Most Significant Bit (MSB) to a Least Significant Bit (LSB), where N is a positive integer, and N is 10.

The SAR ADC 100 may include a first capacitive Digital to Analog Converter (CDAC) 120, a comparator 140, and a controller 160. The first capacitive DAC 120 may include a sampling switch 121 and a plurality of switched capacitor banks SCP 1-SCP 10 respectively controlled by first control signals SP 1-SP 10. The first capacitive digital-to-analog converter 120 may receive and sample the first analog input signal VIP through the sampling switch 121 at a time point to generate the first voltage VP 0. The sampling Switch 121 may be, for example, a Bootstrapped Switch (Bootstrapped Switch) controlled by a sampling clock signal CLKS. The first capacitive dac 120 is controlled by a plurality of first control signals SP1 to SP10 to control the switching operations of the switched capacitor banks SCP1 to SCP10, respectively. In detail, the switched capacitor bank SCPi may include a capacitor CPi and a switch WPi, where i is an integer from 1 to L (in this example, L ═ 10). The first terminals of the capacitors CP1-CP 10 are coupled to the non-inverting input terminal of the comparator 140, and the second terminals of the capacitors CP1-CP 10 are respectively switched between the reference voltage Vref and the ground voltage GND through the corresponding switches WP 1-WP 10. The switches WP1 to WP10 are controlled by first control signals SP1 to SP10, respectively. The capacitance values of the capacitors CP1-CP 8 are twice the capacitance values of the capacitors CP2-CP 9, respectively, and the capacitance value of the capacitor CP9 is equal to the capacitance value of the capacitor CP 10. In an embodiment, the coupling may be a direct connection or an indirect connection, for example, the indirect connection is through another device, for example, if device a is coupled to device B, device a and device B may be directly connected, or device a and device B may be connected through device C, for example, device C is directly connected to device B after device a is directly connected to device C.

The comparator 140 receives the first voltage VP0 from the first capacitive digital-to-analog converter 120 and is controlled by the comparison clock signal CLKC to compare the first voltage VP0 with a comparison reference voltage Vr, which may be, for example, a reference voltage Vref, to generate a first comparison result CQ 1. The controller 160 is coupled to the comparator 140 and the first capacitive digital-to-analog converter 120. In particular, the controller 160 may generate first control signals SP1 to SP10 to control the switching operations of the switched capacitor banks SCP1 to SCP10 according to the first comparison result CQ 1.

Further, the controller 160 has a binary window (binary window) function. The controller 160 determines a switching operation of at least one of the switched capacitor banks SCP 1-SCP 10 according to the output of the comparator 140 (i.e., the first comparison result VP0) to approximate the output of the first capacitive dac 120 to the binary window, wherein the binary window is a window of M bits, and M is a positive integer smaller than or equal to N. In detail, in the kth iteration (k is less than or equal to M) of M iterations of the successive approximation register adc 100, the controller 160 may switch the kth switched capacitor bank SCPk of the switched capacitor banks SCP 1-SCP 10 (e.g., from the first state to the second state), so that the first capacitive dac 120 generates the corresponding second voltage VPk. Then, the comparator 140 may compare the second voltage VPk of the kth iteration with the comparison reference voltage Vr to generate a corresponding second comparison result CQ2_ k. The controller 160 may define (or determine) a window area WINk according to the first comparison result CQ1 and the second comparison result CQ2_ k. The controller 160 may determine whether to switch the kth switched capacitor bank SCPk back to the first state or maintain the kth switched capacitor bank SCPk in the second state according to the first comparison result CQ1 and the second comparison result CQ2_ k.

In the kth iteration, if the first comparison result CQ1 indicates that the first voltage VP0 is greater than the comparison reference voltage Vr, and the second comparison result CQ2_ k indicates that the second voltage VPk is also greater than the comparison reference voltage Vr, the controller 160 maintains the kth switching capacitor bank in the second state (i.e., the switched state). Alternatively, in the kth iteration, if the first comparison result CQ1 indicates that the first voltage VP0 is less than the comparison reference voltage Vr, and the second comparison result CQ2_ k indicates that the second voltage VPk is also less than the comparison reference voltage Vr, the controller 160 maintains the kth switched capacitor bank in the second state (i.e., the switched state).

In contrast, in the kth iteration, if the first comparison result CQ1 and the second comparison result CQ2_ k indicate that one of the first voltage VP0 and the second voltage VPk is greater than the comparison reference voltage Vr and the other of the first voltage VP0 and the second voltage VPk is less than the comparison reference voltage Vr, the controller 160 switches the kth switching capacitor bank back to the first state (i.e., the state before switching).

Fig. 2 is a schematic diagram of a switching mechanism when the single-ended input type successive approximation register analog-to-digital converter performs a binary window function according to an embodiment of the disclosure, in which a horizontal axis represents time and a vertical axis represents an output voltage of the first capacitive digital-to-analog converter 120, and M is equal to 4. Based on the binary window being a 4-bit window, four window regions, i.e., WIN 1-WIN 4, are respectively shown in the first iteration (i.e., k is 1) to the fourth iteration (i.e., k is 4) of fig. 2, which are enclosed by dotted lines.

First, in a sample-and-hold (i.e., k is 0) operation, the first capacitive dac 120 receives and samples the first analog input signal VIP through the sampling switch 121 to generate the first voltage VP 0. In one embodiment, the Amplitude (Amplitude) of the first analog input signal VIP is equal to the reference Voltage Vref, and the Common Mode Voltage (Common Mode Voltage) of the first analog input signal VIP is equal to the reference Voltage Vref. The comparator 140 may determine whether the first voltage VP0 is greater than the comparison reference voltage Vr, thereby generating a first comparison result CQ 1. Then, in the first iteration (i.e., k is 1), the controller 160 may generate the first control signal SP1 to control the switching operation of the switched capacitor bank SCP1 according to the first comparison result CQ 1. The following description will be made with respect to the case where the first voltage VP0 is greater than the comparison reference voltage Vr.

In the sample-and-hold operation (i.e., k is 0), if the first voltage VP0 is greater than the comparison reference voltage Vr, the comparator 140 may output a first comparison result CQ1, which is, for example, a logic 1. Therefore, in the first iteration (i.e. k is 1), the controller 160 switches the switch WP1 in the switched capacitor bank SCP1 to pull down the first voltage VP0, so that the first capacitive dac 120 generates the corresponding second voltage VP1, where VP1 is VP 0- (Vref/2)^k) VP 0- (Vref/2) ═ VP 0- (Vr/2). It should be noted that the reference voltage Vref is the comparison reference voltage Vr, and therefore, the following example is described assuming that Vref is equal to Vr. Then, the comparator 140 may compare the second voltage VP1 of the first iteration (i.e., k is 1) with the comparison reference voltage Vr to determine whether the second voltage VP1 is greater than the comparison reference voltage Vr. If the second voltage VP1 is greater than the comparison reference voltage Vr, the comparator 140 will output a second comparison result CQ2_1, which is, for example, a logic 1. It is understood that if the second voltage VP1 is greater than the comparison reference voltage Vr, indicating that the first voltage VP0 is greater than 1.5Vref and is outside the window region WIN1, the controller 160 maintains the switch WP1 in the switched capacitor bank SCP1 in the switched state, where VP1 is VP 0- (Vr/2).In contrast, if the second voltage VP1 is less than the comparison reference voltage Vr, the comparator 140 will output the second comparison result CQ2_1, which is, for example, logic 0. It is understood that if the second voltage VP1 is smaller than the comparison reference voltage Vr, it indicates that the first voltage VP0 is smaller than 1.5Vref and is located in the window region WIN1, so the controller 160 returns the switch WP1 in the switched capacitor bank SCP1 to the state before switching, where VP1 is VP 0.

Then, in the second iteration (i.e. k is 2), the controller 160 switches the switch WP2 in the switched capacitor bank SCP2 to pull down the second voltage VP1, so that the first capacitive dac 120 generates the corresponding second voltage VP2, where VP2 is VP 1- (Vr/2)^k) VP 1- (Vr/4). Then, the comparator 140 may compare the second voltage VP2 of the second iteration (i.e., k is 2) with the comparison reference voltage Vr to determine whether the second voltage VP2 is greater than the comparison reference voltage Vr. If the second voltage VP2 is greater than the comparison reference voltage Vr, the comparator 140 will output a second comparison result CQ2_2, which is, for example, logic 1. It is understood that if the second voltage VP2 is greater than the comparison reference voltage Vr, indicating that the second voltage VP1 is greater than 1.25Vref and is located outside the window region WIN2, the controller 160 maintains the switch WP2 in the switched capacitor bank SCP2 in the switched state, where VP2 is VP 1- (Vr/4). In contrast, if the second voltage VP2 is less than the comparison reference voltage Vr, the comparator 140 will output the second comparison result CQ2_2, which is, for example, logic 0. It is understood that if the second voltage VP2 is smaller than the comparison reference voltage Vr, it indicates that the second voltage VP1 is smaller than 1.25Vref and is located in the window region WIN2, so the controller 160 returns the switch WP2 in the switched capacitor bank SCP2 to the state before switching, where VP2 is VP 1. It should be noted that the second voltage VP1 is determined according to the result of the first iteration (i.e., k is 1) (i.e., the second comparison result CQ2_1), and if the second comparison result CQ2_1 is, for example, logic 1, then VP1 is VP 0- (Vr/2); if the second comparison result CQ2_1 is, for example, logic 0, then VP1 is VP 0.

For the operation of the successive approximation register adc 100 in the third iteration (i.e., k is 3) and the fourth iteration (i.e., k is 4), the operation can be analogized according to the description of the first iteration (i.e., k is 1) and the second iteration (i.e., k is 2), and thus the description thereof is omitted here.

The following description deals with a case where the first voltage VP0 is smaller than the comparison reference voltage Vr. In the sample-and-hold operation (i.e., k is 0), if the first voltage VP0 is less than the comparison reference voltage Vr, the comparator 140 may output a first comparison result CQ1, which is logic 0, for example. Therefore, in the first iteration (i.e. k is 1), the controller 160 will switch the switch WP1 in the switched capacitor bank SCP1 to pull up the first voltage VP0, so that the first capacitive dac 120 generates the corresponding second voltage VP1, where VP1 is VP0+ (Vr/2)^k) VP0+ (Vr/2). Then, the comparator 140 may compare the second voltage VP1 of the first iteration (i.e., k is 1) with the comparison reference voltage Vr to determine whether the second voltage VP1 is greater than the comparison reference voltage Vr. If the second voltage VP1 is greater than the comparison reference voltage Vr, the comparator 140 will output a second comparison result CQ2_1, which is, for example, a logic 1. It is understood that if the second voltage VP1 is greater than the comparison reference voltage Vr, it indicates that the first voltage VP0 is greater than 0.5Vref and is located within the window region WIN1, so the controller 160 returns the switch WP1 in the switched capacitor bank SCP1 to the state before switching, where VP1 is VP 0. In contrast, if the second voltage VP1 is less than the comparison reference voltage Vr, the comparator 140 will output the second comparison result CQ2_1, which is, for example, logic 0. It is understood that if the second voltage VP1 is smaller than the comparison reference voltage Vr, indicating that the first voltage VP0 is smaller than 0.5Vref and is located outside the window region WIN1, the controller 160 maintains the switch WP1 in the switched capacitor bank SCP1 in a switched state, where VP1 is VP0+ (Vr/2).

Then, in the second iteration (i.e. k is 2), the controller 160 switches the switch WP2 in the switched capacitor bank SCP2 to pull up the second voltage VP1, so that the first capacitive dac 120 generates the corresponding second voltage VP2, where VP2 is VP1+ (Vr/2)^k) VP1+ (Vr/4). Then, the comparator 140 may compare the second voltage VP2 of the second iteration (i.e., k is 2) with the comparison reference voltage Vr to determine whether the second voltage VP2 is greater than the comparison reference voltage Vr. If it is secondThe voltage VP2 is greater than the comparison reference voltage Vr, the comparator 140 outputs a second comparison result CQ2_2, which is logic 1, for example. It is understood that if the second voltage VP2 is greater than the comparison reference voltage Vr, it indicates that the second voltage VP1 is greater than 0.75Vref and is located within the window region WIN2, so the controller 160 returns the switch WP2 in the switched capacitor bank SCP2 to the state before switching, where VP2 is VP 1. In contrast, if the second voltage VP2 is less than the comparison reference voltage Vr, the comparator 140 will output the second comparison result CQ2_2, which is, for example, logic 0. It is understood that if the second voltage VP2 is less than the comparison reference voltage Vr, indicating that the second voltage VP1 is less than 0.75Vref and is outside the window region WIN2, the controller 160 maintains the switch WP2 in the switched capacitor bank SCP2 in the switched state, where VP2 is VP1+ (Vr/4). It should be noted that the second voltage VP1 is determined according to the result of the first iteration (i.e., k equals to 1) (i.e., the second comparison result CQ2_1), and if the second comparison result CQ2_1 is, for example, logic 1, then VP1 equals to VP 0; if the second comparison result CQ2_1 is, for example, logic 0, then VP1 ═ VP0+ (Vr/2).

As for the successive approximation register adc 100 operating in the third iteration (i.e., k is 3) and the fourth iteration (i.e., k is 4), analogy can be made to the description of the first iteration (i.e., k is 1) and the second iteration (i.e., k is 2).

Fig. 3 is a block diagram of a successive approximation register analog-to-digital converter 200 according to another embodiment of the disclosure. The successive approximation register adc 200 is a differential input adc. The successive approximation register adc 200 is used for converting a differential pair signal (including a first analog input signal VIP and a second analog input signal VIN) into a digital output signal SDO.

SAR ADC 200 may include a first capacitive digital-to-analog converter 220, a second capacitive digital-to-analog converter 280, a comparator 240, and a controller 260. The first capacitive dac 220, the comparator 240, and the controller 260 are similar to the first capacitive dac 120, the comparator 140, and the controller 160 of fig. 1, respectively, so that the description of fig. 1 can be referred to for analogy, and the description thereof is omitted here.

The second capacitive DAC 280 may include a sampling switch 281 and a plurality of switching capacitors SCN 1-SCN 10. The second capacitive dac 280 may receive and sample the second analog input signal VIN through the sampling switch 281 at a time point to generate the third voltage VN 0. The sampling switch 281 may be, for example, a bootstrap switch controlled by a sampling clock signal CLKS. The second capacitive DAC 280 is controlled by a plurality of second control signals SN 1-SN 10 to control the switching operations of the switched capacitor sets SCN 1-SCN 10, respectively. In detail, the switched capacitor bank SCNi may include a capacitor CNi and a switch WNi, where i is an integer from 1 to 10. The first terminals of the capacitors CN1-CN 10 are coupled to the inverting input terminal of the comparator 240, and the second terminals of the capacitors CN1-CN 10 are switched between the reference voltage Vref and the ground voltage GND through the switches WN 1-WN 10, respectively. The switches WN 1-WN 10 are controlled by second control signals SN 1-SN 10, respectively. The capacitance values of the capacitors CN1 to CN8 are twice the capacitance values of the capacitors CN2 to CN9, respectively, and the capacitance value of the capacitor CN9 is equal to the capacitance value of the capacitor CN 10.

In operation, the comparator 240 receives the first voltage VP0 from the first capacitive dac 220 and the third voltage VN0 from the second capacitive dac 280. The comparator 240 may be controlled by the comparison clock signal CLKC to compare the difference between the first voltage VP0 and the third voltage VN0 with a zero-value crossing point to generate a first comparison result CQ 1. In particular, the controller 260 may generate the first control signals SP 1-SP 10 and the second control signals SN 1-SN 10 according to the first comparison result CQ1 to control the switching operations of the switched capacitor banks SCP 1-SCP 10 and SCN 1-SCN 10, respectively.

Further, the controller 260 has a binary window function. The controller 260 determines the switching operation of at least one of the switched capacitor banks SCP 1-SCP 10 and at least one of the switched capacitor banks SCN 1-SCN 10 according to the output of the comparator 240 (i.e., the first comparison result CQ1) to approximate the output of the first capacitive dac 220 and the output of the second capacitive dac 280 to the binary window, wherein the binary window is a window of M bits, and M is a positive integer less than or equal to N. In detail, in the kth iteration (k is less than or equal to M) of the M iterations of the successive approximation register adc 200, the controller 260 may switch the kth switched capacitor bank SCPk of the switched capacitor banks SCP 1-SCP 10 (e.g., from the first state to the second state), so that the first capacitive dac 220 generates the corresponding second voltage VPk. In addition, the controller 260 may switch (e.g., from the first state to the second state) the kth switched capacitor bank SCNk of the switched capacitor banks SCN 1-SCN 10, so that the second capacitive digital-to-analog converter 280 generates the corresponding fourth voltage VNk. Then, the comparator 240 may compare a difference between the second voltage VPk and the fourth voltage VNk of the kth iteration with a zero crossing point (e.g., 0 v) to generate a corresponding second comparison result CQ2 — k. The controller 260 may define (or determine) a window area WINk according to the first comparison result CQ1 and the second comparison result CQ2_ k. Also, the controller 260 may determine whether to switch the kth switching capacitor bank of the first capacitive dac 220 and the kth switching capacitor bank of the second capacitive dac 280 back to the first state (i.e., the state before switching) or maintain the kth switching capacitor bank in the second state according to the first comparison result CQ1 and the second comparison result CQ2_ k.

Referring to fig. 3 and 4, fig. 4 is a schematic diagram of a switching mechanism when the differential input type successive approximation register analog-to-digital converter performs a binary window function according to an embodiment of the disclosure, in which a horizontal axis represents time, and a vertical axis represents a voltage difference between an output voltage of the first capacitive digital-to-analog converter 220 and an output voltage of the second capacitive digital-to-analog converter 280 (i.e., a differential input voltage of the comparator 240). For convenience of description, M is equal to 4 (i.e. the binary window is a 4-bit window), and the embodiment where M is other positive integer can be analogized in the following description. Based on the binary window being a 4-bit window, four window regions WIN1 through WIN4 surrounded by dotted lines are shown in the first iteration (i.e., k is 1) through the fourth iteration (i.e., k is 4) of fig. 4.

First, in a sample-and-hold operation (i.e., k is 0), the first capacitive dac 220 controls the sampling switch 221 to receive and sample the first analog input signal VIP to generate the first voltage VP0 according to the sampling clock signal CLKS, and the second capacitive dac 280 controls the sampling switch 281 to receive and sample the second analog input signal VIN to generate the third voltage VN0 according to the sampling clock signal CLKS. In one embodiment, the amplitudes (amplitudes) of the first analog input signal VIP and the second analog input signal VIN are equal to the reference Voltage Vref, the Common Mode voltages (Common Mode voltages) of the first analog input signal VIP and the second analog input signal VIN are equal to each other, and the phase difference between the first analog input signal VIP and the second analog input signal VIN is 180 degrees, for example. The comparator 240 is controlled by the comparison clock signal CLKC to determine whether the difference between the first voltage VP0 and the third voltage VN0 is greater than a zero-crossing point, thereby generating a first comparison result CQ 1. Then, in the first iteration (i.e., k is 1), the controller 260 may generate the first control signal SP1 and the second control signal SN1 according to the first comparison result CQ1 to control the switching operation of the switched capacitor banks SCP1 and SCN 1. The difference between the first voltage VP0 and the third voltage VN0 is greater than the zero-crossing point (i.e., VP 0-VN 0> 0).

In the sample-and-hold operation (i.e., k is 0), if the difference between the first voltage VP0 and the third voltage VN0 is greater than the zero-value crossing point, the comparator 240 may output a first comparison result CQ1, which is, for example, logic 1. Therefore, in the first iteration (i.e. k equals 1), the controller 260 switches the switch WP1 in the switched capacitor bank SCP1 to pull down the first voltage VP0, so that the first capacitive digital-to-analog converter 220 generates the corresponding second voltage VP1, where VP1 equals VP 0- (Vref/2). At the same time, the controller 260 switches the switch WN1 in the switching capacitor bank SCN1 to pull up the third voltage VN0, so that the second capacitive digital-to-analog converter 280 generates the corresponding fourth voltage VN1, where VN1 is VN0+ (Vref/2). Then, the comparator 240 may compare the second voltage VP1 and the fourth voltage VN1 in the first iteration (i.e., k is 1) to determine whether the difference between the second voltage VP1 and the fourth voltage VN1 is greater than the zero crossing point. If the difference between the second voltage VP1 and the fourth voltage VN1 is greater than the zero-value crossing point, the comparator 240 will output a second comparison result CQ2_1, which is, for example, a logic 1. It can be understood that, if the difference between the second voltage VP1 and the fourth voltage VN1 is greater than the zero crossing point, which indicates that the difference between the first voltage VP0 and the third voltage VN0 is greater than Vref and is located outside the window area WIN1, the controller 260 maintains the switch WP1 in the switched capacitor bank SCP1 and the switch WN1 in the switched capacitor bank SCN1 in the switched state, and the difference between the second voltage VP1 and the fourth voltage VN1 is VP 1-VN 1 ═ VP 0- (Vref/2) ] - [ VN0+ (Vref/2) ] - (VP 0-VN 0) -Vref. In contrast, if the difference between the second voltage VP1 and the fourth voltage VN1 is less than the zero-value crossing point, the comparator 240 will output a second comparison result CQ2_1, which is, for example, a logic 0. It can be understood that, if the difference between the second voltage VP1 and the fourth voltage VN1 is smaller than the zero crossing point, which indicates that the difference between the first voltage VP0 and the third voltage VN0 is smaller than Vref and is located within the window area WIN1, the controller 260 returns the switch WP1 in the switched capacitor bank SCP1 and the switch WN1 in the switched capacitor bank SCN1 to the pre-switching state, where the difference between the second voltage VP1 and the fourth voltage VN1 is VP 1-VN 1-VP 0-VN 0.

Then, in the second iteration (i.e., k equals 2), the controller 260 switches the switch WP2 in the switched capacitor bank SCP2 to pull down the second voltage VP1, so that the first capacitive dac 220 generates the corresponding second voltage VP2, where VP2 equals VP 1- (Vref/4). At the same time, the controller 260 switches the switch WN2 in the switching capacitor bank SCN2 to pull up the fourth voltage VN1, so that the second capacitive digital-to-analog converter 280 generates the corresponding fourth voltage VN2, where VN2 is VN1+ (Vref/4). Then, the comparator 240 may compare the second voltage VP2 and the fourth voltage VN2 in the second iteration (i.e., k is 2) to determine whether the difference between the second voltage VP2 and the fourth voltage VN2 is greater than the zero crossing point. If the difference between the second voltage VP2 and the fourth voltage VN2 is greater than the zero-value crossing point, the comparator 240 will output a second comparison result CQ2_2, which is, for example, a logic 1. It is understood that if the difference between the second voltage VP2 and the fourth voltage VN2 is greater than the zero crossing point, indicating that the difference between the second voltage VP1 and the fourth voltage VN1 is greater than 0.5Vref and is located outside the window region WIN2, the controller 260 maintains the switch WP2 in the switched capacitor bank SCP2 and the switch WN2 in the switched capacitor bank SCN2 in the switched state, where VP 2-VN 2 ═ VP 1- (Vref/4) ] - [ VN1+ (Vref/4) ] - (VP 1-VN 1) -0.5 Vref. In contrast, if the difference between the second voltage VP2 and the fourth voltage VN2 is less than the zero-value crossing point, the comparator 240 will output a second comparison result CQ2_2, which is, for example, a logic 0. It is understood that if the difference between the second voltage VP2 and the fourth voltage VN2 is less than the zero crossing point, which indicates that the difference between the second voltage VP1 and the fourth voltage VN1 is less than 0.5Vref and is located within the window region WIN2, the controller 260 returns the switch WP2 in the switched capacitor bank SCP2 and the switch WN2 in the switched capacitor bank SCN2 to the pre-switching state, where VP 2-VN 2 are equal to (VP 1-VN 1).

As for the switching operation of the first capacitive dac 220 and the second capacitive dac 280 in the third iteration (i.e., k is 3) and the fourth iteration (i.e., k is 4), the description of the first iteration (i.e., k is 1) and the second iteration (i.e., k is 2) can be analogized, and thus the description thereof is omitted here. It is understood that, in the case that the difference between the first voltage VP0 and the third voltage VN0 is greater than the zero-value crossing point, the controller controls the switching operation of the first capacitive digital-to-analog converter 220 and the second capacitive digital-to-analog converter 280 according to the first comparison result CQ1 and the second comparison result CQ2_ k. On the other hand, when the difference between the first voltage VP0 and the third voltage VN0 is smaller than the zero crossing point, the controller 260 controls the switching operations of the first capacitive dac 220 and the second capacitive dac 280 according to the first comparison result CQ1 and the second comparison result CQ2 — k.

Correction method

In one embodiment, the analog-to-digital converter operates normally in the analog-to-digital conversion mode and performs the calibration in the calibration mode; in one embodiment, the calibration mode may be entered prior to the operation mode; in one embodiment, the calibration mode may be entered after the operation mode has been performed for a period of time; in one embodiment, the calibration mode may be entered (periodically) after each period of operation. The method of capacitance correction of the disclosed embodiment will be described, which is illustrated as an example of the circuit architecture described above with reference to fig. 3. In the structure of this example, the circuit diagram is simplified to focus on the capacitance correction portion. In this example, 11 capacitors are taken as an example, wherein the capacitors CP1-CP5, CN1-CN 5 are to be corrected, and the capacitors CP6-CP11, CN6-CN11 are accurate capacitors; in practice, each capacitor may be a capacitor group, for example, the capacitors CP1 and CN1 may each be composed of 8 smaller capacitors, and the capacitors CP2 and CN2 may each be composed of 4 smaller capacitors, which is not limited by the invention. The capacitors CP6-CP11 and CN 6-CP11 can reach the required accuracy by requiring the process parameters during the manufacturing process. In one embodiment, the more inaccurate capacitance is calibrated with the accurate capacitance as a reference without adding additional circuitry. In this embodiment, the accurate capacitors CP6-CP11 and CN6-CN11 are used to correct the less accurate capacitors CP1-CP5 and CN1-CN 5.

Fig. 5 is a timing diagram illustrating calibration according to an embodiment of the disclosure. In the embodiment of the present disclosure, the calibration process may be performed multiple times, and the calibration value obtained by calibrating the flicker noise and the offset of the comparator (offset) and the average value of the capacitors C1-C5 multiple times may be more accurate. As shown in fig. 5, the calibration sequence of each calibration cycle is to calibrate the flicker noise and the offset of the comparator (i.e., O & F in the figure, which are collectively referred to as noise), and then calibrate the capacitors CP5 to CP1 and CN5 to CN 1. In one embodiment, the flicker noise and the offset of the comparator are corrected during the first period of the sampling clock CLKS, and the capacitors CP 5-CP 1 and CN 5-CN 1 are corrected during the second period to the sixth period of the sampling clock CLKS, respectively. The offset (offset) and flicker (flicker) noise information Do [ x ] of the comparator is obtained in the first period of the sampling clock CLKS, and then the capacitors CP 5-CP 1, CN 5-CN 1 are sequentially corrected in each sampling clock CLKS to obtain the correction information Do [ x +1] -Do [ x +5], wherein Do [ x ] is the binary digital code output by the analog-digital converter, wherein x represents each correction period, x is a positive integer, and y represents the repetition number of a correction procedure, which is a natural number. Similarly, the above-mentioned calibration procedure is repeated, and for example, offset and flicker (flicker) noise of the comparator and the calibration information Do [ x +6] to Do [ x +11] of the capacitors CP5 to CP1 and CN5 to CN1 can be obtained in the seventh to twelfth periods of the sampling clock CLKS. By analogy, the whole calibration procedure will be averaged over several cycles.

Next, a method of correction will be described with reference to a circuit configuration, in which flicker noise and offset of the comparator and the correction of the capacitances CP5 and CN5 and the capacitances CP1 and CN1 are described, and the methods of correction of the capacitances CP4, CN5 to CP2 and CN2 are similar to the methods of correction of the capacitances CP5 and C1 and the capacitances CN5 and CN 1.

Next, fig. 6 to 8 are used to illustrate an exemplary capacitance calibration method of the present disclosure. Fig. 6 is a schematic diagram illustrating correction of flicker noise and offset of the comparator 340 according to an embodiment of the disclosure.

As shown in fig. 6, the successive approximation register analog-to-digital converter 300 may include a first capacitive digital-to-analog converter 310, a second capacitive digital-to-analog converter 320, a comparator 340, and a controller 360. The outputs VCP and VCN of the first capacitive digital-to-analog converter 310 and the second capacitive digital-to-analog converter 320 are respectively connected to two input terminals of the comparator 340. The capacitors CP1 and CN1 correspond to the MSB, and are sequentially followed by capacitors CP2 and CN2, and capacitors CP3 and cn4. The comparison result output by the comparator 340 is transmitted to the controller 360. In one embodiment, the controller 360 performs the analog-to-digital conversion control described in fig. 1-4, and/or performs the capacitance correction and the quantization of the flicker noise and the offset of the comparator 360.

Correction of flicker noise and offset of the comparator 340 is first performed. As shown in FIG. 6, when the sampling clock CLKS is at a high level, the switches SW of the first terminals (or top plates) of the capacitors CP1-CP 11 and CN1-CN 11 are turned on_TOP1And SW_TOP2Then, the first ends of the capacitors CP1-CP 11 of the first capacitive DAC 310 are connected via the switch SW_TOP1Connected to the first input voltage VIP, the first terminals of the capacitors CN1-CN 11 of the second capacitive DAC 320 are connected via the switch SW_TOP2And is connected to a second input voltage VIN. In one embodiment, the voltages of the first input voltage VIP and the second input voltage VIN are arbitrary voltage values determined based on the input common mode voltage Vicm of the comparator; in an embodiment, when the voltage values of the first input voltage VIP and the second input voltage VIP are the input common mode voltage Vicm, the second terminals (or called bottom boards) of the capacitors CP1-CP 11 and CN1-CN 11 are switched to the first reference voltage Vcm by the switches WP 1-WP 11 and WN 1-WN 11, respectively, so as to reset all the capacitors CP1-CP 11 and CN1-CN 11. In an embodiment, the first input voltage VIP and the second input voltage VIN are Vcm, and the second terminals of the capacitors CP1-CP 11 and CN1-CN 11 are switched to the input common mode voltage Vicm or other voltages by the switches WP 1-WP 11 and the switches WN 1-WN 11, thereby resetting all the capacitors CP1-CP 11 and CN1-CN 11. In one embodiment, the input common mode voltage Vicm of the operating mode is (VIP + VIN)/2. In an embodiment, the first reference voltage Vcm may be an input common mode voltage Vicm. In one embodiment, when the capacitors CP1-CP 11 and CN1-CN 11 are reset, the voltages of the first and second terminals of the capacitors CP1-CP 11 and CN1-CN 11 may be the same.

When the sampling clock CLKS is turned to the low level, the controller 360 turns off the switches SWTOP1 and SWTOP2, so that the first ends of the capacitors CP1 to CP11 and the capacitors CN1 to CN11 are disconnected from the first input voltage VIP and the second input voltage VIP, and all the second ends of the capacitors CP1 to CP5 and the capacitors CN1 to CN5 (i.e., the capacitors to be corrected) are maintained at the first reference voltage Vcm by the switches WP1 to WP5 and the switches WN1 to WN5, respectively. When the sampling clock CLKS is changed from high to low, a calibration procedure is performed to start the calibration of offset and flicker noise at a period T0 of the comparison clock CLKC. In one embodiment, the switches WP 1-WP 5 of the capacitors CP1-CP5 and the switches WN 1-WN 5 of the capacitors CN1-CN 5 do not switch in the period T1-T5 of the comparison clock CLKC. After 5 cycles (T1-T5) of the comparison clock CLKC, the accurate capacitance CP6-CP11 of the first capacitive digital-to-analog converter 310 and the accurate capacitance CN6-CN11 (zADC 5 shown in fig. 6) of the second capacitive digital-to-analog converter 320 perform the digital-to-analog conversion operation of the SAR ADC 300. When the SAR ADC 300 performs the digital-to-analog conversion operation, the second terminals of the capacitors CP6-CP11 and CN6-CN11 are not required to be connected to the first reference voltage Vcm, and can be connected to the second reference voltage Vref or the third reference voltage GND according to the operation of the SAR ADC 300. In one embodiment, zADC is a corresponding analog-to-digital converter consisting of accurate capacitance and/or corrected capacitance. The result of each bit of zADC 5 determines the corresponding capacitance switching, i.e. the binary search method of SAR ADC 300 is performed. If the result of the comparator 340 is 1 for the bit, the VCP side capacitance of the bit is switched from Vcm to GND by the second terminal switch, and the VCN side capacitance is switched from the first reference voltage Vcm to the second reference voltage Vref by the second terminal switch. On the other hand, if the result of the comparator 340 is 0 at the bit, it means that the capacitance on the VCP side of the bit is switched from the first reference voltage Vcm to the second reference voltage Vref by the switch on the second end, and the capacitance on the VCN side is switched from the first reference voltage Vcm to the third reference voltage GND by the switch on the second end. Thus, after the switch is completed, the next bit is compared until all bit transitions are completed. The resulting binary seven digital bit output of zADC 5 is the flicker noise and offset information of comparator 340. In the embodiment, all the information about the flicker noise and the offset of the comparator 340 are accurately measured by the capacitors, but the invention is not limited thereto, and in an embodiment, the information about the flicker noise and the offset of the comparator 340 may be partially accurately measured by the capacitors, for example, the information about the flicker noise and the offset of the comparator 340 measured by the ADC corresponding to the capacitors including the LSB of the lower bits may be measured by CP7 to CP11 and CN7 to CN11, for example, the measurement method is similar to the above, for example, when the sampling clock CLKS is changed from the high level to the low level, the calibration procedure is performed, and the calibration of the skew and the flicker noise is started in the period T0 of the comparison clock CLKC. In the period from T1 to T5 of the comparison clock CLKC, the switches WP1 to WP6 of the capacitors CP1 to CP6 and the switches WN1 to WN6 of the capacitors CN1 to CN6 do not perform switching operation. After 6 cycles of the comparison clock CLKC (T1-T6, T6 is not shown, T6 is the next cycle of T5), the accurate capacitors CP7-CP11 of the first capacitive dac 310 and the accurate capacitors CN7-CN11 of the second capacitive dac 320 perform the digital-to-analog conversion operation of the SAR ADC 300. When the SAR ADC 300 performs the digital-to-analog conversion operation, the second terminals of the capacitors CP7-CP11 and CN7-CN11 are not required to be connected to the first reference voltage Vcm, and can be connected to the second reference voltage Vref or the third reference voltage GND according to the operation of the SAR ADC 300. The resulting binary six digital bits output is the flicker noise and offset information of comparator 340. The high and low voltages in this embodiment are merely examples, and in another embodiment, the capacitor may be reset when the sampling clock CLKS is at the low voltage level, and the calibration may be performed when the sampling clock CLKS is at the high voltage level, which is not limited by the disclosure.

After the flicker noise and the offset of the comparator 340 are quantized, the calibration procedure of the capacitors CP1-CP5 and CN1-CN 5 of the first capacitive dac 310 and the second capacitive dac 320 is performed. In one embodiment, the capacitance calibration starts from the minimum bit of the capacitor to be calibrated, in this embodiment, from the capacitor CP5 and the capacitor CN5, i.e., the capacitors CP6-CP11 and the capacitors CN6-CN11 with the closest bit sequence to the exact one.

Fig. 7 is a schematic diagram of capacitance calibration according to an embodiment of the disclosure. The following examples are provided to illustrate the correction of the capacitances CP5 and CN 5. As shown in FIG. 7, when the sampling clock CLKS is at a high level, the first terminals of the capacitors CP1-CP 11 of the first capacitive DAC 310 are all connected via the switch SW_TOP1The first terminals of the capacitors CN1-CN 11 of the second capacitive DAC 320 are connected to the first input voltage VIP via the switch SW_TOP2And to a second input voltage VIN. In an embodiment, the voltages of the first input voltage VIP and the second input voltage VIN are the input common mode voltage Vicm, and the second ends of the capacitors CP1-CP 11 and CN1-CN 11 are switched to Vcm by the switches WP 1-WP 11 and WN 1-WN 11, so as to reset all the capacitors CP1-CP 11 and CN1-CN 11.

After the sampling clock CLKS is turned to a low level, in the period T0-T4 of the comparison clock CLKC, the second ends of the capacitors CP1-CP4 and CN1-CN4 of the corresponding first capacitor type DAC 310 and the second capacitor type DAC 320 are respectively maintained at the first reference voltage Vcm through the switches WP 1-WP 4 and WN 1-WN 4, and the SW ends corresponding to the first capacitor type DAC 310 and the second capacitor type DAC 320 are respectively maintained at the first reference voltage Vcm_TOP1And SW_TOP2Then both are turned off. During the period T0-T4 of the comparison clock CLKC, the comparator 340 can perform comparison, but does not switch the voltage at the second end of the capacitor. In one embodiment, the switch control signals generated by the controller 360 may be blocked by a logic gate circuit inside the controller 360, so that the switches WP1 to WP4 of the capacitors CP1 to CP4 and the switches WN1 to WN4 of the capacitors CN1 to CN4 are not switched during the periods T1 to T4.

Next, in a period T5 of the comparison clock CLKC, the correction of the capacitances CP5 and CN5 is started. At this time, the second terminal of the capacitor CP5 of the first capacitive digital-to-analog converter 310 is connected to the second reference voltage Vref (reference voltage) through the switch WP5, and the second terminal of the capacitor CN5 of the second capacitive digital-to-analog converter 320 is connected to the third reference voltage GND (ground voltage) through the switch WN 5. Next, after T5 cycles of the comparison clock CLKC, analog-to-digital conversion of the zADC 5 corresponding to the capacitors CP6 to CP11 and CN6 to CN11 is performed.

As described above, the capacitors CP6-CP11 of the first capacitive dac 310 and the capacitors CN6-CN11 of the second capacitive dac 320 can be accurately manufactured by requiring process parameters, so that the analog-to-digital conversion performed by the zADC 5 corresponding to CP6-CP11 and CN6-CN11 can obtain accurate results to correct the capacitors CP5 and CN 5.

In one embodiment, the analog-to-digital conversion result of zADC 5 includes the flicker noise and the offset of comparator 340, and in one embodiment, the flicker noise and the offset of comparator 340 (e.g., the flicker noise and the offset of comparator 340) are subtracted from the analog-to-digital conversion result of zADC 5 to obtain the capacitance weight W of capacitor CP5 and/or capacitor CN5_C5. In thatIn one embodiment, such as the differential circuit shown in FIG. 7, the capacitance weight W_C5The weights of the bits corresponding to capacitor CP5 and capacitor CN 5. In another embodiment, such as the single-ended circuit shown in FIG. 1, the capacitance weight W_C5The weight of the bit corresponding to the capacitance CP 5. In another embodiment, the capacitance weight W_C5Is the weight of the bit corresponding to capacitance CN 5. Capacitance weight W_C1～W_C4And the capacitance weight W_C5Similarly, and so on.

Fig. 8 is a schematic diagram of capacitance calibration according to an embodiment of the disclosure. The following examples are provided to illustrate the correction of the capacitances CP1 and CN 1. As shown in FIG. 8, when the sampling clock CLKS is at a high level, the first terminals of the capacitors CP1-CP 11 of the first capacitive DAC 310 are all connected via the switch SW_TOP1The first terminals of the capacitors CN1-CN 11 of the second capacitive DAC 320 are connected to the first input voltage VIP via the switch SW_TOP2Is connected to the second input voltage VIN. In an embodiment, the voltages of the first input voltage VIP and the second input voltage VIN are the input common mode voltage Vicm, and the second ends of the capacitors CP1-CP 11 and CN1-CN 11 are switched to Vcm by the switches WP 1-WP 11 and the switches WN 1-WN 11, respectively, so as to reset all the capacitors CP1-CP 11 and CN1-CN 11.

After the sampling clock CLKS is turned to a low level, SW corresponding to the first capacitive DAC 310 and the second capacitive DAC 320 respectively_TOP1And SW_TOP2Are all disconnected. During period T0 of the comparison clock CLKC, the comparator 340 may perform the comparison, but does not switch the voltage at the second terminal of the capacitor. In a period T1 of the comparison clock CLKC, the capacitances CP1 and CN1 are corrected. At this time, the second terminal of the capacitor CP1 of the first capacitive digital-to-analog converter 310 is connected to the second reference voltage Vref (reference voltage) through the switch WP1, and the second terminal of the capacitor CN1 of the second capacitive digital-to-analog converter 320 is connected to the third reference voltage GND (ground voltage) through the switch WN 1. Then, after comparing the period T1 of the clock CLKC, zADC1 (including corrected SAR ADCs corresponding to the capacitors CP2-CP5, CN2-CN 5 and the accurate capacitors CP6-CP11, CN 6-CP 11) is used to perform analog-to-digital conversion, and the ratio of each bit of zADC1 is usedAs a result, the voltage of the second terminal of the capacitor corresponding to each bit is switched. The binary eleven-bit digital output obtained by this is the weight of the capacitors CP1 and CN1, in one embodiment, the analog-to-digital result obtained by zADC1 includes the flicker noise and the offset of the comparator 340, and the weight of the capacitors CP1 and CN1 obtained by analog-to-digital conversion by zADC1 minus the flicker noise and the offset of the comparator 340 (e.g., the obtained flicker noise and the offset of the comparator 340) can obtain the capacitance weight W of the capacitors CP1 and CN1_C1。

As described above, the capacitances CP6 to CP11 of the first capacitive digital-to-analog converter 310 and the capacitances CN6 to CN11 of the second capacitive digital-to-analog converter 320 are accurate capacitances, the capacitances CP2 to CP5 and CN2 to CN5 are also corrected, and the capacitances CP1 and CN1 can be corrected when the general successive approximation analog-to-digital conversion operation is performed by the capacitances CP2 to CP11 and CN2 to CN11 of the zADC 1. The weights of the capacitors CP1 and CN1 obtained in this way include the flicker noise and the offset of the comparator 340, so that the flicker noise and the offset of the comparator 340 can be subtracted to obtain the weights W of the capacitors CP1 and CN1_C1。

In a similar manner as described above, the capacitance weights of the capacitors CP2-CP4 of the first capacitive dac 310 and the capacitors CN2-CN4 of the second capacitive dac 320 may be corrected. Taking the correction capacitors CP4 and CN4 as examples, when the sampling clock CLKS is at a high level, the capacitors CP1-CP 11 and CN1-CN 11 are reset, and SW is turned off during the period from T0-T3 of the comparison clock CLKC when the sampling clock CLKS is at a low level_TOP1And SW_TOP2During the period T4 of the comparison clock CLKC, the second terminals of the capacitors CP1-CP 3 and CN1-CN 3 are maintained at the first reference voltage Vcm, while the second terminal of the capacitor CP4 of the first capacitive digital-to-analog converter 310 is switched to the second reference voltage Vref by the switch WP4, and the second terminal of the capacitor CN4 of the second capacitive digital-to-analog converter 320 is switched to the third reference voltage GND by the switch WN 4. In a period T4 of the comparison clock CLKC, the correction of the capacitors CP4 and CN4 is started, and the general continuous approximate simulation is carried out on the zADC4 (including the corrected capacitors CP5 and CN5 and SAR ADCs corresponding to the accurate capacitors CP6-CP11 and CN6-CN 11) to carry outThe flicker noise and the offset of the comparator 340 are subtracted by digital conversion to obtain the capacitance weight W of the capacitors CP4 and CN4_C4. The correction methods of the capacitors CP2 and CN2, CP3 and CN3 are similar to the above, and can be analogized.

In one embodiment, the timing of the calibration procedure of the SAR ADC 300 in the calibration mode is the same as or similar to the timing of the operation mode, so that the calibration of the capacitance and the measurement of the flicker noise and the offset of the comparator 340 can be achieved without adding or changing circuits.

In one embodiment, after obtaining the capacitance weight of each capacitor, the digital code output by the first capacitive digital-to-analog converter 310 and/or the second capacitive digital-to-analog converter 320 may be modified by the capacitance weight to obtain an accurate digital code. In one embodiment, due to the inaccurate capacitance, the digital code output by the first capacitive digital-to-analog converter 310 and/or the second capacitive digital-to-analog converter 320 may deviate from the correct digital code, and after the capacitance weight of each capacitance is obtained, the deviation may be corrected by using a redundancy circuit (not shown) to obtain the correct digital code.

The capacitance weights W of the capacitors CP1-CP5 and the capacitors CN1-CN 5 are described below by another embodiment_C1～W_C5The calculation method of (1). As described above, in the exemplary circuit configurations shown in fig. 6-8, a calibration process is performed to perform the flicker noise and the comparator offset and the calibration of the capacitors CP 5-CP 1 and the capacitors CN 5-CN 1 in six cycles through 6 cycles of the sampling clock CLKS. In one implementation, the calibration procedure may be performed multiple times, averaging the respective calibration values obtained each time to obtain a more accurate capacitive calibration value. Referring to FIG. 5, after the above procedure is performed y times, the average weight W of the capacitors CP 5-CP 1, CN 5-CN 1_C1avg～W_C5avgCan be calculated by the formula (1), wherein W_C1avgIs the average weight of the capacitances CP1, CN1, D0[ x +6y]Is the offset of the flicker noise obtained at the (y +1) th time from the comparator 340. Where x represents each correction period and x is a positive integer. y represents the number of repetitions of a correction procedure, which is a natural number. Tong (Chinese character of 'tong')The influence of white noise on the capacitance correction weight can be eliminated by executing the correction procedure for multiple times. D0[ (x +1) +6y]～D0[(x+5)+6y]And D0[ x +6y ]]The binary digital code obtained by the sar adc 300 operation for each calibration period.

Fig. 9A is a schematic diagram illustrating a circuit block variation according to an embodiment of the disclosure. As shown in fig. 9A, the successive approximation buffer analog-to-digital converter 300 may further include: an encoder 380 coupled to the controller 360 for receiving an output of the controller 360; and a correction processor 400 coupled to the encoder 380. In the calibration mode, taking the calibration capacitors CP5 and CN5 as an example, the SAR ADC 300 outputs the binary digital result to the encoder 380, the encoder 380 encodes the binary digital result to generate a decimal encoding result, and then transmits the encoding result to the calibration processor 400. The correction processor 400 may average the correction procedure performed y times with a loop. In one embodiment, the operations of equation (1) may be performed by the correction processor 400. In one embodiment, the averaged capacitance weight W_C1avg～W_C5avgThe digital code output by the first capacitive dac 310 and/or the second capacitive dac 320 is modified to perform an analog-to-digital conversion in the operation mode, so as to obtain an accurate analog-to-digital conversion result. In one embodiment, the effect of white noise can be eliminated by averaging the data obtained from multiple corrections. In one embodiment, the one-time capacitance weight W may not be averaged_C1～W_C5The digital code output by the first capacitive digital-to-analog converter 310 and/or the second capacitive digital-to-analog converter 320 is corrected.

Fig. 9B is a schematic diagram illustrating a circuit block variation according to an embodiment of the disclosure. As shown in fig. 9B, successive approximation register analog-to-digital converter 300 may further include a clock reduction circuit 345 operable to generate a reduced comparison clock RCLKC. In one embodiment, clock reduction circuit 345 may reduce comparison clock CLKC to generate a reduced comparison clock RCLKC. In one embodiment, the correction time may be further reduced using a reduced compare clock RCLKC.

In the above embodiment, after measuring the noise, the correction is started from the capacitor to be corrected closest to the LSB until the capacitor to be corrected closest to the MSB. For example, the capacitances CP1 to CP5 and CN1 to CN5 are corrected from the capacitances CP5 and CN5 to the capacitances CP1 and CN1 in this order. In this order, the first capacitors CP5 and CN5 to be corrected are the capacitors to be corrected closest to the LSB, and the capacitors CP6 to CP11 and CN6 to CN11 which are the basis of correction are all accurate capacitors. After the capacitors CP5 and CN5 are corrected, the capacitors CP 5-CP 11 and CN 5-CN 11 are used for correcting the next capacitors CP4 and CN4 to be corrected, which are closest to the LSB. And so on, the capacitor to be corrected closest to the LSB is corrected each time, and the capacitor used for correcting the capacitor to be corrected includes the capacitor corrected previously and the accurate capacitor.

However, the present disclosure is not limited thereto. In another embodiment, after measuring the noise, the correction is started from the capacitor to be corrected closest to the MSB until the capacitor to be corrected closest to the LSB. However, the correction from the MSB side to the LSB side is explained below.

First, the capacitances CP1 and CN1 are corrected using the capacitances CP2-CP11 and CN2 to CN11 (for example, zADC1 in fig. 8). At this time, the capacitances CP6-CP11, CN6-CN11 in zADC1 are accurate, but the capacitances CP2-CP5, CN2-CN 5 have not been corrected. Therefore, when the weight W of the capacitances CP1, CN1 is obtained in the above manner_C1’When W is_C1’Errors in the capacitors CP2-CP5, CN2-CN 5 may be included. Similarly, the weight W of the capacitors CP2 and CN2_C2’May include errors of the capacitors CP3-CP5, CN 3-CN 5, W of the capacitor CP3_C3’The error of the capacitors CP4-CP5, CN 4-CN 5, and the weight W of the capacitors CP4, CN4 may be included_C4’Errors in the capacitors CP5, CN5 may be included. When the correction of the capacitances CP5, CN5 is performed, the correct capacitance weight W of the capacitances CP5, CN5 can be obtained in the same or similar manner as in fig. 7_C5。

Next, the calibration processor 400 shown in FIG. 9A or 9B is calibrated by the capacitance weights W of the capacitors CP5 and CN5_C5Calculating the capacitance weights of the correct capacitances CP4, CN4Heavy W_C4The weight W of the capacitors CP5, CN5 and CP4, CN4_C5、W_C4Calculate the capacitance weight W of the correct capacitance CP3, CN3_C3. And so on, finally, the weight W is used_C5～W_C2Calculate the capacitance weight W of the correct capacitance CP1, CN1_C1. In one embodiment, the average capacitance weight of the capacitors CP1-CP5 and CN1-CN 5 can be calculated by the formula (1).

In one embodiment, if the exact capacitance of the successive approximation register adc is bits 0 to a, in one embodiment, the correction order may be that the ith bit is repeatedly incremented from bit i + a +1 to generate the capacitance weight of each capacitor until the capacitance weight of bit (Nd-1) is generated. In one embodiment, the correction order may be that the ith bit is decreased from the i-Nd-1 bit repeatedly and downwards, and the capacitance weight of each capacitor is generated until the capacitance weight of the a +1 th bit is generated.

In one embodiment, the calibration timing is based on the clock sequence of the ADC in the operation mode, so that the calibration of the capacitance and the measurement of the flicker noise and the offset of the comparator 340 can be achieved without adding or changing the hardware structure of the circuit. In another embodiment, the correction time can be further reduced, for example, as shown in fig. 7, when the capacitors CP5 and CN5 are corrected, the capacitors are not switched during the T0 to T4 cycles of the comparison clock CLKC using the timing of the original operation mode, so that the T0 to T4 cycles can be reduced to reduce the correction time.

Fig. 10A and 10B are schematic diagrams illustrating clock signal reduction according to an embodiment of the disclosure. As shown in the upper half of FIG. 10A, in the operation mode, the period T0 is the period of the sample-and-hold operation, and the periods T1T 5 are the corresponding analog-to-digital conversion periods of the capacitors CP1 CP5, CN1 CN 5. In the calibration mode, after the flicker noise and the offset of the comparator 340 are measured, the capacitors CP1 to CP5 and CN1 to CN5 are not switched during the period T1 to T5 until the analog-to-digital conversion of the zADC 5 is performed after the next period of the comparison clock CLKC. In one embodiment, as shown in the lower half of FIG. 10A, the T1-T5 cycles are omitted in the calibration mode; that is, the next cycle of the period T0 is to perform zADC 5 operation with the timing shown by the waveform of the reduced comparison clock RCLKC.

In one embodiment, as shown in the top half of FIG. 10B, in the operation mode, the period T0 is the period of the sample-and-hold operation, and the periods T1T 5 are the corresponding analog-to-digital conversion periods of the capacitors CP1 CP5, CN1 CN 5; in the calibration mode, after the flicker noise and the offset of the comparator 340 are measured, the capacitors CP1 to CP4 and CN1 to CP4 are not switched during the period T1 to T4 until the voltages at the second ends of the capacitors CP5 and CN5 are switched during the period T5, and then the analog-to-digital conversion of the zADC 5 is performed. In one embodiment, as shown in the lower half of FIG. 10B, the T0-T4 cycles are omitted in the calibration mode; that is, after the sampling clock CLKS is turned low, the first period of the comparison clock CLKC may be the period T5, and the calibration procedure of the capacitors CP5, CN5 is directly performed, the timing of which is shown by the waveform of the reduced comparison clock RCLKC. In this embodiment, the waiting periods T0-T4 may not be needed to make the calibration time faster. Similarly, when the capacitances CP4 and CN4 are corrected, the waiting period from T0 to T3 can be omitted. In the correction of the capacitances CP3 and CN3, the waiting period from the period T0 to T2 can be omitted. In the correction of the capacitances CP2 and CN2, the waiting period from the period T0 to T1 can be omitted. In the correction of the capacitances CP1 and CN1, the waiting period of the period T0 may be omitted. Thus, the overall correction time can be further shortened.

In one embodiment, the capacitive DAC has Nd bits, where Nd is a positive integer, and reducing the comparison clock RCLKC omits a latency period from the Nd-1 st bit capacitor to the (i +1) th bit in the operation mode timing (comparison clock CLKC) when correcting the capacitance of the ith bit, where i is an integer less than Nd. In one embodiment, as shown in fig. 9B, a clock reduction circuit 345 may be added to the successive approximation register adc 300 for clock reduction, i.e., reducing the comparison clock CLKC in the operating mode to the reduced comparison clock RCLKC, and omitting the waiting period.

In addition, in the calibration procedure, when the capacitance to be calibrated is calibrated, the voltage of the second terminal of the capacitance to be calibrated of the first capacitive digital-to-analog converter 310 is switched to be connected to the second reference voltage Vref, and the second terminal of the capacitance to be calibrated of the second capacitive digital-to-analog converter 320 is switched to be connected to the third reference voltage GND, but the disclosure is not limited thereto. For example, the voltage of the second terminal of the capacitor to be calibrated of the first capacitive digital-to-analog converter 310 is switched to be connected to the third reference voltage GND, and the voltage of the second terminal of the capacitor to be calibrated of the second capacitive digital-to-analog converter 320 is switched to be connected to the second reference voltage Vref. In another embodiment, the voltage of the second terminal of the capacitor to be calibrated of the first capacitive dac 310 may be connected to the second reference voltage Vref or the third reference voltage GND, i.e., may be switched to a different reference voltage, or may be switched to another voltage in another embodiment. Similarly, the voltage of the second terminal of the capacitor to be calibrated of the second capacitive dac 320 may be connected to the second reference voltage Vref or the third reference voltage GND, i.e., may be switched to a different reference voltage, or may be switched to another voltage in another embodiment. In another embodiment, the second reference voltage may be one of Vref or GND, the third reference voltage may be the other of Vref or GND, and for example, the second reference voltage may be GND and the third reference voltage may be Vref.

In the above embodiments, the capacitance correction procedure is described by using a differential circuit (e.g., the circuit shown in fig. 3), but a single ended circuit (e.g., the circuit shown in fig. 1) may be applied to the capacitance correction method of the present disclosure. That is, the input terminal of the comparator 340 is connected to only one capacitive digital-to-analog converter, and the capacitance calibration method of the present disclosure can also be applied. The capacitance calibration method in the single-ended circuit architecture is the same as or similar to the calibration method in the differential circuit, and the description thereof is omitted here.

FIG. 11 is a flow chart illustrating a calibration method of the successive approximation register ADC according to the present disclosure. In one embodiment, the successive approximation register analog-to-digital converter comprises at least one Nd-bit capacitive digital-to-analog converter having capacitances corresponding to the 0 th bit to the Nd-1 th bit, wherein the capacitances from the 0 th bit to the i-1 th bit are, for example, the exact capacitances described above (e.g., capacitances CP 11-CP 6, CN 11-CN 6), and the capacitances from the i th bit to the Nd-1 th bit are, for example, capacitances to be corrected (e.g., capacitances CP 5-CP 1, CN 5-CN 1 described above), i being an integer less than Nd. In one embodiment, the digital code converted by the Nd-bit capacitive digital-to-analog converter is converted by the SAR ADC to obtain a digital code of Nd +1 bits, for example, the SAR ADC can compare the difference between VIP and VIN without capacitance operation to obtain a digital code of more than 1 bit. As shown in FIG. 11, in step S100, the capacitors from the i-th bit to the (Nd-1) -th bit are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors from the (i-1) -th bit to the 0-th bit, wherein i is an integer smaller than Nd. In an embodiment, step S100 may obtain noise, which may include flicker noise and offset of the comparator.

In one embodiment, a first terminal of a capacitor from the Nd-1 th bit to the 0 th bit is connected to an input voltage (e.g., VIP, VIN), and a second terminal of the capacitor is connected to a first reference voltage (e.g., Vcm); disconnecting the input voltage from a first terminal of a capacitance of the Nd-1 th bit to the 0 th bit; and generating a first digital code by using a successive approximation register analog-to-digital converter corresponding to the capacitance from the (i-1) th bit to the 0 th bit to measure the noise.

Next, step S102 is performed. In step S102, the capacitors from (i +1) th bit to (Nd-1) th bit are coupled to a first reference voltage, the capacitor from the i-th bit is coupled to a second reference voltage, and a second digital code is generated according to the operation of the capacitors from the (i-1) th bit to the 0 th bit. In one embodiment, step S102 corrects the capacitance of the ith bit based on the operation of the (i-1) th bit to 0 th bit capacitances, generates the second digital code from the comparator, and subtracts the second digital code from the first digital code to generate the weight of the ith bit capacitance.

In one embodiment, the ith bit capacitor is coupled to a second reference voltage or a third reference voltage, the (Nd-1) th to (i +1) th bit capacitors are coupled to the first reference voltage, a second digital code is generated by successive approximation register analog-to-digital converters corresponding to the (i-1) th to 0 th bit capacitors, and weights of the ith bit capacitor are generated by the second digital code and the first digital code.

In one embodiment, the first terminal of the capacitor (e.g., CP1-CP 11, CN1-CN 11) from the (Nd-1) th bit to the 0 th bit is connected to the input voltage (e.g., VIP, VIN), and the second terminal of the capacitor is connected to the first reference voltage (e.g., Vcm); disconnecting the input voltage from a first terminal of a capacitance of the Nd-1 th bit to the 0 th bit; coupling a second terminal of the capacitance of the ith bit to a second reference voltage (e.g., Vref) or a third reference voltage (e.g., GND); and generating a second digital code by using a successive approximation register analog-to-digital converter corresponding to the capacitance from the (i-1) th bit to the 0 th bit, and generating the capacitance weight of the capacitance of the ith bit by using the second digital code and the first digital code.

In step S106, it is determined whether i has been equal to Nd-1, i.e., the above-described operation has been performed up to the Nd-1 th bit. If the Nd-1 th bit has not been reached, i.e., the determination result is NO, step S108 is performed. Step S108 increments i, i +1, and then continues to step S102 until i is Nd-1. In addition, in step S106, it is determined whether i is equal to Nd-1, i.e. the capacitance weight to the (Nd-1) th bit capacitance is generated, and the successive approximation register ADC is calibrated. In one embodiment, a step may be added between steps S102 and S106 to generate a capacitance weight of the capacitance of the ith bit according to the first digital code and the second digital code; in one embodiment, after determining that i is Nd — 1 in step S106, the capacitance weight of the capacitor of each bit may be generated according to each second digital code obtained in each execution of step S102. After the capacitance weights of each bit or all bits are obtained, the corresponding successive approximation register analog-to-digital converter can be corrected according to the obtained capacitance weights.

FIG. 12 is a flowchart illustrating a calibration method for a successive approximation register analog-to-digital converter according to an embodiment of the invention. In this embodiment, not all the exact capacitances are required to obtain flicker noise and comparator offset. The successive approximation register analog-to-digital converter includes at least one capacitive digital-to-analog converter including Nd capacitors corresponding to the Nd bits, Nd being a positive integer, and a controller. As shown in fig. 12. In step S1202, a first digital code is generated by coupling a capacitor from a z-th bit to a (Nd-1) -th bit to a first reference voltage according to an operation of the capacitor from the (z-1) -th bit to a 0-th bit, wherein z is an integer less than Nd. In one embodiment, for example, the 0 th to 5 th capacitive digital-to-analog converters have accurate capacitance, Nd is 11, and z is 5, the capacitance of the 5 th to 10 th bits is coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitance of the 4 th to 0 th bits, wherein the first digital code includes flicker noise and offset of a comparator. In step S1204, coupling capacitors from (i +1) th bit to (Nd-1) th bit to a first reference voltage, coupling capacitors from the i-th bit to a second reference voltage, and generating a second digital code according to operations of the capacitors from the (i-1) th bit to the 0 th bit, wherein i is an integer less than Nd, and z is less than i. In this embodiment, i is, for example, 6, the capacitors from the 7 th bit to the 10 th bit are coupled to a first reference voltage, the capacitor from the 6 th bit is coupled to a second reference voltage, and the second digital code is generated according to the operation of the capacitors from the 5 th bit to the 0 th bit. In step S1206, a capacitance weight of the capacitance of the ith bit is generated according to the first digital code and the second digital code. In this embodiment, the capacitance weight of the capacitor of the 6 th bit is generated according to the first digital code generated by the operation of the capacitors of the 4 th bit to the 0 th bit and the second digital code generated by the capacitors of the 5 th bit to the 0 th bit, and the successive approximation register analog-to-digital converter is calibrated according to the capacitance weight of the capacitor of the i th bit in step S1208.

FIG. 13 is a flowchart illustrating a calibration method for a successive approximation register analog-to-digital converter according to an embodiment of the invention. The successive approximation register analog-to-digital converter includes at least one capacitive digital-to-analog converter including Nd capacitors corresponding to the Nd bits, Nd being a positive integer, and a controller. As shown in fig. 13. In step S1302, coupling the capacitors from the i-th bit to the (Nd-1) -th bit to a first reference voltage, and generating a first digital code according to the operation of the capacitors from the (i-1) -th bit to the 0-th bit, wherein i is an integer smaller than Nd. In one embodiment, where Nd is 11, i is 6, the capacitors from bit 6 to bit 10 are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors from bit 5 to bit 0, where the first digital code includes flicker noise and offset of the comparator. In step S1304, the capacitors from (i +1) th bit to (Nd-1) th bit are coupled to a first reference voltage, the capacitor from the i-th bit is coupled to a second reference voltage, and a second digital code is generated according to the operation of the capacitors from (i-1) th bit to 0 th bit. In this embodiment, i is, for example, 6, the capacitors from the 7 th bit to the 10 th bit are coupled to a first reference voltage, the capacitor from the 6 th bit is coupled to a second reference voltage, and the second digital code is generated according to the operation of the capacitors from the 5 th bit to the 0 th bit. In step S1306, a capacitance weight of the capacitance of the ith bit is generated according to the first digital code and the second digital code. In this embodiment, the capacitance weight of the capacitor of the 6 th bit is generated according to the first digital code generated by the operation of the capacitors of the 5 th bit to the 0 th bit and the second digital code generated by the capacitors of the 5 th bit to the 0 th bit, and the successive approximation register adc is calibrated according to the capacitance weight of the capacitor of the i th bit in step S1308.

As can be seen from the above description, the capacitance calibration method according to the embodiment of the disclosure can be performed under the original operation architecture of the successive approximation register analog-to-digital converter without adding an additional circuit architecture. For example, the comparison clock CLKC driving the successive approximation register ADC for analog-to-digital conversion is used as a correction clock, during the period from T1 to T5 of the comparison clock CLKC, the capacitors CP1 to CP5 and CN1 to CN5 can be driven for analog-to-digital conversion in the operation mode, and in the correction mode, the corrected capacitor can be connected to the second reference voltage Vref or the third reference voltage GND, while the other capacitors which are not corrected are connected to the first reference voltage Vcm. Therefore, in one embodiment, the control sequence (control sequence) in the controller 360 can be changed to adapt to the operation mode and the calibration mode without significantly changing the overall circuit structure and without increasing the area of the capacitor, and the overall circuit size will not be increased.

In summary, based on the above description of the present disclosure, if the number of the capacitors to be corrected is NumC, the time required for correction can be reduced to (NumC +1) cycle, which is about 2 times faster than the conventional 2NumC cycle required for correction. If the calibration process is repeated continuously for several times, the white noise generated by the circuit can be eliminated, so that the calibration is more accurate. The embodiment of the disclosure can obtain the flicker noise and the comparator offset information without adding a circuit on a signal path.

In addition, the embodiment of the disclosure can improve the capacitance weight deviation accumulated by correction to further improve the integration nonlinearity of the capacitive digital-to-analog converter.

According to one embodiment of the present disclosure, a method for calibrating a successive approximation register analog-to-digital converter is provided. The successive approximation register analog-to-digital converter includes at least one capacitive digital-to-analog converter including Nd capacitors corresponding to Nd bits, where Nd is a positive integer, and a controller. The capacitance correction method of the successive approximation buffer analog-to-digital converter comprises the following steps: coupling the capacitors from the z-th bit to the (Nd-1) -th bit to a first reference voltage, generating a first digital code according to the operation of the capacitors from the (z-1) -th bit to the 0-th bit, wherein z is an integer less than Nd; coupling the capacitors of the (i +1) th bit to the (Nd-1) th bit to the first reference voltage, coupling the capacitor of the ith bit to a second reference voltage, and generating a second digital code according to the operation of the capacitors of the (i-1) th bit to the 0 th bit, wherein i is an integer less than Nd, and z is less than i; generating a capacitance weight of the capacitance of the ith bit from the first digital code and the second digital code; and correcting the successive approximation buffer analog-to-digital converter according to the capacitance weight of the capacitance of the ith bit.

In the capacitance correction method of the successive approximation register analog-to-digital converter, wherein the coupling of the capacitance from the z-th bit to the (Nd-1) -th bit to the first reference voltage, the generating of the first digital code according to the operation of the capacitance from the (z-1) -th bit to the 0-th bit comprises: coupling a first terminal of the capacitor of the (Nd-1) th bit to the 0 th bit to an input voltage, a second terminal of the capacitor of the (Nd-1) th bit to the 0 th bit to the first reference voltage; disconnecting the input voltage from the first terminal of the capacitance of the (Nd-1) th bit to the 0 th bit; and generating the first digital code by using the successive approximation register analog-to-digital converter corresponding to the (z-1) th bit to the 0 th bit of capacitance.

According to an embodiment of the present disclosure, a calibration method for successive approximation register analog-to-digital converter is provided, wherein the successive approximation register analog-to-digital converter includes at least one capacitive digital-to-analog converter including Nd capacitors corresponding to Nd bits, wherein Nd is a positive integer, and a controller. The capacitance correction method of the successive approximation buffer analog-to-digital converter comprises the following steps: coupling the capacitors from the (i) -th bit to the (Nd-1) -th bit to a first reference voltage, and generating a first digital code according to the operation of the capacitors from the (i-1) -th bit to the 0-th bit, wherein i is an integer less than Nd; coupling the capacitors from the (i +1) th bit to the (Nd-1) th bit to the first reference voltage, coupling the capacitor from the i th bit to a second reference voltage, and generating a second digital code according to the operation of the capacitors from the (i-1) th bit to the 0 th bit; generating a capacitance weight of the capacitance of the ith bit from the first digital code and the second digital code; and correcting the successive approximation buffer analog-to-digital converter according to the capacitance weight of the capacitance of the ith bit.

The capacitance correction method for the successive approximation buffer analog-to-digital converter further comprises performing the capacitance correction method a plurality of times to obtain an average value of the capacitance weight of the ith bit.

In the capacitance correction method of the successive approximation register analog-to-digital converter, wherein the coupling of the capacitance of the ith bit to the (Nd-1) th bit to the first reference voltage, the generating of the first digital code according to the operation of the capacitance of the (i-1) th bit to the 0 th bit comprises: coupling a first terminal of the capacitor of the (Nd-1) th bit to the 0 th bit to an input voltage, a second terminal of the capacitor of the (Nd-1) th bit to the 0 th bit to the first reference voltage; disconnecting the input voltage from the first terminal of the capacitance of the (Nd-1) th bit to the 0 th bit; and generating the first digital code by using the successive approximation register analog-to-digital converter corresponding to the capacitance from the (i-1) th bit to the 0 th bit.

In the capacitance correction method of the successive approximation register analog-to-digital converter, coupling the capacitance of the (i +1) th bit to the (Nd-1) th bit to the first reference voltage, coupling the capacitance of the ith bit to the second reference voltage, and generating the second digital code according to the operation of the capacitance of the (i-1) th bit to the 0 th bit comprises: coupling a second terminal of the capacitors of the (i +1) th bit to the (Nd-1) th bit to the first reference voltage, and coupling a second terminal of a capacitor of the ith bit to the second reference voltage; and generating the second digital code by using the successive approximation register analog-to-digital converter corresponding to the capacitors from the (i-1) th bit to the 0 th bit.

In the capacitance calibration method of the successive approximation register analog-to-digital converter, wherein the at least one capacitive digital-to-analog converter includes a first capacitive digital-to-analog converter and a second capacitive digital-to-analog converter, and wherein coupling the second end of the capacitance of the ith bit to the second reference voltage comprises: a second end of the capacitance of the ith bit of the first capacitive digital-to-analog converter is coupled to the second reference voltage; and a second end of the capacitance of the ith bit of the second capacitive digital-to-analog converter is coupled to a third reference voltage.

In the capacitance correction method of the successive approximation register analog-to-digital converter, the successive approximation register analog-to-digital converter further includes a comparator, and the input voltage is determined by an input common mode voltage of the comparator.

The capacitance correction method for the successive approximation register analog-to-digital converter further comprises the following steps: after the second digital code is generated, coupling the capacitors from the (i +2) th bit to the (Nd-1) th bit to the first reference voltage, coupling the capacitors from the (i +1) th bit to the second reference voltage, and generating a third digital code according to the operation of the capacitors from the i th bit to the 0 th bit; and generating a capacitance weight of the capacitance of the (i +1) th bit from the first digital code and the third digital code. In one embodiment, i is repeatedly incremented up to generate the capacitance weight for each capacitor until the capacitance weight for the (Nd-1) th bit is generated.

The capacitance correction method for the successive approximation register analog-to-digital converter further comprises the following steps: after generating the second digital code, coupling the capacitors from the i-th bit to the (Nd-1) -th bit to the first reference voltage, coupling the capacitors from the (i-1) -th bit to the second reference voltage, and generating a third digital code according to the operation of the capacitors from the (i-2) -th bit to the 0-th bit; and generating a capacitance weight of the capacitance of the i-1 th bit according to the first digital code and the third digital code. In one embodiment, i is repeatedly decremented down to generate the capacitance weight for each capacitor until the capacitance weight for the (a +1) th bit is generated.

The capacitance correction method for the successive approximation register analog-to-digital converter further comprises the following steps: obtaining a capacitance weight of the capacitance of a j-th bit from capacitance weights of the capacitances of (j-1) -th to i-th bits, wherein Nd > j > i.

In the capacitance calibration method of the successive approximation register analog-to-digital converter, a calibration timing of the capacitance calibration method is the same as an operation mode timing of the successive approximation register analog-to-digital converter.

In the capacitance correction method of the successive approximation register analog-to-digital converter, when the capacitance of the ith bit is corrected, the correction timing of the capacitance correction method omits the waiting period from the (Nd-1) th bit capacitance to the (i +1) th bit in the operation mode timing.

In the capacitance correction method of the successive approximation buffer analog-to-digital converter, the successive approximation buffer analog-to-digital converter further comprises a comparator, and the first digital code comprises flicker noise and offset information of the comparator.

In the capacitance correction method of successive approximation buffer analog-to-digital converter, generating a capacitance weight of the capacitance of the ith bit according to the first digital code and the second digital code comprises subtracting the first digital code and the second digital code to generate a capacitance weight of the capacitance of the ith bit.

According to another embodiment of the present disclosure, there is provided a successive approximation buffer analog-to-digital converter with correction function, including: at least one capacitive digital-to-analog converter controlled by a plurality of control signals to respectively control the switching operation of Nd switching capacitors of the at least one capacitive digital-to-analog converter, wherein Nd is a positive integer; a comparator coupled to the at least one capacitive digital-to-analog converter for comparing an output of the at least one capacitive digital-to-analog converter with a comparison voltage; and a controller coupled to the comparator and the at least one capacitive digital-to-analog converter for generating the control signal and the digital output signal according to an output of the comparator. The controller obtains a capacitance weight of an ith bit of the at least one capacitive digital-to-analog converter by a result of (Nd +1) operations of the comparator when in a calibration mode, wherein i is an integer less than Nd.

In the aforementioned successive approximation register analog-to-digital converter with calibration function, when the controller is in an operation mode, the output of the at least one capacitive digital-to-analog converter is approximated to the window of Nd bits according to the output of the comparator, and an operation of approximating the output of the at least one capacitive digital-to-analog converter to the window of Nd bits is performed according to a result of (Nd +1) times of comparison operations of the comparator.

According to another embodiment of the present disclosure, there is provided a successive approximation buffer analog-to-digital converter with correction function, including: at least one Nd-bit capacitive digital-to-analog converter having a Nd-bit capacitor, wherein Nd is a positive integer; a controller coupled to the at least one capacitive digital-to-analog converter. The controller is used for executing the following capacitance correction programs: coupling the capacitors from the (i) -th bit to the (Nd-1) -th bit to a first reference voltage, and generating a first digital code according to the operation of the capacitors from the (i-1) -th bit to the 0-th bit, wherein i is an integer less than Nd; coupling the capacitors from the (i +1) th bit to the (Nd-1) th bit to the first reference voltage, coupling the capacitor from the i th bit to a second reference voltage, and generating a second digital code according to the operation of the capacitors from the (i-1) th bit to the 0 th bit; generating a capacitance weight of the capacitance of the ith bit from the first digital code and the second digital code; and correcting the successive approximation buffer analog-to-digital converter according to the capacitance weight of the capacitance of the ith bit.

In the successive approximation buffer analog-to-digital converter with correction function described above, the controller performs the correction procedure a plurality of times to obtain an average value of the capacitance weight of the ith bit.

In the successive approximation register analog-to-digital converter with correction function, the controller is configured to generate the first digital code according to the operation of the capacitors from the (i-1) th bit to the 0 th bit by performing the operation of coupling the capacitors from the i-1) th bit to the (Nd-1) th bit to the first reference voltage, and comprises: coupling a first terminal of the capacitor of the (Nd-1) th bit to the 0 th bit to an input voltage, a second terminal of the capacitor of the (Nd-1) th bit to the 0 th bit to the first reference voltage; disconnecting the input voltage from the first terminal of the capacitance of the (Nd-1) th bit to the 0 th bit; and generating the first digital code by using the successive approximation register analog-to-digital converter corresponding to the capacitance from the (i-1) th bit to the 0 th bit.

In the successive approximation register analog-to-digital converter with correction function, wherein the controller is configured to couple the capacitors from the (i +1) th bit to the (Nd-1) th bit to the first reference voltage, couple the capacitors from the i th bit to the second reference voltage, and generate the second digital code according to the operations of the capacitors from the (i-1) th bit to the 0 th bit, the controller is configured to: coupling a second terminal of the capacitors of the (i +1) th bit to the (Nd-1) th bit to the first reference voltage, and coupling a second terminal of a capacitor of the ith bit to the second reference voltage; and generating the second digital code by using the successive approximation register analog-to-digital converter corresponding to the capacitors from the (i-1) th bit to the 0 th bit.

In the aforementioned successive approximation register analog-to-digital converter with calibration function, wherein the at least one capacitive digital-to-analog converter comprises a first capacitive digital-to-analog converter and a second capacitive digital-to-analog converter, and wherein the controller performs the coupling of the second end of the capacitance of the ith bit to the second reference voltage comprises: a second end of the capacitance of the ith bit of the first capacitive digital-to-analog converter is coupled to the second reference voltage; and a second end of the capacitance of the ith bit of the second capacitive digital-to-analog converter is coupled to a third reference voltage.

In the successive approximation register analog-to-digital converter with the correction function, the successive approximation register analog-to-digital converter further includes a comparator, and the input voltage is determined by an input common mode voltage of the comparator.

In the aforementioned successive approximation register analog-to-digital converter with calibration function, the controller is further configured to: after the second digital code is generated, coupling the capacitors from the (i +2) th bit to the (Nd-1) th bit to the first reference voltage, coupling the capacitors from the (i +1) th bit to the second reference voltage, and generating a third digital code according to the operation of the capacitors from the i th bit to the 0 th bit; and generating a capacitance weight of the capacitance of the (i +1) th bit from the first digital code and the third digital code.

In the above successive approximation buffer analog-to-digital converter with correction function, the controller further performs: after generating the second digital code, coupling the capacitors from the i-th bit to the (Nd-1) -th bit to the first reference voltage, coupling the capacitors from the (i-1) -th bit to the second reference voltage, and generating a third digital code according to the operation of the capacitors from the (i-2) -th bit to the 0-th bit; and generating a capacitance weight of the capacitance of the i-1 th bit according to the first digital code and the third digital code.

In the successive approximation register analog-to-digital converter with correction function, the controller is further configured to: obtaining a capacitance weight of the capacitance of a j-th bit from capacitance weights of the capacitances of (j-1) -th to i-th bits, wherein Nd > j > i.

In the successive approximation register analog-to-digital converter with the calibration function, the calibration timing of the capacitance calibration procedure of the controller is the same as the operation mode timing of the successive approximation register analog-to-digital converter.

In the successive approximation buffer analog-to-digital converter with correction function, the method further includes: a clock reduction circuit coupled between the controller and the comparator for omitting the waiting period from the (Nd-1) th bit capacitor to the (i +1) th bit capacitor in the operation mode timing from the correction timing of the capacitance correction procedure when correcting the capacitance of the ith bit.

In the successive approximation buffer analog-to-digital converter with the correction function, the successive approximation buffer analog-to-digital converter further includes a comparator, and the first digital code includes information of flicker noise and an offset of the comparator.

In the successive approximation buffer analog-to-digital converter with correction function, the controller subtracts the first digital code and the second digital code to generate the capacitance weight of the capacitance of the ith bit.

Although the present disclosure has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure should be determined by that defined in the appended claims.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for calibrating a successive approximation register analog-to-digital converter (SAR ADC), wherein the SAR ADC comprises at least one capacitive DAC comprising Nd capacitors corresponding to Nd bits, wherein Nd is a positive integer, and a controller, the method comprising:

coupling the capacitors from the z-th bit to the (Nd-1) -th bit to a first reference voltage, generating a first digital code according to the operation of the capacitors from the (z-1) -th bit to the 0-th bit, wherein z is an integer less than Nd;

coupling the capacitors from (i +1) th bit to (Nd-1) th bit to the first reference voltage, coupling the capacitor from the i-th bit to a second reference voltage, and generating a second digital code according to the operation of the capacitors from (i-1) th bit to the 0 th bit, wherein i is an integer less than Nd, and z is less than i;

generating a capacitance weight of the capacitance of the ith bit from the first digital code and the second digital code; and

correcting the successive approximation buffer analog-to-digital converter according to the capacitance weight of the capacitance of the ith bit.

2. The successive approximation buffer analog-to-digital converter correction method of claim 1, further comprising performing said capacitance correction method a plurality of times to obtain an average of said capacitance weights for said ith bit.

3. The method of claim 1, wherein the coupling of the capacitance of the z-th bit to the (Nd-1) -th bit to the first reference voltage, the generating of the first digital code according to the operation of the capacitance of the (z-1) -th bit to the 0-th bit comprises:

coupling a first terminal of the capacitor of the (Nd-1) th bit to the 0 th bit to an input voltage, a second terminal of the capacitor of the (Nd-1) th bit to the 0 th bit to the first reference voltage;

disconnecting the input voltage from the first terminal of the capacitance of the (Nd-1) th bit to the 0 th bit; and

and generating the first digital code by using the successive approximation register analog-to-digital converter corresponding to the capacitance from the (z-1) th bit to the 0 th bit.

4. The method of claim 3, wherein coupling the capacitors from the (i +1) th bit to the (Nd-1) th bit to the first reference voltage, coupling the capacitors from the i th bit to the second reference voltage, and generating the second digital code according to the operation of the capacitors from the (i-1) th bit to the 0 th bit comprises:

coupling a second terminal of the capacitors of the (i +1) th bit to the (Nd-1) th bit to the first reference voltage, and coupling a second terminal of a capacitor of the ith bit to the second reference voltage; and

generating the second digital code by using the successive approximation register analog-to-digital converter corresponding to the capacitors from the (i-1) th bit to the 0 th bit.

5. The method of claim 4, wherein the at least one capacitive digital-to-analog converter comprises a first capacitive digital-to-analog converter and a second capacitive digital-to-analog converter, and wherein coupling the second end of the capacitance of the ith bit to the second reference voltage comprises:

a second end of the capacitance of the ith bit of the first capacitive digital-to-analog converter is coupled to the second reference voltage; and

a second end of the capacitor of the ith bit of the second capacitive digital-to-analog converter is coupled to a third reference voltage.

6. The method of calibrating a successive approximation buffer analog-to-digital converter according to claim 5, wherein said successive approximation buffer analog-to-digital converter further comprises a comparator, said input voltage being determined by an input common mode voltage of said comparator.

7. The successive approximation buffer analog-to-digital converter correction method of claim 1, further comprising:

after the second digital code is generated, coupling the capacitors from the (i +2) th bit to the (Nd-1) th bit to the first reference voltage, coupling the capacitors from the (i +1) th bit to the second reference voltage, and generating a third digital code according to the operation of the capacitors from the i th bit to the 0 th bit; and

generating a capacitance weight of the capacitance of the (i +1) th bit from the first digital code and the third digital code.

8. The successive approximation buffer analog-to-digital converter correction method of claim 1, further comprising:

after generating the second digital code, coupling the capacitors from the i-th bit to the (Nd-1) -th bit to the first reference voltage, coupling the capacitors from the (i-1) -th bit to the second reference voltage, and generating a third digital code according to the operation of the capacitors from the (i-2) -th bit to the 0-th bit; and

generating a capacitance weight of the capacitance of the (i-1) th bit from the first digital code and the third digital code.

9. The successive approximation buffer analog-to-digital converter correction method of claim 1, further comprising:

obtaining a capacitance weight of the capacitance of a j-th bit from capacitance weights of the capacitances of (j-1) -th to i-th bits, wherein Nd > j > i.

10. The successive approximation buffer analog-to-digital converter correction method of claim 1, wherein the correction timing of the capacitance correction method is the same as the operation mode timing of the successive approximation buffer analog-to-digital converter.

11. The method of claim 1, wherein the capacitance calibration method is performed in a calibration sequence that omits a waiting period from a (Nd-1) th bit capacitance to a (i +1) th bit in an operation mode sequence when calibrating the capacitance of the ith bit.

12. The successive approximation buffer analog-to-digital converter correction method of claim 1, wherein said successive approximation buffer analog-to-digital converter further comprises a comparator, said first digital code comprising information of flicker noise and offset of said comparator.

13. The method of claim 1, wherein generating a capacitance weight of the capacitance of the ith bit from the first digital code and the second digital code comprises subtracting the first digital code and the second digital code to generate a capacitance weight of the capacitance of the ith bit.

14. A method for calibrating a successive approximation register analog-to-digital converter (SAR ADC), wherein the SAR ADC comprises at least one capacitive DAC comprising Nd capacitors corresponding to Nd bits, wherein Nd is a positive integer, and a controller, the method comprising:

coupling the capacitors from the (i) -th bit to the (Nd-1) -th bit to a first reference voltage, and generating a first digital code according to the operation of the capacitors from the (i-1) -th bit to the 0-th bit, wherein i is an integer less than Nd;

coupling the capacitors from the (i +1) th bit to the (Nd-1) th bit to the first reference voltage, coupling the capacitor from the i th bit to a second reference voltage, and generating a second digital code according to the operation of the capacitors from the (i-1) th bit to the 0 th bit;

15. The successive approximation buffer analog-to-digital converter correction method of claim 14, further comprising performing said capacitance correction method a plurality of times to obtain an average of said capacitance weights for said ith bit.

16. The method of claim 14, wherein the coupling the capacitance of the i-th bit to the (Nd-1) -th bit to the first reference voltage, the generating the first digital code according to the operation of the capacitance of the (i-1) -th bit to the 0-th bit comprises:

and generating the first digital code by using the successive approximation register analog-to-digital converter corresponding to the capacitance from the (i-1) th bit to the 0 th bit.

17. The method of claim 16, wherein coupling the capacitors from the (i +1) th bit to the (Nd-1) th bit to the first reference voltage, coupling the capacitors from the i th bit to the second reference voltage, and generating the second digital code according to the operation of the capacitors from the (i-1) th bit to the 0 th bit comprises:

18. The method of claim 17, wherein the at least one capacitive digital-to-analog converter comprises a first capacitive digital-to-analog converter and a second capacitive digital-to-analog converter, and wherein coupling the second end of the capacitance of the ith bit to the second reference voltage comprises:

19. The successive approximation buffer analog-to-digital converter correction method of claim 14, further comprising:

20. The successive approximation buffer analog-to-digital converter correction method of claim 14, wherein the correction timing of the capacitance correction method is the same as the operation mode timing of the successive approximation buffer analog-to-digital converter.

21. The method of claim 14, wherein the capacitance calibration method is performed in a calibration sequence that omits a waiting period from a (Nd-1) th bit capacitance to a (i +1) th bit in an operation mode sequence when calibrating the capacitance of the ith bit.

22. The successive approximation buffer analog-to-digital converter correction method of claim 14, wherein said successive approximation buffer analog-to-digital converter further comprises a comparator, said first digital code comprising information of flicker noise and offset of said comparator.

23. The method of calibrating a successive approximation buffer analog-to-digital converter of claim 14, wherein generating a capacitance weight of the capacitance of the ith bit from the first digital code and the second digital code comprises subtracting the first digital code and the second digital code to generate a capacitance weight of the capacitance of the ith bit.

24. A successive approximation buffer analog-to-digital converter with correction function, comprising:

at least one capacitive digital-to-analog converter controlled by a plurality of control signals to respectively control the switching operation of Nd switching capacitors of the at least one capacitive digital-to-analog converter, wherein Nd is a positive integer;

a comparator coupled to the at least one capacitive digital-to-analog converter for comparing an output of the at least one capacitive digital-to-analog converter with a comparison voltage; and

a controller coupled to the comparator and the at least one capacitive DAC for generating the control signal and the digital output signal according to an output of the comparator,

wherein the controller obtains a capacitance weight of an i-th bit of the at least one capacitive DAC by a result of (Nd +1) operations of the comparator in a calibration mode, wherein i is an integer less than Nd.

25. The successive approximation register analog-to-digital converter with correction function of claim 24, wherein the controller approximates the output of the at least one capacitive digital-to-analog converter to a window of Nd bits according to the output of the comparator when in an operation mode, the approximating the output of the at least one capacitive digital-to-analog converter to the window of Nd bits being accomplished by a result of (Nd +1) comparison operations of the comparator.

26. A successive approximation buffer analog-to-digital converter with correction function, comprising:

at least one Nd-bit capacitive digital-to-analog converter having a Nd-bit capacitor, wherein Nd is a positive integer;

a controller coupled to the at least one capacitive digital-to-analog converter,

wherein the controller is configured to perform the following capacitance correction procedure:

27. The successive approximation register analog-to-digital converter with correction function according to claim 26, wherein said controller, in performing the operation of coupling the capacitance of the z-th bit to the (Nd-1) -th bit to the first reference voltage, generating the first digital code according to the operation of the capacitance of the (z-1) -th bit to the 0-th bit, comprises:

28. The successive approximation register analog-to-digital converter with correction function of claim 27, wherein the controller is performing the operations of coupling the capacitor from the (i +1) th bit to the (Nd-1) th bit to the first reference voltage, coupling the capacitor from the i th bit to the second reference voltage, and generating the second digital code according to the operation of the capacitor from the (i-1) th bit to the 0 th bit comprises:

29. The successive approximation register analog-to-digital converter with correction function of claim 28, wherein the at least one capacitive digital-to-analog converter comprises a first capacitive digital-to-analog converter and a second capacitive digital-to-analog converter, wherein the controller performs the coupling of the second reference voltage to the second end of the capacitance of the ith bit comprises:

30. The successive approximation buffer analog-to-digital converter with correction function of claim 26, the controller further to perform:

31. The successive approximation buffer analog-to-digital converter with correction function of claim 26, wherein the correction timing of the capacitance correction procedure of the controller is the same as the operation mode timing of the successive approximation buffer analog-to-digital converter.

32. The successive approximation buffer analog-to-digital converter with correction function of claim 26, further comprising:

a frequency reduction circuit coupled between the controller and the comparator for omitting the waiting period from the (Nd-1) th bit capacitor to the (i +1) th bit capacitor in the operation mode timing from the correction timing of the capacitance correction procedure when correcting the capacitance of the ith bit.

33. The successive approximation buffer analog-to-digital converter with correction function of claim 26, further comprising a comparator, the first digital code comprising information of flicker noise and offset of the comparator.

34. The successive approximation buffer analog-to-digital converter with correction function of claim 26, wherein the controller subtracts the first digital code from the second digital code to generate a capacitance weight of the capacitance of the ith bit.

35. A successive approximation buffer analog-to-digital converter with correction function, comprising: