CN113131924A - Hardware pulse detection locking circuit - Google Patents
Hardware pulse detection locking circuit Download PDFInfo
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- CN113131924A CN113131924A CN202110549682.1A CN202110549682A CN113131924A CN 113131924 A CN113131924 A CN 113131924A CN 202110549682 A CN202110549682 A CN 202110549682A CN 113131924 A CN113131924 A CN 113131924A
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- 238000001514 detection method Methods 0.000 title claims abstract description 17
- 230000010354 integration Effects 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims 1
- 230000002159 abnormal effect Effects 0.000 abstract description 7
- 230000007547 defect Effects 0.000 abstract description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017545—Coupling arrangements; Impedance matching circuits
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Abstract
The invention relates to a pulse detection locking circuit, in particular to a hardware pulse detection locking circuit, which comprises a pulse integrating circuit, a pulse detecting circuit and a pulse locking circuit, wherein the pulse integrating circuit is used for integrating an input signal; the level comparison locking circuit is used for locking the output at a high level when the pulse integrating circuit outputs the high level; the pulse signal locking circuit is used for enabling the input signal to be connected with the control signal of the bridge type switch circuit when the level comparison locking circuit outputs a low level; when the level comparison locking circuit outputs a high level, isolating the input signal; the technical scheme provided by the invention can effectively overcome the defect that the main control tube in the bridge type switching circuit can not be closed in time when the pulse input signal is abnormal in the prior art.
Description
Technical Field
The invention relates to a pulse detection locking circuit, in particular to a hardware pulse detection locking circuit.
Background
The single-phase bridge and the three-phase bridge are common controllable bridge type level conversion circuits, wherein the direct connection of an upper bridge arm and a lower bridge arm is a common and serious circuit fault, so that an effective protection driving circuit is very necessary. If the upper bridge arm and the lower bridge arm are directly connected, the bridge arms are short-circuited, a large short-circuit current is formed, and the switch tube is damaged or even explodes.
In a bridge type level conversion circuit, not only the upper and lower arms are easily led straight, but also the pulse input signal is easily abnormal. When the pulse input signal is abnormal, the effective control of the main control tube in the bridge type switch circuit can not be realized, and then the bridge type switch circuit can not work normally. However, in the conventional bridge type level conversion circuit, when a pulse input signal is abnormal, a main control tube in the bridge type switching circuit cannot be closed in time, so that effective protection on a main circuit is formed.
Disclosure of Invention
Technical problem to be solved
Aiming at the defects in the prior art, the invention provides a hardware pulse detection locking circuit which can effectively overcome the defect that a main control tube in a bridge type switching circuit cannot be closed in time when a pulse input signal is abnormal in the prior art.
(II) technical scheme
In order to achieve the purpose, the invention is realized by the following technical scheme:
a hardware pulse detection lockout circuit comprising:
a pulse integration circuit for integrating an input signal;
the level comparison locking circuit is used for locking the output at a high level when the pulse integrating circuit outputs the high level;
the pulse signal locking circuit is used for enabling the input signal to be connected with the control signal of the bridge type switch circuit when the level comparison locking circuit outputs a low level; when the level comparison locking circuit outputs a high level, the input signal is isolated.
Preferably, the pulse integration circuit comprises diodes DD1, DD2 and DD3, common anodes of the diodes DD1, DD2 and DD3 are respectively connected to input signals IN0, IN1 and IN2 through resistors R74, R75 and R76, one ends of the resistors R74, R75 and R76 are respectively grounded through capacitors C48, C49 and C55, the other ends of the resistors R74, R75 and R76 are respectively connected to one cathode of the diodes DD1, DD2 and DD3, and the other cathodes of the diodes DD1, DD2 and DD3 are connected to a level comparison locking circuit.
Preferably, the other cathode of the diode DD3 is coupled to a latch circuit reset signal EN244C _ JC.
Preferably, the level comparison locking circuit comprises an operational amplifier U9A, a voltage division circuit for providing a reference level for the operational amplifier U9A, and a locking circuit for locking the output when the operational amplifier U9A outputs a high level, wherein a forward input end of the operational amplifier U9A is connected to the other cathode of the diodes DD1, DD2 and DD 3;
the voltage division circuit comprises resistors R78 and R79 which are connected in series, and a capacitor C51 which is connected with a resistor R79 in parallel, wherein the reverse input end of the operational amplifier U9A is connected with a resistor R79;
the locking circuit comprises a resistor R80 and a diode D25 which are connected in series between the output end and the positive input end of an operational amplifier U9A.
Preferably, the output end of the operational amplifier U9A is connected to the pulse signal locking circuit through a diode DD4, one anode of the diode DD4 is connected to the output end of the operational amplifier U9A, the other anode of the diode DD4 is connected to the control signal EN244, and the common cathode of the diode DD4 outputs the pulse locking signal EN 244C.
Preferably, the level comparison locking circuit further comprises a filter circuit, and the filter circuit composed of a capacitor C50 and a resistor R77 is connected to the positive input end of the operational amplifier U9A.
Preferably, the pulse signal locking circuit comprises a bus driver U10, the bus driver U10 is connected with a pulse locking signal EN244C and input signals IN0, IN1 and IN2, and the bus driver U10 sends output signals OUT0, OUT1 and OUT2 to the bridge switching circuit.
(III) advantageous effects
Compared with the prior art, the hardware pulse detection locking circuit provided by the invention can timely close the supply of the control signal of the bridge type switching circuit when the pulse input signal is abnormal, so as to close the main control tube of the bridge type switching circuit, thereby realizing the function of protecting the main circuit when the abnormal pulse occurs; if the circuit needs to be recovered, a low-level reset pulse is added to the reset signal of the locking circuit, and the recovery is very convenient.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
FIG. 1 is a schematic diagram of the circuit connection between a pulse integrator circuit and a level comparison latch circuit according to the present invention;
FIG. 2 is a circuit diagram of a pulse signal locking circuit according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A hardware pulse detection locking circuit, as shown in fig. 1 and 2, comprising:
a pulse integration circuit for integrating an input signal;
the level comparison locking circuit is used for locking the output at a high level when the pulse integrating circuit outputs the high level;
the pulse signal locking circuit is used for enabling the input signal to be connected with the control signal of the bridge type switch circuit when the level comparison locking circuit outputs a low level; when the level comparison locking circuit outputs a high level, the input signal is isolated.
The pulse integration circuit comprises diodes DD1, DD2 and DD3, common anodes of the diodes DD1, DD2 and DD3 are connected with input signals IN0, IN1 and IN2 through resistors R74, R75 and R76 respectively, one ends of the resistors R74, R75 and R76 are grounded through capacitors C48, C49 and C55 respectively, the other ends of the resistors R74, R75 and R76 are connected with one cathode of the diodes DD1, DD2 and DD3 respectively, and the other cathodes of the diodes DD1, DD2 and DD3 are connected with a level comparison locking circuit.
The other cathode of the diode DD3 receives the latch circuit reset signal EN244 _ 244C _ JC.
The level comparison locking circuit comprises an operational amplifier U9A, a voltage division circuit for providing a reference level for the operational amplifier U9A and a locking circuit for locking the output when the operational amplifier U9A outputs a high level, wherein the positive input end of the operational amplifier U9A is connected with the other cathode of the diodes DD1, DD2 and DD 3;
the voltage division circuit comprises resistors R78 and R79 which are connected in series, and a capacitor C51 which is connected with the resistor R79 in parallel, and the reverse input end of the operational amplifier U9A is connected with the resistor R79;
the locking circuit comprises a resistor R80 and a diode D25 which are connected in series between the output end and the positive input end of the operational amplifier U9A.
The output end of the operational amplifier U9A is connected with the pulse signal locking circuit through a diode DD4, one anode of a diode DD4 is connected with the output end of the operational amplifier U9A, the other anode of the diode DD4 is connected with the control signal EN244, and the common cathode of a diode DD4 outputs a pulse locking signal EN 244C.
The level comparison locking circuit further comprises a filter circuit, and the forward input end of the operational amplifier U9A is connected with the filter circuit consisting of a capacitor C50 and a resistor R77.
The pulse signal locking circuit comprises a bus driver U10, wherein the bus driver U10 accesses a pulse locking signal EN244C and input signals IN0, IN1 and IN2, and the bus driver U10 sends output signals OUT0, OUT1 and OUT2 to the access bridge type switching circuit.
When the input signals IN0, IN1, IN2 input normal pulse signals, the pulse integration circuit outputs a low level because there is not enough integration time. At this time, the low level is lower than the reference voltage formed by the voltage divider circuit, and the pulse integration circuit outputs the pulse locking signal EN244C of the low level. The pulse locking signal EN244C is input to the bus driver U10 of the pulse signal locking circuit, and the output signals OUT0, OUT1, and OUT2 are passed through the input signals IN0, IN1, and IN2, and are normally controlled by the input signals IN0, IN1, and IN 2.
When the input signals IN0, IN1, IN2 remain high for a long time, the pulse integration circuit output level gradually rises. When the output of the operational amplifier U9A exceeds the reference voltage formed by the voltage divider circuit, the operational amplifier U9A outputs a high level, the output of the operational amplifier U9A can be locked at the high level by the resistor R80 and the diode D25, and the pulse locking signal EN244C of the high level is output through the diode DD 4.
The pulse locking signal EN244C is input into the bus driver U10 of the pulse signal locking circuit, at the moment, the bus driver U10 is IN a high-impedance state, and the input signals IN0, IN1 and IN2 are isolated from the output signals OUT0, OUT1 and OUT2, so that each bridge arm IN the bridge type switching circuit is closed, and effective protection on a main circuit is formed. If the circuit operation needs to be restored, a low-level reset pulse is added to the latch circuit reset signal EN244C _ JC.
IN the technical scheme of the application, the output end of the operational amplifier U9A is connected with the pulse signal locking circuit through the diode DD4, and the diode DD4 plays a role of "line and line", when any one of the output ends of the EN244 and the operational amplifier U9A is at a high level, the input signals IN0, IN1 and IN2 are isolated from the output signals OUT0, OUT1 and OUT2, so that a better control effect can be achieved.
In the technical scheme of the application, diodes DD1, DD2, DD3, DD4 all use bat54 schottky diodes, operational amplifier U9A uses ad8542, and bus driver U10 uses 74HC 245.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.
Claims (7)
1. A hardware pulse detection lockout circuit, comprising: the method comprises the following steps:
a pulse integration circuit for integrating an input signal;
the level comparison locking circuit is used for locking the output at a high level when the pulse integrating circuit outputs the high level;
the pulse signal locking circuit is used for enabling the input signal to be connected with the control signal of the bridge type switch circuit when the level comparison locking circuit outputs a low level; when the level comparison locking circuit outputs a high level, the input signal is isolated.
2. The hardware pulse detection lock-in circuit of claim 1, wherein: the pulse integration circuit comprises diodes DD1, DD2 and DD3, common anodes of the diodes DD1, DD2 and DD3 are respectively connected with input signals IN0, IN1 and IN2 through resistors R74, R75 and R76, one ends of the resistors R74, R75 and R76 are respectively grounded through capacitors C48, C49 and C55, the other ends of the resistors R74, R75 and R76 are respectively connected with one cathode of the diodes DD1, DD2 and DD3, and the other cathodes of the diodes DD1, DD2 and DD3 are connected with a level comparison locking circuit.
3. The hardware pulse detection lock-in circuit of claim 2, wherein: the other cathode of the diode DD3 is connected to a latch circuit reset signal EN244 _ 244C _ JC.
4. The hardware pulse detection lock-in circuit of claim 2, wherein: the level comparison locking circuit comprises an operational amplifier U9A, a voltage division circuit for providing a reference level for the operational amplifier U9A and a locking circuit for locking the output when the operational amplifier U9A outputs a high level, wherein the positive input end of the operational amplifier U9A is connected with the other cathode of the diodes DD1, DD2 and DD 3;
the voltage division circuit comprises resistors R78 and R79 which are connected in series, and a capacitor C51 which is connected with a resistor R79 in parallel, wherein the reverse input end of the operational amplifier U9A is connected with a resistor R79;
the locking circuit comprises a resistor R80 and a diode D25 which are connected in series between the output end and the positive input end of an operational amplifier U9A.
5. The hardware pulse detection lock-in circuit of claim 4, wherein: the output end of the operational amplifier U9A is connected with a pulse signal locking circuit through a diode DD4, one anode of the diode DD4 is connected with the output end of the operational amplifier U9A, the other anode of the diode DD4 is connected with a control signal EN244, and the common cathode of the diode DD4 outputs a pulse locking signal EN 244C.
6. The hardware pulse detection lock-in circuit of claim 4, wherein: the level comparison locking circuit further comprises a filter circuit, and the forward input end of the operational amplifier U9A is connected with the filter circuit consisting of a capacitor C50 and a resistor R77.
7. The hardware pulse detection lock-in circuit of claim 5, wherein: the pulse signal locking circuit comprises a bus driver U10, wherein the bus driver U10 is connected with a pulse locking signal EN244C, and input signals IN0, IN1 and IN2, and the bus driver U10 sends output signals OUT0, OUT1 and OUT2 to the access bridge type switching circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110549682.1A CN113131924A (en) | 2021-05-20 | 2021-05-20 | Hardware pulse detection locking circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110549682.1A CN113131924A (en) | 2021-05-20 | 2021-05-20 | Hardware pulse detection locking circuit |
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| CN113131924A true CN113131924A (en) | 2021-07-16 |
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| CN202110549682.1A Pending CN113131924A (en) | 2021-05-20 | 2021-05-20 | Hardware pulse detection locking circuit |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101593961A (en) * | 2009-07-07 | 2009-12-02 | 中国科学技术大学 | DC power supply short-circuit protection circuit based on contactless current sample |
| CN104697646A (en) * | 2015-02-09 | 2015-06-10 | 中国计量学院 | Single photon counting identifier circuit with dark counting pulse discrimination |
| CN106569570A (en) * | 2016-10-20 | 2017-04-19 | 上海传英信息技术有限公司 | Hardware power-off circuit and method |
| CN209860580U (en) * | 2019-06-12 | 2019-12-27 | 安徽智纳农业科技有限公司 | Intelligent motor protector |
| CN214626957U (en) * | 2021-05-20 | 2021-11-05 | 安徽智纳智能装备有限公司 | Hardware pulse detection locking circuit |
-
2021
- 2021-05-20 CN CN202110549682.1A patent/CN113131924A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101593961A (en) * | 2009-07-07 | 2009-12-02 | 中国科学技术大学 | DC power supply short-circuit protection circuit based on contactless current sample |
| CN104697646A (en) * | 2015-02-09 | 2015-06-10 | 中国计量学院 | Single photon counting identifier circuit with dark counting pulse discrimination |
| CN106569570A (en) * | 2016-10-20 | 2017-04-19 | 上海传英信息技术有限公司 | Hardware power-off circuit and method |
| CN209860580U (en) * | 2019-06-12 | 2019-12-27 | 安徽智纳农业科技有限公司 | Intelligent motor protector |
| CN214626957U (en) * | 2021-05-20 | 2021-11-05 | 安徽智纳智能装备有限公司 | Hardware pulse detection locking circuit |
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