CN113130442B - MIM capacitor and method for manufacturing the same - Google Patents

MIM capacitor and method for manufacturing the same Download PDF

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CN113130442B
CN113130442B CN202010043961.6A CN202010043961A CN113130442B CN 113130442 B CN113130442 B CN 113130442B CN 202010043961 A CN202010043961 A CN 202010043961A CN 113130442 B CN113130442 B CN 113130442B
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CN113130442A (en
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林昱佑
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Guangdong Hanqi Industrial Technology Research And Development Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions

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Abstract

The invention provides an MIM capacitor and a manufacturing method thereof, wherein the MIM capacitor comprises a CBM electrode (300), a CTM electrode (100) and a first dielectric layer (200) arranged between the CBM electrode (300) and the CTM electrode (100); the MIM capacitor further comprises a second dielectric layer (600) and a first dielectric barrier layer (700) disposed on a bottom surface of the second dielectric layer (600); a trench (610) is formed in the second dielectric layer (600), the trench (610) penetrates through the first dielectric barrier layer (700) and forms a bottom opening on the first dielectric barrier layer (700); the MIM capacitor comprises a first diffusion barrier layer (500) arranged on the inner wall of the trench (610) and closing the bottom opening, and a second diffusion barrier layer (400) arranged in the trench (610) and positioned on the upper surface of the first diffusion barrier layer (500); the CBM electrode (300), the first dielectric layer (200) and the CTM electrode (100) are also disposed within the trench (610); the MIM capacitor and the manufacturing method thereof have novel design and strong practicability.

Description

MIM capacitor and method for manufacturing the same
Technical Field
The invention relates to the field of integrated circuits, in particular to an MIM capacitor and a manufacturing method thereof.
Background
Today, the semiconductor industry is increasing the performance and decreasing the power of integrated chips by continually decreasing the size of the integrated chip components. In the case of a MIM (metal-insulator-metal) capacitor, as the size of integrated chip components is reduced, the capacitance or energy of the MIM capacitor is reduced. This is because the MIM capacitor electrode is also reduced in size as the size of the integrated chip component is reduced. Also, since the capacitance of a MIM capacitor is proportional to the area of the electrodes, a reduction in the size of the electrodes also results in a reduction in the capacitance of the MIM capacitor. The reduction in capacitance makes MIM capacitors difficult to meet device specifications used in today's integrated chips.
As shown in fig. 1-2, fig. 1 shows a schematic structure of a conventional two-dimensional MIM capacitor; fig. 2 illustrates a schematic view of the MIM capacitor shown in fig. 1 in another orientation. In this MIM capacitor, the first metal interconnection line cannot be provided at the same layer as the CTM (capacitor top metal) electrode and the CBM (capacitor bottom metal) electrode, which increases the size of the MIM capacitor. Meanwhile, the CTM contact hole and the CBM contact hole reduce the electrode area of the MIM capacitor, so that the capacitance of the MIM capacitor is reduced.
Disclosure of Invention
The present invention provides an MIM capacitor and a method for manufacturing the same.
The technical scheme provided by the invention is as follows:
the invention provides an MIM capacitor, which comprises a CBM electrode, a CTM electrode and a first dielectric layer arranged between the CBM electrode and the CTM electrode;
the MIM capacitor further comprises a second dielectric layer and a first dielectric barrier layer arranged on the bottom surface of the second dielectric layer; a groove is formed in the second dielectric layer, penetrates through the first dielectric barrier layer and forms a bottom opening on the first dielectric barrier layer;
the MIM capacitor comprises a first diffusion barrier layer and a second diffusion barrier layer, wherein the first diffusion barrier layer is arranged on the inner wall of the groove and seals the bottom opening, and the second diffusion barrier layer is arranged in the groove and positioned on the upper surface of the first diffusion barrier layer; the CBM electrode is arranged in the groove and positioned on the upper surface of the second diffusion impervious layer, and the first dielectric layer and the CTM electrode are also arranged in the groove;
the MIM capacitor also comprises a second dielectric barrier layer which is embedded in the second dielectric layer and positioned above the CTM electrode; a CTM contact hole which penetrates through the second dielectric barrier layer and is communicated with the CTM electrode is formed in the top surface of the second dielectric layer; the MIM capacitor further includes a first metal interconnection layer formed at the bottom of the first dielectric barrier layer and connected to the first diffusion barrier layer, and a second metal interconnection layer filling the CTM contact hole and connected to the CTM electrode.
In the MIM capacitor according to the present invention, the first dielectric barrier layer is an SiN layer; the second dielectric barrier layer adopts an SiN layer;
when the first diffusion impervious layer is a Ta layer, the second diffusion impervious layer is a TaN layer;
when the second diffusion impervious layer is a Ta layer, the first diffusion impervious layer is a TaN layer.
In the above MIM capacitor of the invention, the first dielectric layer is made of HfO and Ta 2 O 5 Or ZrO;
the second dielectric layer is made of SiO 2 A layer or a LOW-K dielectric layer.
In the MIM capacitor according to the present invention, the CTM electrode and the CBM electrode are made of TiN.
In the above-described MIM capacitor according to the present invention, the second metal interconnection layer is made of Al.
The invention also provides a manufacturing method of the MIM capacitor, which comprises the following steps:
step S1, providing a substrate including a fifth dielectric layer, a first dielectric barrier layer disposed on a bottom surface of the fifth dielectric layer, and a first metal interconnection layer formed on a bottom of the first dielectric barrier layer; laying a first etching-resistant photoresist layer with a groove pattern on the top surface of the fifth dielectric layer, and etching a groove which sequentially penetrates through the fifth dielectric layer and the first dielectric barrier layer on the substrate according to the groove pattern of the first etching-resistant photoresist layer; the groove forms a bottom opening on the first dielectric barrier layer and is communicated with the first metal interconnection layer; then removing the first anti-etching photoresist layer;
step S2, laying a first diffusion impervious layer to make the first diffusion impervious layer cover the inner wall of the groove and the top surface of the fifth dielectric layer and make the first diffusion impervious layer seal the bottom opening; laying a second diffusion barrier layer on the upper surface of the first diffusion barrier layer; laying a CBM electrode on the second diffusion barrier layer; arranging a first dielectric layer on the upper surface of the CBM electrode; arranging a CTM electrode on the upper surface of the first dielectric layer;
step S3 of laying a second etching resist layer on a portion of the CTM electrode directly above the trench, and etching away a portion of the CTM electrode not covered by the second etching resist layer to expose the first dielectric layer; then removing the second anti-etching photoresist layer;
step S4, laying a third dielectric layer to cover the CTM electrode and the first dielectric layer; then, a second dielectric barrier layer is arranged on the upper surface of the third dielectric layer;
step S5, a third anti-etching photoresist layer is arranged on the part, located right above the CTM electrode, of the second dielectric barrier layer; etching away the second dielectric barrier layer, the third dielectric layer, the first dielectric layer, the CBM electrode, the second diffusion barrier layer, and the portion of the first diffusion barrier layer not covered by the third etch-resistant photoresist layer to expose the fifth dielectric layer; then removing the third etching-resistant photoresist layer;
step S6, laying a fourth dielectric layer to cover the second dielectric barrier layer and respectively connect with the third dielectric layer and the fifth dielectric layer, thereby forming a second dielectric layer;
step S7, laying a fourth etching-resistant photoresist layer with contact hole patterns on the top surface of the second dielectric layer; etching a CTM contact hole penetrating through the second dielectric barrier layer and communicated with the CTM electrode on the top surface of the second dielectric layer according to a fourth etching-resistant photoresist layer with a contact hole pattern; then removing the fourth etching-resistant photoresist layer;
step S8, covering a second metal interconnection layer on the top surface of the second dielectric layer, and filling the CTM contact hole with the second metal interconnection layer and connecting the CTM electrode;
step S9, a fifth anti-etching photoresist layer is arranged on the part, located right above the groove, of the second metal interconnection layer; then etching away the portion of the second metal interconnection layer not covered by the fifth etch-resistant photoresist layer to expose the second dielectric layer;
and step S10, removing the fifth anti-etching photoresist layer.
In the manufacturing method of the MIM capacitor, the first dielectric barrier layer adopts the SiN layer; the second dielectric barrier layer adopts a SiN layer;
when the first diffusion impervious layer is a Ta layer, the second diffusion impervious layer is a TaN layer;
when the second diffusion impervious layer is a Ta layer, the first diffusion impervious layer is a TaN layer.
In the manufacturing method of the MIM capacitor of the invention, the first dielectric layer is made of HfO and Ta 2 O 5 Or ZrO;
the fourth dielectric layer, the third dielectric layer and the fifth dielectric layer are made of SiO 2 A layer or a LOW-K dielectric layer.
In the manufacturing method of the MIM capacitor according to the present invention, the CTM electrode and the CBM electrode are made of TiN.
In the above method for manufacturing the MIM capacitor according to the present invention, the second metal interconnection layer is made of Al.
The MIM capacitor and the method of manufacturing the same of the present invention greatly increase the capacitance of the MIM capacitor through the second metal interconnect layer. In contrast to the three-dimensional MIM capacitor shown in figure 3, the MIM capacitor of the present inventionThe container increases the size of the MIM capacitor with the second metal interconnect layer through the IMD. The MIM capacitor and the manufacturing method thereof also adopt the structure of the groove, and the MIM layer is arranged on the thickest IMD layer to ensure that the first metal interconnection layer is connected with the CBM electrode and the second metal interconnection layer is connected with the CTM electrode, thereby increasing the total electrode area of the MIM capacitor, and the depth of the groove is greatly increased by arranging the MIM layer on the thickest IMD layer to be larger than that of the groove
Figure BDA0002368716080000041
To increase the sidewall area and thereby increase the capacitance density of the MIM capacitor by at least a factor of 4.6. The MIM capacitor and the manufacturing method thereof have novel design and strong practicability.
Drawings
The invention will be further described with reference to the following drawings and examples, in which:
fig. 1 shows a schematic diagram of a conventional two-dimensional MIM capacitor;
fig. 2 is a schematic diagram of another orientation of the MIM capacitor shown in fig. 1;
fig. 3 shows a schematic structural diagram of a three-dimensional MIM capacitor;
fig. 4 shows a schematic view of another orientation of the MIM capacitor of fig. 3;
fig. 5 is a schematic diagram illustrating a first step of a method of fabricating a MIM capacitor according to a preferred embodiment of the present invention;
fig. 6 is a schematic diagram of a second step of a MIM capacitor fabrication method according to a preferred embodiment of the present invention;
fig. 7 is a schematic diagram of a third step of a MIM capacitor fabrication method according to a preferred embodiment of the present invention;
fig. 8 is a schematic diagram illustrating a fourth step of a method of fabricating a MIM capacitor according to a preferred embodiment of the present invention;
fig. 9 is a schematic diagram illustrating a fifth step of a method of fabricating a MIM capacitor according to a preferred embodiment of the present invention;
fig. 10 is a schematic diagram illustrating a sixth step of a method of fabricating a MIM capacitor according to a preferred embodiment of the present invention;
fig. 11 is a schematic diagram illustrating a seventh step of a method of fabricating a MIM capacitor according to a preferred embodiment of the present invention;
fig. 12 is a schematic diagram illustrating an eighth step of a method of fabricating a MIM capacitor according to a preferred embodiment of the present invention;
fig. 13 is a schematic diagram illustrating a ninth step of a method of fabricating a MIM capacitor according to a preferred embodiment of the present invention;
fig. 14 is a schematic diagram illustrating a tenth step of a method of fabricating a MIM capacitor according to a preferred embodiment of the present invention;
fig. 15 shows a schematic diagram of a MIM capacitor according to a preferred embodiment of the present invention.
Detailed Description
In order to make the technical purpose, technical solutions and technical effects of the present invention more clear and facilitate those skilled in the art to understand and implement the present invention, the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 3-4, fig. 3 shows a schematic structure of a three-dimensional MIM capacitor; fig. 4 shows a schematic view of the MIM capacitor of fig. 3 in another orientation. Specifically, the MIM capacitor includes a CBM electrode 300, a CTM electrode 100, and a first dielectric layer 200 disposed between the CBM electrode 300 and the CTM electrode 100;
further, the MIM capacitor further comprises a second dielectric layer 600 and a first dielectric barrier layer 700 disposed on a bottom surface of the second dielectric layer 600; a trench 610 is formed in the second dielectric layer 600, wherein the trench 610 penetrates through the first dielectric barrier layer 700 and forms a bottom opening on the first dielectric barrier layer 700;
the MIM capacitor includes a first diffusion barrier 500 disposed on an inner wall of the trench 610 and closing the bottom opening, and a second diffusion barrier 400 disposed in the trench 610 and on an upper surface of the first diffusion barrier 500; the CBM electrode 300 is disposed in the trench 610 on the upper surface of the second diffusion barrier layer 400, and the first dielectric layer 200 and the CTM electrode 100 are also disposed in the trench 610. Here, the CBM electrode 300 may be varied between different vertical positions by the trench 610, so that the CBM electrode 300 has a "saw tooth" or curved shape that varies in height according to a lateral position. First dielectric layer 200 is conformally disposed on the top surface of CBM electrode 300, also having a "saw tooth" shape. CTM electrode 100 is also disposed on the top surface of first dielectric layer 200, also having a "saw tooth" shape. Because the area between the CBM electrode 300 and the CTM electrode 100 has a vertical component and a lateral component, the "saw tooth" shape of the CBM electrode 300 increases the surface area between the CBM electrode 300 and the CTM electrode 100, thereby increasing the capacitance of the MIM capacitor.
Further, the MIM capacitor further includes a second dielectric barrier 900 embedded inside the second dielectric layer 600 and located above the CTM electrode 100, and a third dielectric barrier 710 embedded inside the second dielectric layer 600 and located above the second dielectric barrier 900; a CTM contact hole 810 sequentially penetrating through the third dielectric barrier layer 710 and the second dielectric barrier layer 900 and communicating with the CTM electrode 100 is formed on the top surface of the second dielectric layer 600; the MIM capacitor further includes a first metal interconnection layer 800 formed at the bottom of the first dielectric barrier 700 and connected to the first diffusion barrier 500, and a second metal interconnection layer 820 filling the CTM contact hole 810 and connected to the CTM electrode 100.
When the first diffusion barrier layer 500 is a Ta layer, the second diffusion barrier layer 400 is a TaN layer;
when the second diffusion barrier layer 400 is a Ta layer, the first diffusion barrier layer 500 is a TaN layer.
Further, the first dielectric barrier layer 700, the second dielectric barrier layer 900 and the third dielectric barrier layer 710 are all SiN layers. It is understood that other materials may be used for the first dielectric barrier layer 700, the second dielectric barrier layer 900, and the third dielectric barrier layer 710 in other embodiments.
In the above-described technical solution, the region of the CTM electrode 100 of the MIM capacitor is enlarged through the CTM contact hole 810. However, the depth of the trench 610 is limited by an IMD (Inter-Metal Dielectric) thickness of the MIM capacitor, i.e., a distance between the CBM electrode 300 and the CTM electrode 100. This results in the MIM capacitor of this embodiment having only a few times increased capacitance density compared to the existing two-dimensional MIM capacitor, and additional IMD oxide CMP (Chemical Mechanical Polishing) is required for IMD planarization after the MIM (Metal injection Molding) process.
Further, as shown in fig. 5-14, fig. 5 is a schematic diagram illustrating a first step of a method of fabricating a MIM capacitor according to a preferred embodiment of the present invention; fig. 6 is a schematic diagram of a second step of a method of fabricating a MIM capacitor according to a preferred embodiment of the present invention; fig. 7 is a schematic diagram of a third step of a method of fabricating a MIM capacitor according to a preferred embodiment of the present invention; fig. 8 is a schematic diagram illustrating a fourth step of a method of fabricating a MIM capacitor according to a preferred embodiment of the present invention; fig. 9 is a schematic diagram illustrating a fifth step of a method of fabricating a MIM capacitor according to a preferred embodiment of the present invention; fig. 10 is a schematic diagram illustrating a sixth step of a method of fabricating a MIM capacitor according to a preferred embodiment of the present invention; fig. 11 is a schematic diagram illustrating a seventh step of a method of fabricating a MIM capacitor according to a preferred embodiment of the present invention; fig. 12 is a schematic diagram illustrating an eighth step of a method of fabricating a MIM capacitor according to a preferred embodiment of the present invention; fig. 13 is a schematic diagram illustrating a ninth step of a method of fabricating a MIM capacitor according to a preferred embodiment of the present invention; fig. 14 is a schematic diagram illustrating a tenth step of a method of fabricating a MIM capacitor according to a preferred embodiment of the present invention; specifically, the manufacturing method of the MIM capacitor includes the steps of:
step S1, providing a substrate including a fifth dielectric layer 650, a first dielectric barrier layer 700 disposed on a bottom surface of the fifth dielectric layer 650, and a first metal interconnection layer 800 formed on a bottom of the first dielectric barrier layer 700; a first anti-etching photoresist layer 620 with a groove pattern is arranged on the top surface of the fifth dielectric layer 650, and a groove 610 which sequentially penetrates through the fifth dielectric layer 650 and the first dielectric barrier layer 700 is etched on the substrate according to the groove pattern of the first anti-etching photoresist layer 620; the trench 610 forms a bottom opening on the first dielectric barrier layer 700 and communicates with the first metal interconnect layer 800, as shown in fig. 5; the first etch resist layer 620 is then removed;
in this step, the first dielectric barrier layer 700 is a SiN layer.
Step S2, laying the first diffusion barrier 500, so that the first diffusion barrier 500 covers the inner wall of the trench 610 and the top surface of the fifth dielectric layer 650, and the first diffusion barrier 500 closes the bottom opening; laying a second diffusion barrier layer 400 on the upper surface of the first diffusion barrier layer 500; laying a CBM electrode 300 on the second diffusion barrier layer 400; laying a first dielectric layer 200 on the upper surface of the CBM electrode 300; and the CTM electrode 100 is disposed on the upper surface of the first dielectric layer 200, as shown in fig. 6;
in this step, the first dielectric layer 200 is made of HfO, Ta 2 O 5 Or ZrO.
Both the CTM electrode 100 and the CBM electrode 300 are made of TiN.
When the first diffusion barrier layer 500 is a Ta layer, the second diffusion barrier layer 400 is a TaN layer;
when the second diffusion barrier layer 400 is a Ta layer, the first diffusion barrier layer 500 is a TaN layer.
Step S3, disposing a second etching resist layer 110 on the part of the CTM electrode 100 directly above the trench 610, and etching away the part of the CTM electrode 100 not covered by the second etching resist layer 110 to expose the first dielectric layer 200, as shown in fig. 7; the second etch resist layer 110 is then removed;
step S4, laying a third dielectric layer 630 to cover the CTM electrode 100 and the first dielectric layer 200; then, a second dielectric barrier layer 900 is disposed on the upper surface of the third dielectric layer 630, as shown in fig. 8;
the second dielectric barrier 900 employs a SiN layer.
Step S5, laying a third etching-resistant photoresist layer 910 on the portion of the second dielectric barrier layer 900 directly above the CTM electrode 100; etching away the second dielectric barrier layer 900, the third dielectric layer 630, the first dielectric layer 200, the CBM electrode 300, the second diffusion barrier layer 400, and the portion of the first diffusion barrier layer 500 not covered by the third etch-resistant photoresist layer 910 to expose the fifth dielectric layer 650, as shown in fig. 9; the third etch resistant photoresist layer 910 is then removed;
step S6, laying a fourth dielectric layer 640 to cover the second dielectric barrier layer 900 and respectively connect with the third dielectric layer 630 and the fifth dielectric layer 650, thereby forming a second dielectric layer 600, as shown in fig. 10;
in this step, the fourth dielectric layer 640, the third dielectric layer 630 and the fifth dielectric layer 650 may be made of SiO 2 A layer or a LOW-K dielectric layer.
Step S7, disposing a fourth etch-resistant photoresist layer 660 with a contact hole pattern on the top surface of the second dielectric layer 600; etching a CTM contact hole 810 penetrating the second dielectric barrier layer 900 and communicating with the CTM electrode 100 on the top surface of the second dielectric layer 600 according to the fourth etch resist layer 660 having a contact hole pattern, as shown in fig. 11; the fourth etch resist layer 660 is then removed;
step S8, covering the top surface of the second dielectric layer 600 with a second metal interconnection layer 820, and making the second metal interconnection layer 820 fill the CTM contact hole 810 and connect with the CTM electrode 100, as shown in fig. 12;
in this step, the second metal interconnection layer 820 is made of Al, and more specifically, is formed by an IMD process.
Step S9, laying a fifth etch-resistant photoresist layer 830 on the portion of the second metal interconnection layer 820 directly above the trench 610; portions of the second metal interconnect layer 820 not covered by the fifth etch-resistant photoresist layer 830 are then etched away to expose the second dielectric layer 600, as shown in fig. 13;
step S10, the fifth etch resist layer 830 is removed, as shown in fig. 14.
Further, as shown in fig. 14 and fig. 15, fig. 15 shows a schematic structural diagram of an MIM capacitor according to a preferred embodiment of the present invention. Specifically, the MIM capacitor includes a CBM electrode 300, a CTM electrode 100, and a first dielectric layer 200 disposed between the CBM electrode 300 and the CTM electrode 100;
further, the MIM capacitor further comprises a second dielectric layer 600 and a first dielectric barrier layer 700 disposed on a bottom surface of the second dielectric layer 600; a trench 610 is formed inside the second dielectric layer 600, the trench 610 penetrates the first dielectric barrier layer 700 and forms a bottom opening on the first dielectric barrier layer 700;
the MIM capacitor includes a first diffusion barrier 500 disposed on an inner wall of the trench 610 and closing the bottom opening, and a second diffusion barrier 400 disposed in the trench 610 and on an upper surface of the first diffusion barrier 500; the CBM electrode 300 is disposed in the trench 610 and on the upper surface of the second diffusion barrier layer 400, and the first dielectric layer 200 and the CTM electrode 100 are also disposed in the trench 610. Here, the CBM electrode 300 may be varied between different vertical positions by the trench 610, so that the CBM electrode 300 has a "saw tooth" or curved shape that varies in height according to a lateral position. First dielectric layer 200 is conformally disposed on the top surface of CBM electrode 300, also having a "saw tooth" shape. The CTM electrode 100 is also laid on the top surface of the first dielectric layer 200, thus also having a "saw tooth" shape. Because the area between CBM electrode 300 and CTM electrode 100 has a vertical component and a lateral component, the "saw tooth" shape of CBM electrode 300 increases the surface area between CBM electrode 300 and CTM electrode 100, thereby increasing the capacitance of the MIM capacitor.
Further, when the first diffusion barrier layer 500 is a Ta layer, the second diffusion barrier layer 400 is a TaN layer;
when the second diffusion barrier layer 400 is a Ta layer, the first diffusion barrier layer 500 is a TaN layer.
Further, the MIM capacitor further includes a second dielectric barrier layer 900 embedded inside the second dielectric layer 600 and located above the CTM electrode 100; a CTM contact hole 810 penetrating the second dielectric barrier layer 900 and communicating with the CTM electrode 100 is formed on the top surface of the second dielectric layer 600; the MIM capacitor further includes a first metal interconnection layer 800 formed at the bottom of the first dielectric barrier 700 and connected to the first diffusion barrier 500, and a second metal interconnection layer 820 filling the CTM contact hole 810 and connected to the CTM electrode 100.
Further, the first dielectric barrier layer 700 and the second dielectric barrier layer 900 are both SiN layers. It is understood that other materials may be used for the first dielectric barrier layer 700 and the second dielectric barrier layer 900 in other embodiments.
Further, the first dielectric layer 200 is made of HfO, Ta 2 O 5 Or ZrO. Both the CTM electrode 100 and the CBM electrode 300 are made of TiN.
Further, the second dielectric layer 600 may employ SiO 2 A layer or a LOW-K dielectric layer.
Further, the second metal interconnection layer 820 is made of Al, and more particularly, is formed by an IMD process.
The MIM capacitor and the method of manufacturing the same of the present invention greatly increase the capacitance of the MIM capacitor through the second metal interconnect layer. The MIM capacitor of the present invention increases the size of the MIM capacitor using the second metal interconnect layer through IMD, as compared to the three-dimensional MIM capacitor shown in fig. 3. The MIM capacitor and the manufacturing method thereof also adopt the structure of the groove, and the MIM is arranged on the thickest IMD layer, so that the first metal interconnection layer is connected with the CBM electrode, the second metal interconnection layer is connected with the CTM electrode, thereby increasing the total electrode area of the MIM capacitor, and the depth of the groove can be greatly increased by arranging the MIM on the thickest IMD layer to be larger than the depth of the groove
Figure BDA0002368716080000101
To increase the sidewall area and thereby increase the capacitance density of the MIM capacitor by at least a factor of 4.6. The MIM capacitor and the manufacturing method thereof have novel design and strong practicability.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (5)

1. A method of manufacturing a MIM capacitor, comprising the steps of:
step S1, providing a substrate, wherein the substrate comprises a fifth dielectric layer (650), a first dielectric barrier layer (700) arranged on the bottom surface of the fifth dielectric layer (650), and a first metal interconnection layer (800) formed at the bottom of the first dielectric barrier layer (700); laying a first etching-resistant photoresist layer (620) with a groove pattern on the top surface of the fifth dielectric layer (650), and etching a groove (610) which sequentially penetrates through the fifth dielectric layer (650) and the first dielectric barrier layer (700) on the substrate according to the groove pattern of the first etching-resistant photoresist layer (620); the trench (610) forms a bottom opening on the first dielectric barrier layer (700) and communicates with the first metal interconnect layer (800); the first etch resistant photoresist layer is then removed (620);
step S2, laying a first diffusion impervious layer (500) to make the first diffusion impervious layer (500) cover the inner wall of the groove (610) and the top surface of the fifth dielectric layer (650), and make the first diffusion impervious layer (500) close the bottom opening; laying a second diffusion barrier layer (400) on the upper surface of the first diffusion barrier layer (500); laying a CBM electrode (300) on the second diffusion barrier layer (400); arranging a first dielectric layer (200) on the upper surface of the CBM electrode (300); arranging a CTM electrode (100) on the upper surface of the first dielectric layer (200);
step S3, disposing a second anti-etching photoresist layer (110) on the part of the CTM electrode (100) directly above the trench (610), and etching away the part of the CTM electrode (100) not covered by the second anti-etching photoresist layer (110) to expose the first dielectric layer (200); the second etch resist layer (110) is then removed;
step S4, laying a third dielectric layer (630) to cover the CTM electrode (100) and the first dielectric layer (200); then laying a second dielectric barrier layer (900) on the upper surface of the third dielectric layer (630);
step S5, laying a third etching-resistant photoresist layer (910) on the part of the second dielectric barrier layer (900) which is positioned right above the CTM electrode (100); etching away the second dielectric barrier layer (900), the third dielectric layer (630), the first dielectric layer (200), the CBM electrode (300), the second diffusion barrier layer (400), and the portion of the first diffusion barrier layer (500) not covered by the third etch-resistant photoresist layer (910) to expose the fifth dielectric layer (650); the third etch resistant photoresist layer is then removed (910);
step S6, laying a fourth dielectric layer (640) to cover the second dielectric barrier layer (900) and respectively connected with the third dielectric layer (630) and the fifth dielectric layer (650) so as to form a second dielectric layer (600);
step S7, a fourth anti-etching photoresist layer (660) with a contact hole pattern is arranged on the top surface of the second dielectric layer (600); etching a CTM contact hole (810) penetrating the second dielectric barrier layer (900) and communicating with the CTM electrode (100) on the top surface of the second dielectric layer (600) according to a fourth etch-resistant photoresist layer (660) having a contact hole pattern; the fourth etch resistant photoresist layer (660) is then removed;
step S8, covering a second metal interconnection layer (820) on the top surface of the second dielectric layer (600), and making the second metal interconnection layer (820) fill the CTM contact hole (810) and connect with the CTM electrode (100);
step S9, laying a fifth anti-etching photoresist layer (830) on the part of the second metal interconnection layer (820) which is positioned right above the groove (610); then etching away the portion of the second metal interconnect layer (820) not covered by the fifth etch-resistant photoresist layer (830) to expose the second dielectric layer (600);
step S10, the fifth etch-resistant photoresist layer is removed (830).
2. The method of manufacturing a MIM capacitor according to claim 1 wherein the first dielectric barrier (700) is a SiN layer; the second dielectric barrier layer (900) adopts an SiN layer;
when the first diffusion impervious layer (500) is a Ta layer, the second diffusion impervious layer (400) is a TaN layer;
when the second diffusion barrier layer (400) is a Ta layer, the first diffusion barrier layer (500) is a TaN layer.
3. The method of claim 1, wherein the first dielectric layer (200) is made of HfO, Ta 2 O 5 Or ZrO;
the fourth dielectric layer (640), the third dielectric layer (630) and the fifth dielectric layer (650) are made of SiO 2 A layer or a LOW-K dielectric layer.
4. The method of claim 1, wherein the CTM electrode (100) and the CBM electrode (300) are made of TiN.
5. The method of manufacturing a MIM capacitor according to claim 1 wherein the second metal interconnect layer (820) is made of Al.
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