CN113127273B - Singlechip detection circuit and corresponding detection method - Google Patents
Singlechip detection circuit and corresponding detection method Download PDFInfo
- Publication number
- CN113127273B CN113127273B CN201911412778.2A CN201911412778A CN113127273B CN 113127273 B CN113127273 B CN 113127273B CN 201911412778 A CN201911412778 A CN 201911412778A CN 113127273 B CN113127273 B CN 113127273B
- Authority
- CN
- China
- Prior art keywords
- instruction
- comparison
- data
- program memory
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Quality & Reliability (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention relates to a singlechip detection circuit and a corresponding detection method, wherein, by checking the accuracy of a PC address transmitted to a program memory by a central processing unit and the accuracy of instruction data output by the program memory, whether the operation of a real-time monitoring instruction is normal or not is ensured, the condition that the central processing unit works in disorder caused by the operation error of the instruction is avoided, the abnormality of the circuit can be checked in time, and the system is prevented from continuously operating after the failure, thereby causing more serious damage. The single chip microcomputer detection circuit and the corresponding detection method are adopted for detection, and less logic can be adopted for detection, so that the detection speed is high, and the situation that unnecessary function settings exist is prevented by comprehensively monitoring the running process of the central processing unit and the instruction part data in the corresponding program memory data, and the detection circuit has the characteristics of safety, reliability and high efficiency.
Description
Technical Field
The invention relates to the field of circuits, in particular to the technical field of single-chip microcomputer detection, and specifically relates to a single-chip microcomputer detection circuit and a corresponding detection method.
Background
With the development of integrated circuits, the safety requirements of regulatory authorities around the world on single-chip Microcomputer (MCU) are continuously improved, and there are standards of single-chip Microcomputer (MCU) for home appliances and standards of single-chip Microcomputer (MCU) for automobiles, so as to protect users from injury and damage of the machine itself. The program running stability and the data safety of the singlechip are the problems which a designer must consider in different running environments, and the most easily encountered problems are that the CPU can encounter the following conditions after the singlechip is interfered:
case 1: the CPU enters some unknown areas;
case 2: the data read error in the program memory results in subsequent execution error, the data consists of operation code and operand, the error of operation code affects the data error of the register, the error of operand results in the uncontrolled control of CPU, the error of operand results in the data error of the register directly, the difference between the two data is that the operation code is the item fixed by CPU kernel, the data range is definite, the operand is set by user, and the data range is uncertain.
Once the single-chip microcomputer is in operation, damage to operation equipment may be caused, for example:
in the environment of motor application, the interference is great, and the procedure runs and flies and can cause the motor to not normally work, if can not shut down in time after stopping and make the drive be in continuous on state, easily lead to the motor to generate heat and damage, causes more abominable result even.
In summary, the anti-interference performance of the whole system of the device is critical, and for the singlechip, emergency measures are necessary to be taken in the first time after the CPU program runs.
In the prior art, a software trap and a software watchdog are generally adopted to prompt that the system is not normally operated, the operation flow is shown in fig. 1, and by adopting the software monitoring method, once a Central Processing Unit (CPU) executes errors, the execution of a circuit is uncertain and can jump to an abnormal program area, a watchdog timer (WDT) can not clear 0 timely and overflow for resetting, or enter the software trap to execute dead cycles, and the abnormal program area can be adjusted to a normal program area again, so that the capture of the abnormality can be missed and can not be processed timely.
The software protection method needs a certain time to enable the circuit to detect faults, and the time when the abnormality is detected cannot be ensured to be the first time when the abnormality occurs, so that untimely processing can be caused. The method can be applied to the situation that the time requirement for finding faults is not high, but the requirement of timeliness is often not met if continuous operation or severe environment conditions exist.
Disclosure of Invention
The invention aims to overcome at least one defect of the prior art and provides a singlechip detection circuit with stable performance and high test speed and a corresponding detection method.
In order to achieve the above purpose, the singlechip detection circuit and the corresponding detection method of the invention are as follows:
the single chip microcomputer detection circuit is mainly characterized by comprising:
and the instruction comparison module of the address comparison and program memory is connected with the central processing unit and the program memory and is used for checking the PC address transmitted to the program memory by the central processing unit and the instruction data output by the program memory.
Preferably, the address comparison and instruction comparison module of the program memory comprises an address comparison sub-module and an instruction comparison sub-module;
the input end of the address comparison sub-module is used for receiving the PC address, and the output end of the address comparison sub-module outputs a verification result of the PC address;
the input end of the instruction comparison sub-module is used for receiving the data output by the program memory, and the output end of the instruction comparison sub-module outputs a verification result of the instruction data in the data output by the program memory.
Preferably, the instruction comparing submodule is used for checking the operation code in the instruction data.
Further, the instruction comparison submodule includes: the device comprises an operation code extraction unit, a decoding unit and a bitwise comparison unit;
the input end of the operation code extraction unit forms the input end of the instruction comparison submodule, the output end of the operation code extraction unit is connected with the input end of the decoding unit, and the operation code extraction unit is used for extracting the operation code from the data output by the program memory;
the input end of the bitwise comparison unit is correspondingly connected with a port in the decoding unit for outputting data corresponding to the operation code, and the output end of the bitwise comparison unit is used as the output end of the instruction comparison sub-module to output the verification result of the instruction data.
Further, the instruction comparing sub-module further comprises a first or gate, a second or gate, a selector and a trigger;
the first input end of the first OR gate is connected with a port in the decoding unit, which is used for outputting data corresponding to the long-call subroutine instruction;
the second input end of the first OR gate is connected with a port for outputting data corresponding to the long jump instruction in the decoding unit;
the output end of the first OR gate is connected with the first input end of the selector, and the second input end of the selector is grounded;
the input end of the trigger is connected with the output end of the selector, and the clock end of the trigger is connected with a clock signal; the output end of the trigger is connected with the selection end of the selector and the first input end of the second OR gate at the same time;
the output end of the bitwise comparison unit is connected with the second input end of the second OR gate;
and the output end of the second OR gate is used as the output end of the instruction comparison submodule to output the verification result of the instruction data.
More preferably, the address comparison submodule comprises a first subtracter, a second subtracter and an AND gate;
the input end of the first subtracter and the input end of the second subtracter form the input end of the address comparison submodule together, the PC address is input into the first subtracter and the second subtracter, and the PC address is compared with a threshold value set in the first subtracter and a threshold value set in the second subtracter respectively;
the output end of the first subtracter is connected with the first input end of the AND gate, and the output end of the second subtracter is connected with the second input end of the AND gate;
the output end of the AND gate forms the output end of the address comparison sub-module.
Preferably, the address comparison and instruction comparison module of the program memory transmits a verification result for verifying the PC address transmitted to the program memory by the central processing unit and the instruction data output by the program memory to the central processing unit.
The method for realizing the detection of the singlechip based on the singlechip detection circuit is mainly characterized by comprising the following steps of:
and the address comparison and instruction comparison module of the program memory checks the PC address transmitted to the program memory by the central processing unit and the instruction data output by the program memory one by one so as to monitor the working state of the singlechip.
Preferably, the address comparing and program memory command comparing module includes an address comparing sub-module and a command comparing sub-module, and the address comparing and program memory command comparing module checks the PC address and the program memory command data sent from the cpu to the program memory one by one, including the following operations:
the address comparison submodule collects the PC addresses one by one, judges whether each PC address is in a preset system range or not in sequence, and judges that the working state of the singlechip is abnormal when detecting that any PC address is not in the preset system range;
the command comparison submodule collects the command data one by one, judges whether the command data are consistent with corresponding system preset data or not in sequence, and judges that the working state of the singlechip is abnormal when detecting that the command data collected by any one of the command comparison submodules are inconsistent with the corresponding system preset data.
Preferably, the instruction comparing submodule is used for checking the operation code in the instruction data, and the instruction comparing submodule comprises an operation code extracting unit, a decoding unit and a bitwise comparing unit;
the command comparison submodule collects the command data one by one, judges whether the command data are consistent with corresponding system preset data in sequence, and judges that the working state of the singlechip is abnormal when detecting that the command data collected by any one command comparison submodule are inconsistent with the corresponding system preset data, the method comprises the following steps:
(1) The operation code extraction unit acquires the data currently output by the program memory, and extracts the operation code in the instruction data from the data currently output by the program memory as the current operation code;
(2) The decoding unit decodes the current operation code and transmits decoded data corresponding to the current operation code to the bitwise comparison unit;
(3) The bit-by-bit comparison unit compares each bit value in the decoded data corresponding to the current operation code with each bit value in the corresponding system preset data respectively, if the decoded data corresponding to the current operation code is identical to the corresponding system preset data, the bit-by-bit comparison unit judges that the instruction data currently output by the program memory is correct, and returns to the step (1) until the verification of the instruction data output by the program memory is completed; if the decoded data corresponding to the current operation code is not identical to the corresponding system preset data, the bit-by-bit comparison unit judges that the working state of the singlechip is abnormal.
Further, if the instruction comparing submodule detects that the data currently output by the program memory is any one instruction of a long-call subroutine instruction or a long-jump instruction, the comparison result of the current operation code output by the bitwise comparing unit is not used as a checking result, and the step (1) is returned, otherwise, the comparison result of the current operation code output by the bitwise comparing unit is used as a checking result.
The singlechip detection circuit and the corresponding detection method are used for verifying the accuracy of the PC address transmitted to the program memory by the central processing unit and the accuracy of the instruction data output by the program memory, so that whether the operation of the instruction is normal or not is ensured to be monitored in real time, the condition that the central processing unit works in disorder caused by the error operation of the instruction is avoided, the abnormality of the circuit can be timely detected, and the system is prevented from continuously operating after the system fails to cause more serious damage. The singlechip detection circuit and the corresponding detection method are adopted for detection, and less logic is adopted for detection, so that the singlechip detection circuit has the characteristics of higher detection speed, safety, reliability and high detection efficiency, and unnecessary function settings are prevented by comprehensively monitoring the running process of the central processing unit and the instruction data of corresponding program memory data.
Drawings
FIG. 1 is a flow chart of monitoring the operation state of a singlechip in the prior art.
Fig. 2 is a schematic diagram of a single chip microcomputer detection circuit according to an embodiment of the present invention.
FIG. 3 is a schematic diagram of an instruction comparison sub-module according to an embodiment of the present invention.
FIG. 4 is a timing diagram of the long call subroutine instruction or long jump instruction processing of the instruction comparison sub-module of FIG. 3.
FIG. 5 is a schematic diagram of an address comparison sub-module according to an embodiment of the present invention.
Detailed Description
In order to more clearly describe the technical contents of the present invention, a further description will be made below in connection with specific embodiments.
The invention discloses a single-chip microcomputer detection circuit and a corresponding detection method, as shown in fig. 2, 3 and 5, the single-chip microcomputer detection circuit comprises:
and the instruction comparison module of the address comparison and program memory is connected with the Central Processing Unit (CPU) and the program memory and is used for checking the PC address transmitted to the program memory by the CPU and the instruction data output by the program memory.
In this embodiment, the address comparison and instruction comparison module of the program memory includes an address comparison sub-module and an instruction comparison sub-module;
the input end of the address comparison sub-module is used for receiving the PC address, and the output end of the address comparison sub-module outputs a verification result of the PC address;
the input end of the instruction comparison sub-module is used for receiving the data input by the program memory, and the output end of the instruction comparison sub-module outputs a verification result of the instruction data in the data input by the program memory.
In this embodiment, the instruction comparison submodule is configured to verify an opcode in the instruction data.
In this embodiment, the instruction comparison submodule includes: the device comprises an operation code extraction unit, a decoding unit and a bitwise comparison unit;
the input end of the operation code extraction unit forms the input end of the instruction comparison submodule, the output end of the operation code extraction unit is connected with the input end of the decoding unit, and the operation code extraction unit is used for extracting the operation code from the data output by the program memory;
the input end of the bitwise comparison unit is correspondingly connected with a port in the decoding unit for outputting data corresponding to the operation code, and the output end of the bitwise comparison unit is used as the output end of the instruction comparison sub-module to output the verification result of the instruction data; in this embodiment, the use of the bitwise comparing unit uses the corresponding comparison of the data of each bit output by the decoding unit with the preset value in the bitwise comparing unit (i.e., the superposition comparison using the or gate in the bitwise comparing unit), thereby implementing the calibration function.
The instruction comparison sub-module further comprises a first OR gate OR1, a second OR gate OR2, a selector and a trigger;
the first input end of the first OR gate OR1 is connected with a port in the decoding unit, which is used for outputting data corresponding to the long-call subprogram instruction;
the second input end of the first OR gate OR1 is connected with a port for outputting data corresponding to the long jump instruction in the decoding unit;
the output end of the first OR gate OR1 is connected with the first input end of the selector, and the second input end of the selector is grounded;
the input end of the trigger is connected with the output end of the selector, and the clock end of the trigger is connected with a clock signal; the output end of the trigger is connected with the selection end of the selector and the first input end of the second OR gate OR2 at the same time;
the output end of the bitwise comparison unit is connected with the second input end of the second OR gate OR 2;
the output end of the second OR gate OR2 is used as the output end of the instruction comparing sub-module, and the verification result of the instruction data is output.
As shown in fig. 3, when the port Bit < k+q > =1 in the decoding unit for outputting the data corresponding to the long-call subroutine instruction, the current instruction is the long-call subroutine instruction; when the port Bit < k+p > =1 in the decoding unit for outputting the data corresponding to the long jump instruction, the current instruction is the long jump instruction
The instruction comparison sub-module can solve the problem of subsequent execution errors caused by data reading errors in the program memory, and can be used for matching whether an operation code part of instruction data in program memory data corresponding to the PC pointer is consistent with a correct operation code preset in a system or not in real time, so that the program memory data part corresponding to the PC pointer can be dynamically monitored in real time. In this circuit, an operation code section is divided from a command data composition structure in program memory data, and after decoding processing, whether or not data corresponding to an operation code is normal is judged by judging decoded data corresponding to the operation code, and if there is an abnormality, an abnormality flag is immediately output.
As the instruction formats in the singlechip are generally three: the operation code is not defaultable, and is determined, the detection process is convenient and quick, the size of the operand is not fixed, and therefore, the operation code is selected to be compared on the premise of considering the accuracy and the efficiency of detection in the embodiment.
In other embodiments, for example, when executing some single-cycle programs, the output end of the bitwise comparing unit may be directly used as the output end of the instruction comparing sub-module without setting the first OR gate OR1, the second OR gate OR2, the selector and the trigger, and the check result of the instruction data may be output.
In order to better explain the technical scheme, the following uses a program memory data format of an 8-bit singlechip as an example, and because the 8-bit singlechip is selected, the decoder in fig. 3 can decode 256 bits of data, and four groups of data are listed below:
a first group: 0010 1111 kkkkkkkkkkkk denotes AND A, K (K is an immediate number);
second group: 1110 1111 11rr rrrr denotes OR A, R;
third group: 0000 0011 11kk kkkkk denotes CALL K;
fourth group: 0000 1011 1101 1111KKKK KKKK KKKK KKKK LCALL K;
the first set of data and the second set of data represent the characteristics of a logic operation type instruction, and arithmetic operation is also the same, wherein the difference between the first set of data and the second set of data is that the first set of data is aimed at an immediate operation mode, the second set of data is aimed at a register operation mode, the operation code of the first set of data is 8 bits, the operation code of the second set of data is 10 bits, but the lower two-bit operation code of the second set of data is a default value, and the default value is 1 in the instruction decoding process and can be ignored.
The third set of data and the fourth set of data represent call instructions, the difference between the first set of data and the second set of data is that the upper four bits are 0, and another problem of long call subroutine instruction LCALL is that it needs to occupy two instruction cycles, and if the instruction is not recognized, the instruction such as long call subroutine instruction LCALL is misjudged. In this case, according to the flow executed in fig. 3, when the 11 th bit of the decoding result is 1, the instruction is indicated as a long call subroutine instruction LCALL instruction, and a flag 1 is output as a basis for whether the next group of data is to be compared or not. For better understanding, the circuit in fig. 3 is analyzed with reference to fig. 4 for the case that the long call subroutine command LCALL and the long jump command LJMP are encountered, fig. 4 is a timing chart of the long call subroutine command OR the long jump command processing of the command comparison submodule in fig. 3, the timing of the output terminal of the first OR gate OR1, the timing of the clock signal received by the clock terminal of the flip-flop, the timing of the output terminal of the flip-flop, and the timing of the output terminal of the selector are plotted sequentially from top to bottom, from these timings, it can be seen that the timing of the clock signal is not affected by the outside, and changes from 0 to 1 when the long call subroutine command LCALL OR the long jump command LJMP is included in the detected command data in the program memory, the signal output from the output terminal of the first OR gate OR1 is 0 in the initial case, the data output from the first input terminal of the selector is received at the low level when the selection terminal of the selector is received at the low level, and the data output from the second input terminal of the selector is received at the high level when the selection terminal of the selector is received at the second input terminal of the selector. Therefore, when the selector outputs a high level, the trigger outputs a standard when the signal output by the output end of the selector changes to a later instruction period of the high level, prompts the comparison module to ignore the data of the period, then in the later period, the output end of the trigger is restored to be the original state, and if the next instruction period is still a long calling subprogram instruction or a long jump instruction, a mark is output when the next instruction period of the trigger is again, prompts the comparison module to ignore the data of the period.
The instruction comparison sub-module in the embodiment can identify the long jump instruction and the long call sub-program instruction in the double-period or multi-period program, so that misjudgment caused by the occurrence of the long jump instruction and the long call sub-program instruction is avoided, and detection of the corresponding instruction is skipped when the long jump instruction and the long call sub-program instruction are detected.
In this embodiment, as shown in FIG. 3, the operation code included in the instruction data in the program memory data can be decoded first, considering that the operation code data is fixed but discontinuous, assuming that the total number of instructions of the operation code is n and the number of bits of the operation code is m,2 m (number of decoded data bits)) And (3) if the data is larger than n, only taking n-bit data corresponding to the normal instruction for phase or superposition comparison. Decoded 2 m One bit of the bit data is necessarily 1, if the operation code is wrong, the bit 1 is outside the designated n-bit data, so that the output bit 0 is compared, and the error is indicated, and otherwise, the operation code is correct.
In fig. 3, bit (k) -bit (k+n-1) bits are input to the bitwise comparison unit, where n is the total number of instructions of the preset opcode and n is the bit of the first-ordered opcode in the n-bit opcode. In this embodiment, bits (k) to bit (k+n-1), that is, the bit of 256 bits of data decoded by the correct instruction, are 1, and bits (k) to bit (k+n-1) are not continuous data, for example, correct instruction data <15:8> (i.e., program memory data <15:8 >) is 0×32,0×56, and the decoded data bit50 corresponding to 0×32 is 1, and the rest is 0; the decoded data bit86 corresponding to 0x56 is 1 and the rest is 0, and the decoding result cannot be incremented one by one because the operation code is discontinuous.
In this embodiment, the address comparison submodule includes a first subtracter, a second subtracter and an and gate;
the input end of the first subtracter and the input end of the second subtracter form the input end of the address comparison submodule together, the PC address is input into the first subtracter and the second subtracter, and the PC address is compared with a threshold value (namely an upper limit range of a preset PC address) set in the first subtracter and a threshold value (namely a lower limit range of the preset PC address) set in the second subtracter respectively;
the output end of the first subtracter is connected with the first input end of the AND gate, and the output end of the second subtracter is connected with the second input end of the AND gate;
the output end of the AND gate forms the output end of the address comparison sub-module.
The user can complete the setting of the self-defined area (namely the area which is defined by the user and works abnormally) by setting the threshold value in the first subtracter and the threshold value in the second subtracter in the address comparison submodule, and judge whether the CPU operates in the normal working area or not by comparing the PC address with the threshold values of the first subtracter and the threshold value of the second subtracter, if the CPU operates in the normal working area, the output end of the address comparison submodule (namely the output end of the AND gate) can immediately output the abnormal mark. As shown in fig. 5, in this embodiment, the PC address (i.e., the PC in fig. 5, which is a specific numerical value) is subtracted from the threshold value in the first subtractor (i.e., A1 in fig. 5) and the threshold value in the second subtractor (i.e., A2 in fig. 5), respectively, and the sign bit output from the subtractor is input to the and gate to obtain whether it falls within the normal range. In fig. 5, A1-A2 is a preset abnormal working area, the value of A1 is smaller than the value of A2, if a PC enters the A1-A2 interval, A1-PC generates a symbol bit 1, PC-A2 generates a symbol bit 1, the output result is 1, otherwise, the output is 0. In the embodiment, comparing a PC address of a running circuit with a preset abnormal working area, if the PC address is consistent with the preset abnormal working address, namely, a Central Processing Unit (CPU) runs to the abnormal working area, the comparison result is 1, and the circuit enters a Central Processing Unit (CPU) abnormal working processing flow; if the PC address is inconsistent with the preset abnormal operation address, that is, the Central Processing Unit (CPU) does not run in the abnormal operation area defined by the user, the comparison result is 0, and the circuit continues to run normally.
In this embodiment, as shown in fig. 2, the address comparison and instruction comparison module of the program memory transmits a verification result for verifying the PC address transmitted from the Central Processing Unit (CPU) to the program memory and the instruction data output from the program memory to the Central Processing Unit (CPU), and the central processing unit further performs operations of writing signals and reading signals to the program memory.
The technical scheme in the embodiment fully utilizes the distribution of address data and the multi-aspect relation of the compiler, the internal long jump instruction and the interrupt. By adopting the singlechip detection circuit in the embodiment, aiming at the condition that a Central Processing Unit (CPU) enters some unknown areas, the accuracy of a PC address can be checked in real time, so that the judgment of whether the CPU runs in a normal working area is realized, and whether an operation code is normal is judged by dynamically monitoring an instruction data part corresponding to a PC pointer in real time so as to further monitor the circuit; because the operation codes are generally fixed, each operation code can be compared with a system preset value preset in the bitwise comparison unit by adopting the bitwise comparison unit, so that verification is realized, a range is not required to be given when the verification of the PC address is not required, and whether corresponding data falls into the preset range is judged.
If the singlechip detection circuit is adopted for detection, the working state of the singlechip can be monitored by adopting the following singlechip detection method, and the method comprises the following steps:
the address comparison and instruction comparison module of the program memory checks the PC address transmitted to the program memory by the CPU and the instruction data output by the program memory one by one so as to monitor the working state of the singlechip, and specifically comprises the following operations:
the address comparison submodule collects the PC addresses one by one, judges whether each PC address is in a preset system range or not in sequence, and judges that the working state of the singlechip is abnormal when detecting that any PC address is not in the preset system range;
before detection, the flexibly configurable option entrance is used for configuring the range of the address comparison submodule, namely, the preset range of the system is set, and in combination with the singlechip detection circuit in the embodiment, the flexibly configurable option entrance is used for setting the threshold value in the first subtracter and the threshold value in the second subtracter, so that the preset range of the system is set.
The command comparison submodule collects the command data one by one, judges whether the command data are consistent with corresponding system preset data or not in sequence, and judges that the working state of the singlechip is abnormal when detecting that the command data collected by any one of the command comparison submodules are inconsistent with the corresponding system preset data, specifically comprises the following steps:
(1) The operation code extraction unit acquires the data currently output by the program memory, and extracts the operation code in the instruction data from the data currently output by the program memory as the current operation code;
(2) The decoding unit decodes the current operation code and transmits decoded data corresponding to the current operation code to the bitwise comparison unit;
(3) The bit-by-bit comparison unit compares each bit value in the decoded data corresponding to the current operation code with each bit value in the corresponding system preset data respectively, if the decoded data corresponding to the current operation code is identical to the corresponding system preset data, the bit-by-bit comparison unit judges that the instruction data currently output by the program memory is correct, and returns to the step (1) until the verification of the instruction data output by the program memory is completed; if the decoded data corresponding to the current operation code is not identical to the corresponding system preset data, the bit-by-bit comparison unit judges that the working state of the singlechip is abnormal.
In the detection process, if the instruction comparison submodule detects that the data currently output by the program memory is any one of a long-call subroutine instruction and a long-jump instruction, the comparison result of the current operation code output by the bitwise comparison unit is not taken as a verification result, the step (1) is returned, and otherwise, the comparison result of the current operation code output by the bitwise comparison unit is taken as a verification result; in combination with the singlechip detection circuit in the embodiment, corresponding functions are realized through the first or gate, the second or gate, the selector and the trigger.
The circuit in the embodiment solves the problems that the existing software method is slow in running time and cannot respond immediately after interference is generated, meanwhile, the instruction is guaranteed to run normally from the angle of an operation code, confusion of the work of a CPU (central processing unit) caused by the error of the instruction running is avoided, and the circuit is simple, convenient to implement and low in cost.
In general, the invention employs less logic, faster speed and more comprehensive methods to monitor the CPU operation and instruction data in the corresponding program memory to prevent undue function settings.
The singlechip detection circuit and the corresponding detection method are used for verifying the accuracy of the PC address transmitted to the program memory by the central processing unit and the accuracy of the instruction data output by the program memory, so that whether the operation of the instruction is normal or not is ensured to be monitored in real time, the condition that the central processing unit works in disorder caused by the error operation of the instruction is avoided, the abnormality of the circuit can be timely detected, and the system is prevented from continuously operating after the system fails to cause more serious damage. The singlechip detection circuit and the corresponding detection method adopt less logic, so that the singlechip detection circuit has higher detection speed, and the singlechip detection circuit and the corresponding detection method have the characteristics of safety, reliability and high efficiency by comprehensively monitoring the running process of the central processing unit and the instruction data of corresponding program memory data, and preventing the occurrence of unnecessary function settings.
In this specification, the invention has been described with reference to specific embodiments thereof. It will be apparent, however, that various modifications and changes may be made without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (9)
1. The utility model provides a singlechip detection circuit which characterized in that, singlechip detection circuit include:
the instruction comparison module of the address comparison and program memory is connected with the central processing unit and the program memory and is used for checking the PC address transmitted to the program memory by the central processing unit and the instruction data output by the program memory;
the address comparison and instruction comparison module of the program memory comprises an address comparison sub-module and an instruction comparison sub-module;
the input end of the address comparison sub-module is used for receiving the PC address, and the output end of the address comparison sub-module outputs a verification result of the PC address;
the input end of the instruction comparison sub-module is used for receiving the data output by the program memory, and the output end of the instruction comparison sub-module outputs a verification result of the instruction data in the data output by the program memory;
the address comparison submodule comprises a first subtracter, a second subtracter and an AND gate;
the input end of the first subtracter and the input end of the second subtracter form the input end of the address comparison submodule together, the PC address is input into the first subtracter and the second subtracter, and the PC address is compared with a threshold value set in the first subtracter and a threshold value set in the second subtracter respectively;
the output end of the first subtracter is connected with the first input end of the AND gate, and the output end of the second subtracter is connected with the second input end of the AND gate;
the output end of the AND gate forms the output end of the address comparison sub-module.
2. The single chip microcomputer detection circuit of claim 1, wherein said instruction comparison submodule is configured to verify an operation code in said instruction data.
3. The single-chip microcomputer detection circuit according to claim 2, wherein the instruction comparison submodule includes: the device comprises an operation code extraction unit, a decoding unit and a bitwise comparison unit;
the input end of the operation code extraction unit forms the input end of the instruction comparison submodule, the output end of the operation code extraction unit is connected with the input end of the decoding unit, and the operation code extraction unit is used for extracting the operation code from the data output by the program memory;
the input end of the bitwise comparison unit is correspondingly connected with a port in the decoding unit for outputting data corresponding to the operation code, and the output end of the bitwise comparison unit is used as the output end of the instruction comparison sub-module to output the verification result of the instruction data.
4. The single chip microcomputer detection circuit of claim 3, wherein said instruction comparison sub-module further comprises a first or gate, a second or gate, a selector and a trigger;
the first input end of the first OR gate is connected with a port in the decoding unit, which is used for outputting data corresponding to the long-call subroutine instruction;
the second input end of the first OR gate is connected with a port for outputting data corresponding to the long jump instruction in the decoding unit;
the output end of the first OR gate is connected with the first input end of the selector, and the second input end of the selector is grounded;
the input end of the trigger is connected with the output end of the selector, and the clock end of the trigger is connected with a clock signal; the output end of the trigger is connected with the selection end of the selector and the first input end of the second OR gate at the same time;
the output end of the bitwise comparison unit is connected with the second input end of the second OR gate;
and the output end of the second OR gate is used as the output end of the instruction comparison submodule to output the verification result of the instruction data.
5. The single chip microcomputer detection circuit according to claim 1, wherein said address comparison and instruction comparison module of said program memory transmits a verification result for verifying the PC address transmitted from said central processing unit to said program memory and the instruction data outputted from said program memory to said central processing unit.
6. A method for realizing detection of a single chip microcomputer based on the single chip microcomputer detection circuit according to any one of claims 1 to 5, characterized in that the method comprises the following steps:
and the address comparison and instruction comparison module of the program memory checks the PC address transmitted to the program memory by the central processing unit and the instruction data output by the program memory one by one so as to monitor the working state of the singlechip.
7. The method of claim 6, wherein the address comparison and program memory command comparison module comprises an address comparison sub-module and a command comparison sub-module, and the address comparison and program memory command comparison module checks the PC address and the program memory command data sent from the cpu to the program memory one by one, comprising the following operations:
the address comparison submodule collects the PC addresses one by one, judges whether each PC address is in a preset system range or not in sequence, and judges that the working state of the singlechip is abnormal when detecting that any PC address is not in the preset system range;
the command comparison submodule collects the command data one by one, judges whether the command data are consistent with corresponding system preset data or not in sequence, and judges that the working state of the singlechip is abnormal when detecting that the command data collected by any one of the command comparison submodules are inconsistent with the corresponding system preset data.
8. The method of claim 7, wherein the instruction comparing submodule is used for checking the operation code in the instruction data, and the instruction comparing submodule comprises an operation code extracting unit, a decoding unit and a bit-by-bit comparing unit;
the command comparison submodule collects the command data one by one, judges whether the command data are consistent with corresponding system preset data in sequence, and judges that the working state of the singlechip is abnormal when detecting that the command data collected by any one command comparison submodule are inconsistent with the corresponding system preset data, the method comprises the following steps:
(1) The operation code extraction unit acquires the data currently output by the program memory, and extracts the operation code in the instruction data from the data currently output by the program memory as the current operation code;
(2) The decoding unit decodes the current operation code and transmits decoded data corresponding to the current operation code to the bitwise comparison unit;
(3) The bit-by-bit comparison unit compares each bit value in the decoded data corresponding to the current operation code with each bit value in the corresponding system preset data respectively, if the decoded data corresponding to the current operation code is identical to the corresponding system preset data, the bit-by-bit comparison unit judges that the instruction data currently output by the program memory is correct, and returns to the step (1) until the verification of the instruction data output by the program memory is completed; if the decoded data corresponding to the current operation code is not identical to the corresponding system preset data, the bit-by-bit comparison unit judges that the working state of the singlechip is abnormal.
9. The method of claim 8, wherein if the instruction comparing submodule detects that the data currently output by the program memory is any one of a long-call subroutine instruction and a long-jump instruction, the comparison result of the current operation code output by the bitwise comparing unit is not used as a verification result, and the step (1) is returned, otherwise, the comparison result of the current operation code output by the bitwise comparing unit is used as a verification result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911412778.2A CN113127273B (en) | 2019-12-31 | 2019-12-31 | Singlechip detection circuit and corresponding detection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911412778.2A CN113127273B (en) | 2019-12-31 | 2019-12-31 | Singlechip detection circuit and corresponding detection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113127273A CN113127273A (en) | 2021-07-16 |
| CN113127273B true CN113127273B (en) | 2023-07-14 |
Family
ID=76770518
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911412778.2A Active CN113127273B (en) | 2019-12-31 | 2019-12-31 | Singlechip detection circuit and corresponding detection method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113127273B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115967197A (en) * | 2021-10-11 | 2023-04-14 | 华润微集成电路(无锡)有限公司 | Method for realizing communication anti-crosstalk for wireless charging system |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2703310Y (en) * | 2004-05-24 | 2005-06-01 | 肖若冰 | Full-automatic multi-blade collimator blade unit with real-time monitoring and self-protection |
| CN102064836A (en) * | 2010-11-26 | 2011-05-18 | 哈尔滨工业大学深圳研究生院 | Data comparing unit and low density parity check (LDPC) code check node arithmetic circuit |
| CN102541673A (en) * | 2010-12-27 | 2012-07-04 | 北京中电华大电子设计有限责任公司 | Security processing method and circuit for central processing unit (CPU) fetch instruction abnormity |
| CN102567774A (en) * | 2010-12-27 | 2012-07-11 | 北京中电华大电子设计有限责任公司 | Smart card safety protection circuit and smart card safety protection method |
| CN102708013A (en) * | 2011-03-07 | 2012-10-03 | 英飞凌科技股份有限公司 | Program-instruction-controlled instruction flow supervision |
| CN103095409A (en) * | 2013-01-06 | 2013-05-08 | 中国电子科技集团公司第十研究所 | Decoding method for safety control commands of safety command receiver |
| CN107340992A (en) * | 2017-06-15 | 2017-11-10 | 西安微电子技术研究所 | A kind of fixed-point data screening circuit |
| CN109558169A (en) * | 2018-11-28 | 2019-04-02 | 中国电子科技集团公司第四十七研究所 | A kind of microprocessor instruction set on-line reconfiguration method |
| CN110059454A (en) * | 2019-03-29 | 2019-07-26 | 网御安全技术（深圳）有限公司 | Safety encryption, the device of CPU program |
-
2019
- 2019-12-31 CN CN201911412778.2A patent/CN113127273B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2703310Y (en) * | 2004-05-24 | 2005-06-01 | 肖若冰 | Full-automatic multi-blade collimator blade unit with real-time monitoring and self-protection |
| CN102064836A (en) * | 2010-11-26 | 2011-05-18 | 哈尔滨工业大学深圳研究生院 | Data comparing unit and low density parity check (LDPC) code check node arithmetic circuit |
| CN102541673A (en) * | 2010-12-27 | 2012-07-04 | 北京中电华大电子设计有限责任公司 | Security processing method and circuit for central processing unit (CPU) fetch instruction abnormity |
| CN102567774A (en) * | 2010-12-27 | 2012-07-11 | 北京中电华大电子设计有限责任公司 | Smart card safety protection circuit and smart card safety protection method |
| CN102708013A (en) * | 2011-03-07 | 2012-10-03 | 英飞凌科技股份有限公司 | Program-instruction-controlled instruction flow supervision |
| CN103095409A (en) * | 2013-01-06 | 2013-05-08 | 中国电子科技集团公司第十研究所 | Decoding method for safety control commands of safety command receiver |
| CN107340992A (en) * | 2017-06-15 | 2017-11-10 | 西安微电子技术研究所 | A kind of fixed-point data screening circuit |
| CN109558169A (en) * | 2018-11-28 | 2019-04-02 | 中国电子科技集团公司第四十七研究所 | A kind of microprocessor instruction set on-line reconfiguration method |
| CN110059454A (en) * | 2019-03-29 | 2019-07-26 | 网御安全技术（深圳）有限公司 | Safety encryption, the device of CPU program |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113127273A (en) | 2021-07-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5717851A (en) | Breakpoint detection circuit in a data processor and method therefor | |
| CN113127273B (en) | Singlechip detection circuit and corresponding detection method | |
| US8255769B2 (en) | Control apparatus and control method | |
| US10331513B2 (en) | Zero overhead code coverage analysis | |
| US20180135224A1 (en) | Washing machine failure detection and processing method | |
| US5440604A (en) | Counter malfunction detection using prior, current and predicted parity | |
| US20220198005A1 (en) | Method for detecting reverse engineering on a processor using an instruction pointer and corresponding integrated circuit | |
| CN112199642A (en) | Detection method for anti-debugging of android system, mobile terminal and storage medium | |
| US5404499A (en) | Semi-automatic program execution error detection | |
| CN105718375A (en) | Restorability testing method of embedded system | |
| US20200174875A1 (en) | Secure forking of error telemetry data to independent processing units | |
| CN105718326A (en) | Restorability testing method of embedded system | |
| CN112231710B (en) | QNX BSP starting verification method and starting verification module | |
| CN117155209A (en) | Digital signal processing unit and motor control equipment | |
| EP0525672A2 (en) | Microprocessor with program tracing | |
| JP2002175198A (en) | Arithmetic processor, and debugging method and debugging system for the arithmetic processor | |
| CN115061842A (en) | Data processing method, device, equipment and storage medium | |
| JP2743562B2 (en) | Failure handling method | |
| US20080195896A1 (en) | Apparratus and method for universal programmable error detection and real time error detection | |
| CN117055533A (en) | Vehicle-mounted system fault processing method, device, equipment and medium | |
| CN117472657A (en) | Error repairing method, device, equipment and storage medium | |
| CN117631656A (en) | Method and device for analyzing potential faults of motor controller and electronic equipment | |
| JPS6051141B2 (en) | Program runaway detection method | |
| KR960018893A (en) | Controller with Watchdog Timer | |
| CN115201669A (en) | Chip internal circuit detection method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |