CN113113353B - Preparation process of array substrate, array substrate and display device - Google Patents
Preparation process of array substrate, array substrate and display device Download PDFInfo
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- CN113113353B CN113113353B CN202110391099.2A CN202110391099A CN113113353B CN 113113353 B CN113113353 B CN 113113353B CN 202110391099 A CN202110391099 A CN 202110391099A CN 113113353 B CN113113353 B CN 113113353B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The application relates to the technical field of display, in particular to a preparation process of an array substrate, the array substrate and a display device. The preparation process of the array substrate comprises the following steps: wet etching is carried out on the first film layer to form a first blind hole; forming a second film layer on one side of the first film layer, wherein the second film layer covers the first blind holes; wet etching is carried out on the second film layer at the position aligned with the first blind hole, so that a second blind hole is formed; and carrying out dry etching on the second blind hole to form a via hole penetrating through the first film layer and the second film layer. According to the application, through step wet etching, the first blind holes which do not penetrate through the first film layer are formed by wet etching on the first film layer in the first step, the second blind holes are completely covered by the second film layer only on the second film layer in the second step, the interface between the second film layer and the first film layer can be closed by the second film layer after the second wet etching, and etching liquid is prevented from entering the interface from the transverse direction for drilling, so that etching cracks are avoided.
Description
Technical Field
The application relates to the technical field of display, in particular to a preparation process of an array substrate, the array substrate and a display device.
Background
In the related art, top gate TFTs (Thin Film Transistor, thin film transistors) are widely used, and are attracting attention. The top gate TFT mainly comprises the following preparation processes: and sequentially depositing a shading layer, a buffer layer, an active layer, a grid insulating layer and a grid on the substrate, wherein in the preparation process, a dry etching process is required to prepare a via hole penetrating through the interlayer dielectric layer and the buffer layer.
The larger and larger display panels require a sufficiently narrow metal trace to reduce propagation Delay (RC Delay) and increase aperture ratio. However, since the gate layer and the source drain layer of the top gate TFT are thicker, the interlayer dielectric layer and the like which need to be covered on the top gate TFT are thicker, and the via hole which needs to be etched and punched is deeper, so that the dry etching time is longer, the damage rate of the photoresist is faster due to the dry etching process, the current process reaches the equipment limit, and as the hole depth of the interlayer dielectric layer to be etched is further increased, the conventional dry etching process cannot be adopted for punching.
Based on the technical problems, the prior art considers that etching liquid is adopted for wet etching, but in the wet etching process, as the compactness of the buffer layer is higher and the interlayer dielectric layer is arranged on the active layer, the compactness of the buffer layer is lower, so that the film quality difference between the buffer layer and the interlayer dielectric layer is larger, and the etching liquid is easy to transversely drill and etch to the junction of the buffer layer and the interlayer dielectric layer, and etching cracks appear.
Disclosure of Invention
In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to solve the technical problem that etching cracks can occur when wet etching is adopted in the prior art, the application provides a preparation process of an array substrate, the array substrate and a display device, wherein the preparation process is used for avoiding etching cracks at the boundary of a film layer.
In order to achieve the aim of the application, the application adopts the following technical scheme:
according to a first aspect of an embodiment of the present application, there is provided a preparation process of an array substrate, including the steps of:
wet etching is carried out on the first film layer to form a first blind hole;
forming a second film layer on one side of the first film layer, wherein the second film layer covers the first blind hole;
wet etching is carried out on the second film layer at the position aligned with the first blind hole, so that a second blind hole is formed;
and carrying out dry etching on the bottom of the second blind hole to form a via hole penetrating through the first film layer and the second film layer.
In one embodiment, in the step of wet etching the second film layer at the position of aligning the first blind hole, the method further includes: and carrying out wet etching on the second film layer at the position aligned with the first blind hole to form the second blind hole penetrating or not penetrating through the second film layer.
In one embodiment, in the step of dry etching the bottom of the second blind hole, the method further includes: and carrying out dry etching on the first film layer at the bottom of the first blind hole, or simultaneously carrying out dry etching on the first film layer at the bottom of the first blind hole and the second film layer at the bottom of the second blind hole.
In one embodiment, before the wet etching step is performed on the first film layer, the method further includes the following steps:
forming a light shielding layer on a substrate;
forming the first film layer on one side of the shading layer, which is away from the substrate base plate;
in one embodiment, in the step of performing wet etching on the first film layer, the method further includes: wet etching is carried out on one side, away from the shading layer, of the first film layer, so that the first blind holes are formed.
In one embodiment, before the step of forming the second film layer on the side where the first film layer is etched, the method further includes the steps of:
forming an active layer isolated from the first blind hole on one side of the first film layer subjected to etching;
and forming the second film layer on the active layer, the first blind holes and the first film layer together.
In one embodiment, in the step of wet etching the first film layer, the method further includes: and coating photoresist on the first film layer, forming a mask with a first etching hole on the photoresist, and performing wet etching at the first etching hole.
In one embodiment, in the step of forming the second film layer on the side where the first film layer is etched, the method further includes: and forming the second film layer by filling inorganic matters on one side of the first film layer to be etched.
In one embodiment, in the step of wet etching the second film layer at the position of aligning the first blind hole, the method further includes: and coating photoresist on the second film layer aligned with the first blind hole, forming a mask with a second etching hole on the photoresist, and performing wet etching at the second etching hole.
According to a second aspect of the embodiment of the present application, there is provided an array substrate, which is prepared by using the preparation process of the array substrate of any one of the above embodiments, and the array substrate includes:
the first film layer is provided with a first blind hole;
the second membrane layer is positioned on one side of the first membrane layer where the first blind hole is formed, the second membrane layer covers the first blind hole, the second membrane layer aligned with the first blind hole is formed with a second blind hole, and the bottom of the second blind hole is provided with a through hole penetrating through the first membrane layer and the second membrane layer.
According to an embodiment of the application, the first film layer and the second film layer are each formed by depositing silicon oxide.
According to an embodiment of the present application, the first film layer is a buffer layer, and the second film layer is an interlayer dielectric layer.
According toIn one embodiment of the present application, the depth of the first blind hole is d 1 The thickness of the first film layer at the wet etching position is D 1 The method comprises the steps of carrying out a first treatment on the surface of the Wherein d 1 ＜D 1 。
According to an embodiment of the present application, the depth of the second blind hole is d 2 The thickness of the second film layer at the wet etching position is D 2 The method comprises the steps of carrying out a first treatment on the surface of the Wherein d 2 ≤D 2 。
According to one embodiment of the present application, the depth of the via hole is d 3 The sum of the thicknesses of the first film layer and the second film layer at the wet etching position is D 3 The method comprises the steps of carrying out a first treatment on the surface of the Wherein d 3 ＝D 3 。
According to a third aspect of the embodiments of the present application, a display device includes the array substrate according to any one of the embodiments.
As can be seen from the above technical solutions, the preparation process of the array substrate, the array substrate and the display device of the present application have the following advantages and positive effects:
according to the embodiment of the application, the first blind holes formed by step wet etching, namely the first wet etching is only aimed at the first film layer, are not penetrated through the first film layer, so that etching liquid is only etched in the first film layer and cannot occur at the boundary of the film layers, the second wet etching is only aimed at the second film layer, the second film layer completely covers the first blind holes, so that the second blind holes formed by the second film layer after etching can also cover the first blind holes, namely the interface between the second film layer and the first film layer can be closed by the second film layer after the second wet etching, the etching liquid is prevented from entering the interface from the transverse direction, etching cracks are avoided at the boundary of the film layers, and finally, through-holes are formed at the residual parts of the dry etching, thereby improving the yield of products and improving the performance of the products.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIGS. 1 (a) -1 (d) are schematic views of intermediate structures produced during a fabrication process of a prior art array substrate;
FIG. 2 is a scanning electron microscope image of a crack generated in a preparation process of an array substrate in the prior art;
fig. 3 is a process flow diagram illustrating a fabrication process of an array substrate according to an exemplary embodiment;
fig. 4 (a) -4 (e) are schematic views illustrating intermediate structures generated during a manufacturing process of an array substrate according to an exemplary embodiment.
Wherein reference numerals are as follows:
1. a light shielding layer; 2. a first film layer; 21. a first blind hole; 3. a second film layer; 31. a second blind hole; 4. an active layer; 5. a via hole; 6. a substrate.
Detailed Description
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
In order to more clearly illustrate the embodiments of the application or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
In the related art, the size of the display panel is larger and the resolution is higher, which requires the metal wiring to be narrow enough to reduce the propagation delay and increase the aperture ratio. However, since the gate layer and the source drain layer of the top gate TFT are thicker, the interlayer dielectric layer and the like which need to be covered on the top gate TFT are thicker, and the via holes which need to be etched and punched are deeper, so that the dry etching time is longer, the damage rate of the photoresist is faster due to the dry etching process, the current process reaches the equipment limit, and as the hole depth of the interlayer dielectric layer to be etched is further increased, the conventional dry etching process cannot be adopted for punching.
Based on the technical problems, the prior art considers that etching liquid is adopted for wet etching, but because an active layer needs to be formed on a buffer layer, an interlayer dielectric layer is formed on the active layer, so that the compactness of the buffer layer is higher, the compactness of the interlayer dielectric layer is lower, the film quality difference between the buffer layer and the interlayer dielectric layer is larger, the conventional etching liquid is used for etching the junction of the buffer layer and the interlayer dielectric layer, transverse drilling is easy to occur, and etching cracks appear.
Fig. 1 (a) -1 (d) are schematic diagrams of intermediate structures generated during a preparation process of an array substrate in the prior art, fig. 2 is a scanning electron microscope image of cracks generated during the preparation process of the array substrate in the prior art, as can be seen in fig. 1 (a) -1 (d) and fig. 2, the array substrate includes a substrate 6, a Light shielding layer 1 (i.e. Light shield), a Buffer layer 2 (i.e. Buffer), an active layer 4 (i.e. Act) and an interlayer dielectric layer 3 (i.e. Buffer or an inorganic layer) which are sequentially arranged, first blind holes 21 which do not penetrate through the interlayer dielectric layer 3 are formed on the interlayer dielectric layer 3 through etching liquid, then second blind holes 31 which penetrate through the interlayer dielectric layer 3 and the Buffer layer 2 are formed through the interlayer dielectric layer 3 and the Buffer layer 2 simultaneously through etching liquid, finally, through holes 5 penetrating through the interlayer dielectric layer 3 and the Buffer layer 2 are formed through dry etching the bottoms of the second blind holes 31, and in the second wet etching process, etching liquid enters the interlayer dielectric layer 3 and the Buffer layer 2 in the transverse direction, and then both sides of the film layer are formed at the boundary of the two sides of the interlayer dielectric layer and the Buffer layer 2 through wet etching.
Based on the consideration of the above problems, the embodiment of the application provides a preparation process of an array substrate, which comprises the following steps:
wet etching is carried out on the first film layer to form a first blind hole;
forming a second film layer on one side of the first film layer, wherein the second film layer covers the first blind holes;
wet etching is carried out on the second film layer at the position aligned with the first blind hole, so that a second blind hole is formed;
and carrying out dry etching on the bottom of the second blind hole to form a via hole penetrating through the first film layer and the second film layer.
It is known to those skilled in the art that in the step of wet etching the second film layer at the position of aligning the first blind hole, the formed second blind hole has two forms, the first form penetrates through the second film layer, the second form does not penetrate through the second film layer but does not etch the first film layer, and the two forms can ensure that etching liquid does not enter the junction of the first film layer and the second film layer. In the first mode, after penetrating the second film layer, exposing the hole bottom of the first blind hole, wherein the thickness of the hole bottom, namely the thickness of the first film layer at the hole bottom, is about 1000 meter, but the second film layer still surrounds the junction of the second film layer and the first film layer, so that the junction is prevented from being transversely etched; most preferably, in the second mode, a mode of not penetrating through the second film layer is adopted, so that the second film layer with the thickness of 500 m and the first film layer with the thickness of 500 m can be left (the above values are illustrative, only the first film layer and the second film layer with the thickness of about 1000 m are needed to be left finally, so that the dry etching time is shorter), and the etching liquid cannot enter the first film layer during the second wet etching, so that a better effect of preventing cracks is achieved.
For a more specific understanding of the technical idea of the present application, the following description of exemplary embodiments is given with reference to the accompanying drawings:
fig. 3 is a process flow diagram illustrating a process for manufacturing an array substrate according to an exemplary embodiment, and fig. 4 (a) -4 (e) are schematic views illustrating intermediate structures generated during the process for manufacturing an array substrate according to an exemplary embodiment, and as can be seen in fig. 3 and fig. 4 (a) -4 (e), an embodiment of the present application provides a process for manufacturing an array substrate, including the steps of:
s001, as shown in fig. 4 (a) -4 (b), wet etching is carried out on the first film layer 2 to form a first blind hole 21;
s002, as shown in FIG. 4 (c), forming a second film layer 3 on the side where the first film layer 2 is etched, wherein the second film layer 3 covers the first blind holes 21;
s003, as shown in fig. 4 (d), wet etching is performed on the second film layer 3 at the position of aligning the first blind holes 21 to form second blind holes 31;
as shown in fig. 4 (e), the bottom of the second blind hole 31 is dry etched to form a via hole 5 penetrating the first film layer 2 and the second film layer 3.
According to the embodiment of the application, through step wet etching, namely, the first step wet etching is only performed on the first film layer 2, as shown in fig. 4 (a) -4 (b), the formed first blind hole 21 does not penetrate through the first film layer 2, and other layers are not formed in the step, so that etching liquid only etches in the first film layer 2, and does not occur at the interface of the film layers, the second step wet etching is only performed on the second film layer 3, as shown in fig. 4 (c) -4 (d), the second film layer 3 completely covers the first blind hole 21, and as the direction of wet etching is the direction perpendicular to each layer, the formed second blind hole 31 only after the second film layer 3 is used for covering the first blind hole 21, namely, the second film layer 3 after the second etching can completely seal the interface between the second film layer 3 and the first film layer 2, so that etching liquid is prevented from entering the interface in the transverse direction, etching cracks are avoided, and finally, through holes 5 are formed at the interface of the dry etching residues, the product is improved, and the product quality is improved.
Before the step S001, the method further comprises the following steps: first, a light shielding layer 1 is formed on a substrate 6, specifically, the light shielding layer 1 is formed by depositing an insulating material or a conductive material on the substrate 6 and patterning, and then the first film layer 2 is formed on a side of the light shielding layer 1 facing away from the substrate 6.
In step S001, specifically, wet etching is performed on a side of the first film layer 2 facing away from the light shielding layer 1, so as to form a first blind hole 21 that does not penetrate through the first film layer 2. In addition, the wet etching in the step is specifically to smear photoresist on the first film layer 2, form a mask with a first etching hole on the photoresist, and set a light source, when the light source irradiates, the first film layer 2 covered with the mask is not etched by etching liquid, and only the first etching hole is etched by the wet etching liquid, so that the accuracy of the wet etching is improved.
In step S002, the method further comprises the steps of: an active layer 4 isolated from the first blind holes 21 is formed on one side of the first film layer 2, a gate insulating layer and a gate are sequentially formed on one side of the active layer 4 away from the first film layer 2, and a second film layer 3 is formed on the active layer 4, the gate insulating layer, the gate, the first blind holes 21 and the first film layer 2 together through filling of inorganic matters.
Specifically, a semiconductor material is deposited on the first film layer 2 and patterned to form an active layer 4, and a gate insulating layer and a gate electrode are sequentially formed on the active layer 4, specifically, a whole gate insulating layer and a whole metal layer may be sequentially formed on the active layer 4, where the metal layer is used to prepare a gate electrode, and then, patterning is performed on the whole gate insulating layer and the whole metal layer to obtain the gate insulating layer and the gate electrode.
In addition, the active layer 4 may be further subjected to a conductive treatment (i.e. depositing a conductive material and patterning) by using a self-aligned process, so that the active layer 4 is divided into an active region, a first conductive region and a second conductive region, where the first conductive region and the second conductive region are located at two sides of the active region and isolated from the first blind hole 21, the first conductive region may be a source region, the second conductive region may be a drain region, and the active region is located in the projection of the gate insulating layer on the active layer 4.
It should be understood by those skilled in the art that the active layer 4 is isolated from the first blind via 21, and the second blind via 31 and the via 5 are isolated from the active layer 4 because the wet etching and the dry etching are performed in a direction perpendicular to each layer.
In step S003, further comprising: the second film layer 3 is wet etched at the position aligned with the first blind hole 21 to form a second blind hole 31 penetrating or not penetrating the second film layer 3, and no matter whether the second blind hole 31 penetrates the second film layer 3 or not, the etching liquid is only located in the second film layer 3 and cannot enter the first film layer 2. Preferably, the second blind hole 31 may not completely penetrate through the second film layer 3, so that etching liquid can be better prevented from entering a film layer interface between the second film layer 3 and the first film layer 2, etching cracks are prevented from being generated, and the product yield is improved. Specifically, the wet etching in this step is to smear photoresist on the second film layer 3 aligned to the first blind hole 21, form a mask with a second etching hole on the photoresist, and set a light source, when the light source irradiates, the second film layer 3 covered with the mask will not be etched by the etching liquid, and only the second etching hole is etched by the wet etching, thereby improving the accuracy of the wet etching.
In step S004, two ways are also included: one is that the second blind hole 31 penetrates through the second film layer 3, only the first film layer 2 at the bottom of the first blind hole 21 needs to be subjected to dry etching, and the second is that the second blind hole 31 does not penetrate through the second film layer 3, then the first film layer 2 at the bottom of the first blind hole 21 and the second film layer 3 at the bottom of the second blind hole 31 need to be subjected to dry etching, and the thickness of the rest of the film layers needs to be subjected to dry etching is about 1000 Emeter, and the depth of the through hole 5 needed to be etched and penetrated is shallow, so that the needed dry etching time is short, the damage rate of photoresist is slow, and therefore the product quality and the product yield can be improved.
Wherein, for the etching liquid, the main component is Hydrogen Fluoride (HF), and ammonium fluoride (NH) 4 F) And a surfactant, wherein the mass fraction (wt) of hydrogen fluoride is 2% -5%, the mass fraction of ammonium fluoride is 20% -40%, and the mass fraction of the surfactant is 1% -5%. For example, the mass fraction (wt) of hydrogen fluoride is 2%, 3.5% or 5%, the mass fraction of ammonium fluoride is 20%, 30% or 40%, and the mass fraction of surfactant is 1%, 3% or 5%.
According to a second aspect of the embodiment of the present application, there is provided an array substrate including a substrate 6, a light shielding layer 1, a first film layer 2, an active layer 4, and a second film layer 3; the light shielding layer 1 is formed on one side of the substrate 6 and does not completely cover the substrate 6, the active layer 4 is arranged on one side of the first film layer 2 away from the substrate 6 and does not completely cover the first film layer 2, and the second film layer 3 completely covers the active layer 4 and one side of the first film layer 2 away from the substrate 6; the first film layer 2 is etched by wet method to form a first blind hole 21 which does not penetrate through the first film layer 2, the second film layer 3 covers the first blind hole 21, that is, the second film layer 3 is partially located in the first blind hole 21, and then a second blind hole 31 is formed by wet method etching for the second film layer 3 aligned with the first blind hole 21, the second blind hole 31 may penetrate or not penetrate through the second film layer 3, and a via hole 5 penetrating through the first film layer 2 and the second film layer 3 is formed at the bottom of the second blind hole 31 by dry method etching.
Wherein, it is understood by those skilled in the art that the first film layer 2 is a buffer layer, and the second film layer 3 is an interlayer dielectric layer.
For the depth of the first blind hole 21, since the first blind hole 21 does not penetrate the first film layer 2, its hole depth should be smaller than the thickness of the first film layer 2 at the corresponding wet etching, i.e. the depth of the first blind hole 21 is d 1 The thickness of the first film layer 2 at the wet etching position is D 1 The method comprises the steps of carrying out a first treatment on the surface of the Wherein d 1 ＜D 1 。
For the depth of the second blind hole 31, since the second blind hole 31 has two forms, one penetrates the second film layer 3 but does not enter the first film layer 2, and the other does not penetrate the second film layer 3, the depth of the second blind hole 31 should be smaller than or equal to the thickness of the second film layer 3 corresponding to the wet etching, i.e. the depth of the second blind hole 31 is d 2 The thickness of the second film layer 3 at the wet etching position is D 2 The method comprises the steps of carrying out a first treatment on the surface of the Wherein d 2 ≤D 2 。
For the depth of the via hole 5, since the via hole 5 needs to penetrate through the second film layer 3 and the first film layer 2 at the same time and the etching does not involve the light shielding layer 1, the hole depth of the via hole 5 should be the same as the sum of the thicknesses of the second film layer 3 and the first film layer 2 at the corresponding wet etching, i.e. the depth of the via hole 5 is d 3 The sum of the thicknesses of the first film layer 2 and the second film layer 3 at the wet etching position is D 3 The method comprises the steps of carrying out a first treatment on the surface of the Wherein d 3 ＝D 3 。
For the first blind hole 21, the second blind hole 31 and the via hole 5, the first blind hole 21 comprises a first side wall, the second blind hole 31 comprises a second side wall, and the via hole 5 comprises a third side wall, wherein the projection of the second side wall on the first film layer 2 falls into the projection of the first side wall on the first film layer 2, and the projection of the third side wall on the first film layer 2 falls into the projection of the second side wall on the first film layer 2. The included angle between the first side wall and the first film layer 2 is alpha, the included angle between the second side wall and the first film layer 2 is beta, the included angle between the third side wall and the first film layer is gamma, alpha is less than or equal to beta is less than or equal to gamma, and the first blind hole 21, the second blind hole 31 and the through hole 5 are all in a gradually-reduced structure from top to bottom, namely, the first blind hole 21, the second blind hole 31 and the through hole 5 are steeper and steeper.
For each layer of the array substrate, the light shielding layer 1 may be made of an insulating material or a conductive material, the insulating material may be black opaque resin, and the conductive material may be a metal or an alloy material, such as aluminum, silver, magnesium-silver alloy, etc.; the first film layer 2 and the second film layer 3 are made of silicon oxide, have good compactness and can play a good role in blocking water and oxygen; the material of the active layer 4 may be a semiconductor material, such as low-temperature polysilicon, IGZO (indium gallium zinc oxide), etc., and when the array substrate is used for a large-sized display panel, the material of the active layer 4 is usually IGZO, so as to ensure better uniformity of the active layer 4.
According to a third aspect of the embodiment of the present application, a display device includes the array substrate of any one of the above embodiments, and further includes a display module.
It should be understood that the display device in this embodiment may be: electronic paper, electronic book, mobile phone, tablet computer, television, notebook computer, desktop computer, digital camera, digital photo frame, navigator, and any other product or component with display function.
The forming process adopted in the above procedure may include, for example: film forming process such as deposition and sputtering, and patterning process such as etching.
It should be noted that in the description and claims of the present application and in the above figures, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order of such entities or actions. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the application described herein may be capable of being practiced otherwise than as specifically illustrated and described.
Moreover, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Spatially relative terms, such as "above … …," "above … …," "upper surface at … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial location relative to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the exemplary term "above … …" may include both orientations of "above … …" and "below … …". The device may also be positioned in other different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The foregoing is only a specific embodiment of the application to enable those skilled in the art to understand or practice the application. Many modifications and variations to these embodiments will be apparent to those skilled in the art that the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (15)
1. The preparation process of the array substrate is characterized by comprising the following steps of:
wet etching is carried out on the first film layer (2) to form a first blind hole (21);
forming a second film layer (3) on one side of the first film layer (2) which is etched, wherein the second film layer (3) covers the first blind holes (21);
wet etching is carried out on the second film layer (3) at the position of aligning the first blind holes (21) to form second blind holes (31);
and carrying out dry etching on the bottom of the second blind hole (31) to form a via hole (5) penetrating through the first film layer (2) and the second film layer (3).
2. The process for manufacturing an array substrate according to claim 1, wherein in the step of wet etching the second film layer (3) at the position of aligning the first blind hole (21), the process further comprises:
and carrying out wet etching on the second film layer (3) at the position aligned with the first blind holes (21) to form the second blind holes (31) penetrating or not penetrating the second film layer (3).
3. The process for manufacturing an array substrate according to claim 2, wherein in the step of dry etching the bottom of the second blind hole (31), further comprising:
and carrying out dry etching on the first film layer (2) at the bottom of the first blind hole (21), or simultaneously carrying out dry etching on the first film layer (2) at the bottom of the first blind hole (21) and the second film layer (3) at the bottom of the second blind hole (31).
4. The process for preparing an array substrate according to claim 1, further comprising the step of, before the step of wet etching the first film layer (2):
forming a light shielding layer (1) on a substrate (6);
and forming the first film layer (2) on one side of the shading layer (1) away from the substrate (6).
5. The process for preparing an array substrate according to claim 4, wherein in the step of wet etching the first film layer (2), further comprising:
wet etching is carried out on one side, away from the shading layer (1), of the first film layer (2) to form the first blind hole (21).
6. The process for preparing an array substrate according to claim 1, further comprising the step of, before the step of forming the second film layer (3) on the side where the first film layer (2) is etched:
forming an active layer (4) isolated from the first blind hole (21) on one side of the first film layer (2) subjected to etching;
the second film layer (3) is formed on the active layer (4), the first blind holes (21) and the first film layer (2) together.
7. The process for preparing an array substrate according to claim 1, wherein in the step of wet etching the first film layer (2), the process further comprises:
and coating photoresist on the first film layer (2), forming a mask with a first etching hole on the photoresist, and performing wet etching at the first etching hole.
8. The process for manufacturing an array substrate according to claim 1, wherein in the step of forming the second film layer (3) on the side where the first film layer (2) is etched, further comprising:
and forming the second film layer (3) by filling inorganic matters on one side of the first film layer (2) subjected to etching.
9. The process for manufacturing an array substrate according to claim 1, wherein in the step of wet etching the second film layer (3) at the position of aligning the first blind hole (21), the process further comprises:
and coating photoresist on the second film layer (3) aligned with the first blind holes (21), forming a mask with second etching holes on the photoresist, and performing wet etching at the second etching holes.
10. An array substrate, characterized in that the array substrate is prepared by adopting the preparation process of the array substrate as claimed in any one of claims 1 to 9, and the array substrate comprises:
the first film layer (2) is provided with the first blind holes (21);
the second membrane layer (3) is located one side of first blind hole (21) is seted up to first membrane layer (2), second membrane layer (3) cover first blind hole (21), and aligns second membrane layer (3) of first blind hole (21) department are seted up second blind hole (31), through first membrane layer (2) with via hole (5) of second membrane layer (3) are seted up to the bottom of second blind hole (31).
11. The array substrate according to claim 10, wherein the first film layer (2) is a buffer layer, and the second film layer (3) is an interlayer dielectric layer.
12. The array substrate according to claim 10, wherein the depth of the first blind hole (21) is D1, and the thickness of the first film layer (2) at the wet etching is D1; wherein D1 < D1.
13. The array substrate according to claim 10, wherein the depth of the second blind hole (31) is D2, and the thickness of the second film layer (3) at the wet etching is D2; wherein D2 is less than or equal to D2.
14. The array substrate according to claim 10, wherein the depth of the via hole (5) is D3, and the sum of the thicknesses of the first film layer (2) and the second film layer (3) at the wet etching is D3; wherein d3=d3.
15. A display device comprising an array substrate according to any one of claims 10 to 14.
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