CN113110821B - Delay configurable asynchronous FIFO circuit - Google Patents

Delay configurable asynchronous FIFO circuit Download PDF

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CN113110821B
CN113110821B CN202110420079.3A CN202110420079A CN113110821B CN 113110821 B CN113110821 B CN 113110821B CN 202110420079 A CN202110420079 A CN 202110420079A CN 113110821 B CN113110821 B CN 113110821B
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薛颜
万书芹
陈婷婷
邵杰
王俊杰
蔡国文
任凤霞
盛炜
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CETC 58 Research Institute
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    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory

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Abstract

The invention discloses an asynchronous FIFO circuit with configurable delay, which belongs to the field of integrated circuits and comprises integer delay and decimal delay. The maximum allowable value of the FIFO fractional delay is determined by the interpolation multiple of the digital up-conversion, and the maximum allowable value of the FIFO integer delay is determined by the number of FIFO storage units. And judging the phase relation of the read-write clock according to a sampling clock which has the same frequency as the read clock and has fixed offset between phases as a DAC clock period as a scale to obtain FIFO fractional delay, wherein the minimum unit is the period of input data divided by an interpolation ratio. The FIFO integer delay is obtained by comparing the state difference between the read and write pointers, the smallest unit of which is the write clock cycle. On this basis, the delay of the FIFO is configured to reach the target timing margin. The invention can set different FIFO delay values to configure the delay of the data to be suitable for different application environment requirements. The configuration range is 1 DAC clock cycle to (2n-1) write clock cycle plus (m-1) DAC clock cycle. And m and n are valued according to specific design requirements.

Description

Delay configurable asynchronous FIFO circuit
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an asynchronous FIFO circuit with configurable delay, which is applied to a digital up-conversion system.
Background
The digital up-conversion technique is a technique for increasing the sampling rate of data by shifting a baseband signal to an intermediate frequency signal and converting the baseband signal into an analog signal through a digital-to-analog converter for output. The digital up-conversion circuit realized by adopting the technology has the characteristics that: the programmable frequency hopping antenna has the advantages of high programmability, high frequency hopping speed, high resolution, high frequency modulation precision and the like, thereby becoming one of the main technologies in the current frequency synthesis technology and being widely applied to the communication fields of mobile communication, military and commercial radar systems and the like.
The digital up-conversion circuit needs to transmit signals with an FPGA or other circuits in application, an additional interface circuit is needed in chip design, and high-speed signals are converted into low-speed signals to be processed by the up-conversion circuit conveniently. The working clocks of the interface circuit and the digital up-conversion circuit are in two different clock domains, the two clock domains are often not synchronous, and an additional clock synchronization circuit is needed to adjust the time sequence to correctly transmit data. The asynchronous FIFO structure is a commonly used clock synchronization circuit, but generally the asynchronous FIFO can only synchronize data with a write clock period whose delay amount is within the FIFO depth, and cannot synchronize when the deviation between the read and write clocks is less than one write clock period, and cannot be configured after the synchronous delay amount is set. For a digital up-conversion circuit, a low-frequency signal is generally made into a high-frequency signal, a clock of a DAC is often faster than a clock of an interface, and a phase deviation between a clock period of the DAC and a read-write clock has a corresponding multiple relation.
Therefore, there is a need for a delay configurable asynchronous FIFO circuit that can synchronize at least one DAC clock cycle and at most the timing difference of the same write clock cycle as the depth of the FIFO circuit, and is also suitable for applications requiring synchronous and non-fixed delay.
Disclosure of Invention
The invention aims to provide an asynchronous FIFO circuit with configurable delay, which solves the problems in the prior art.
In order to solve the technical problem, the invention provides an asynchronous FIFO circuit with configurable delay, which comprises a storage module, an FIFO read-write control module, an FIFO delay calculation module and an FIFO delay configuration module;
the storage module provides corresponding storage space for data according to the indication of the control signal, when the FIFO writing rate is the same as the FIFO reading rate, the size of the real-time occupied storage space is kept unchanged, and when the effective edge of the clock arrives, data of one unit is written into or read from the storage module;
the FIFO read-write control module is used for generating a read-write address, a read-write pointer and a synchronous read-write pointer of the FIFO, and generating an FIFO full-empty identifier to be fed back to the system to ensure correct data transmission;
the FIFO delay calculation module calculates the current FIFO delay according to the phase relation between a read-write pointer and a write clock provided by an external FPGA (field programmable gate array) and a read clock provided by the asynchronous FIFO circuit, and feeds back the current delay value to a register to be read by the SPI;
the FIFO delay configuration module can configure a delay value required to be set by the SPI, extract the newly configured delay value, compare the newly configured delay value with a real-time delay value, adjust according to a comparison result, and configure the delay of the FIFO to the set value.
Optionally, the storage module is a dual-port RAM, and the FIFO depth is 2nIn total, 2nA plurality of memory cells, n being a positive integer; reading two memory cell data in one reading clock period, and dividing the data into odd and even paths, wherein the reading and writing clock of the asynchronous FIFO circuit has the frequency relation according to the requirement of an external circuit: f. ofwclk＝2frclk，fwclkFor writing clock frequency, frclkFor read clock frequency, data is written from one channel and read from two channels.
Optionally, the bit width of the read-write address of the FIFO read-write control module is n, and the range is 0-2n-1, 2 in FIFOnA plurality of memory cells; the bit width of the read-write pointer is n +1, and the read-write pointer consists of a read-write address and a most significant bit in a range of 0-2n+1-1, representing the read and write pointers traversing the FIFO twice.
Optionally, the method for judging the empty and full states of the FIFO read-write control module is as follows: comparing the read pointer with a write pointer synchronized to a read clock domain, and if the read pointer and the write pointer are equal, judging that the read pointer is empty; and comparing the write pointer with the read pointer synchronized to the write clock domain, and if the highest bits of the write pointer and the read pointer are opposite and the rest bits are equal, judging that the write pointer is full.
Optionally, the method for calculating fractional delay by the FIFO delay calculation module includes: determining the clock period of the DAC with the decimal delay range of 0-m-1 according to different interpolation multiples m, then sampling the write clock by using m/2 sampling clocks with the same frequency as the read clock, and determining the phase difference between the write clock and the read clock; where m/2 sample clocks are offset by one DAC clock cycle in sequence and the read clock is in phase with the first sample clock, where m is 2, 4, 8, 16 … ….
Optionally, the method for calculating the integer delay by the FIFO delay calculation module includes: and synchronizing the writing pointer in the form of the Gray code by using a read clock, synchronizing the writing pointer to a read clock domain, and obtaining the difference value between the synchronized writing pointer and the synchronous read pointer as the integer delay.
Optionally, the FIFO delay configuration module configures fractional delay by adjusting a phase of a read clock: and subtracting the current real-time decimal delay value from the newly configured delay value to obtain the variation which is the DAC clock period needing to be delayed by the read clock, so that the phase difference between the write clock and the read clock is changed.
Optionally, the setting of the integer delay by the FIFO delay configuration module is implemented by changing a value of a read pointer: firstly, judging whether the decimal delay preset value minus the current decimal delay is positive or negative, and if the result is positive, changing a read pointer into a write pointer of a synchronous read clock domain minus a preset value of integer delay; the result is negative, the read pointer becomes the write pointer synchronized to the read clock domain minus the preset value of the integer delay plus 1, thereby changing the difference between the write pointer and the read pointer.
The configurable delay asynchronous FIFO circuit provided by the invention comprises integer delay and decimal delay. The maximum allowable value of the FIFO fractional delay is determined by the interpolation multiple of the digital up-conversion, and the maximum allowable value of the FIFO integer delay is determined by the number of FIFO storage units. And judging the phase relation of the read-write clock according to a sampling clock which has the same frequency as the read clock and has fixed offset between phases as a DAC clock period as a scale to obtain FIFO fractional delay, wherein the minimum unit is the period of input data divided by an interpolation ratio. The FIFO integer delay is obtained by comparing the state difference between the read and write pointers, the smallest unit of which is the write clock cycle. On this basis, the delay of the FIFO is configured to reach the target timing margin. The invention can set different FIFO delay values to configure the delay of the data to be suitable for different application environment requirements. The configuration range is 1 DAC clock cycle to (2n-1) write clock cycle plus (m-1) DAC clock cycle. And m and n are variable quantities and are selected according to specific design requirements.
Drawings
FIG. 1 is a block diagram of an asynchronous FIFO circuit with configurable delay according to the present invention;
FIG. 2 is a schematic diagram of the relationship between the read/write clock and the sampling clock under the 8-fold interpolation condition;
FIG. 3 is a functional block diagram of a FIFO fractional delay design;
FIG. 4 is a functional block diagram of a FIFO integer delay design;
fig. 5 is a FIFO read pointer change flow diagram.
Detailed Description
The following describes a delay configurable asynchronous FIFO circuit according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides an asynchronous FIFO circuit with configurable delay, which has a structure shown in figure 1 and comprises a storage module 1, an FIFO read-write control module 2, an FIFO delay calculation module 3 and an FIFO delay configuration module 4.
The storage module provides corresponding storage space for data according to the indication of the control signal, when the FIFO writing rate is the same as the FIFO reading rate, the size of the real-time occupied storage space is kept unchanged, and when the effective edge of the clock arrives, data of one unit is written into or read from the storage module;
the FIFO read-write control module is used for generating a read-write address, a read-write pointer and a synchronous read-write pointer of the FIFO, and generating an FIFO full-empty identifier to be fed back to the system to ensure correct data transmission;
the FIFO delay calculation module calculates the current FIFO delay according to the phase relation between a read-write pointer and a write clock provided by an external FPGA (field programmable gate array) and a read clock provided by the asynchronous FIFO circuit, and feeds back the current delay value to a register to be read by the SPI;
the FIFO delay configuration module can configure a delay value required to be set by the SPI, extract the newly configured delay value, compare the newly configured delay value with a real-time delay value, adjust according to a comparison result, and configure the delay of the FIFO to the set value.
The storage module is a double-end RAM with FIFO depth of 2nIn total, 2nA plurality of memory cells, n being a positive integer; reading two memory cell data in one reading clock period, dividing the data into odd and even paths, and designing the reading and writing clock of the asynchronous FIFO circuit according to the frequency relation required by an external circuit as follows: f. ofwclk＝2frclk，fwclkFor writing clock frequency, frclkFor read clock frequency, data is written from one channel and read from two channels.
The read-write address bit width of the FIFO read-write control module is n and ranges from 0 to 2n-1, 2 in FIFOnA plurality of memory cells; the bit width of the read-write pointer is n +1, and the read-write pointer consists of a read-write address and a most significant bit in a range of 0-2n+1-1, representing the read and write pointers traversing the FIFO twice. The method for judging the empty and full states of the FIFO read-write control module comprises the following steps: comparing the read pointer with a write pointer synchronized to a read clock domain, and if the read pointer and the write pointer are equal, judging that the read pointer is empty; and comparing the write pointer with the read pointer synchronized to the write clock domain, and if the highest bits of the write pointer and the read pointer are opposite and the rest bits are equal, judging that the write pointer is full.
The calculation method of the FIFO delay calculation module for fractional delay comprises the following steps: determining the clock period of the DAC with the decimal delay range of 0-m-1 according to different interpolation multiples m, then sampling the write clock by using m/2 sampling clocks with the same frequency as the read clock, and determining the phase difference between the write clock and the read clock; where m/2 sample clocks are offset by one DAC clock cycle in sequence and the read clock is in phase with the first sample clock, where m is 2, 4, 8, 16 … …. The calculation method of the FIFO delay calculation module for the integer delay comprises the following steps: and synchronizing the writing pointer in the form of the Gray code by using a read clock, synchronizing the writing pointer to a read clock domain, and obtaining the difference value between the synchronized writing pointer and the synchronous read pointer as the integer delay.
The FIFO delay configuration module configures fractional delay by adjusting the phase of a read clock: and subtracting the current real-time decimal delay value from the newly configured delay value to obtain the variation which is the DAC clock period needing to be delayed by the read clock, so that the phase difference between the write clock and the read clock is changed. The setting of the integer delay by the FIFO delay configuration module is realized by changing the value of a read pointer: firstly, judging whether the decimal delay preset value minus the current decimal delay is positive or negative, and if the result is positive, changing a read pointer into a write pointer of a synchronous read clock domain minus a preset value of integer delay; the result is negative, the read pointer becomes the write pointer synchronized to the read clock domain minus the preset value of the integer delay plus 1, thereby changing the difference between the write pointer and the read pointer.
The invention can set different FIFO delay values to configure the delay of the data to be suitable for different application environment requirements. The configuration range is 1 DAC clock cycle to (2n-1) write clock cycle plus (m-1) DAC clock cycle. And m and n are variable quantities and are selected according to specific design requirements.
In the embodiment, the interpolation multiple m is set to be 2, 4 and 8, the bit width n of the read-write address is set to be 3, the depth of the FIFO is 8, and the bit width of the data is 16 bits.
The storage module 1 is a dual-port RAM with 8 storage units in total, and the relationship between a read-write clock and a DAC clock is fwclk＝2frclk＝1/m fDAC。
The FIFO read-write control module 2 realizes the read-write operation on the storage module, the read-write address bit width is 3, the range is 000-111, and 0-7 storage units in the FIFO are represented. The bit width of the read-write pointer is 4, and the read-write pointer consists of a read-write address and a most significant bit, wherein the most significant bit is used for judging the fullness and the vacancy of the FIFO, the range is 0000-1111, and the FIFO is traversed twice in a circular manner under the control of each read-write clock. When the device is powered on or reset, the read pointer is set to 0, the write pointer is set to 4, and the optimal FIFO timing allowance is kept. And simultaneously, the binary read-write pointer is converted into a read-write pointer in a Gray code form, and the read-write pointers are respectively synchronized to another clock domain through two stages of registers, so that the read-write pointers of different clock domains can be compared to judge the empty and full states of the FIFO.
The FIFO delay calculation block 3 implements the calculation of the current FIFO delay. And performing different frequency division on the read-write clock under different interpolation multiples, sampling the write clock by using a sampling clock which is in phase with the read clock and has fixed phase deviation, and determining that the difference between the write clock and the read clock is a few DAC clock cycles to realize the calculation of fractional delay. Fig. 2 shows a relationship between the read/write clock and the sampling clock under the condition of 8 times of interpolation, where Rd represents fractional delay, i.e., a phase difference between the write clock and the read clock, and is obtained by sampling the sampling clock PCLK, and the fractional delay corresponding to the sampling result of the sampling clock is shown in table 1.
Figure BDA0003027488160000061
TABLE 1 fractional delay calculation results
And meanwhile, synchronizing a writing pointer in a Gray code form to a reading clock domain through a two-stage register, and subtracting the reading pointer at the synchronous moment from the synchronized writing pointer to realize the calculation of integer delay.
The FIFO delay configuration module 4 implements the configuration of the FIFO delay values. As shown in fig. 3, after the fractional delay change is detected, the read clock is delayed by a corresponding clock period according to the change value. Taking 8 times of interpolation as an example, assuming that the decimal delay before configuration is a real-time value of 0, configuring a new decimal delay value of 100, and when 8 times of interpolation is performed, the adjustment range of the decimal delay is 1-7 DAC clock cycles, the new decimal delay is increased compared with the current decimal delay by an amount of 4, so that the read clock is delayed by 4 DAC cycles, the phase difference between the read clock and the write clock is increased, and the configuration of the decimal delay is completed.
The above example is to configure the fractional delay value to be greater than the current fractional delay value, and when the situation is opposite and the fractional delay value needs to be reduced, also taking the case of 8 times of interpolation as an example, the current fractional delay size is 7 DAC clock cycles, the configuration new fractional delay is 1 DAC clock cycle, at this time, the variation is 2, the read clock is delayed by 2 DAC clock cycles, the fractional delay is changed to 9 DAC clock cycles, and the fractional delay range of 8 times of interpolation is 0-7 DAC clock cycles, therefore, when the read clock is delayed by 1 DAC clock cycle, the fractional delay value is changed to 0 again, the phase difference between the read and write clocks is changed to 1 write clock cycle, at this time, the integer delay is increased by 1 on the original basis, the fractional delay is changed to 0, and the read clock is delayed by 1 DAC clock cycle again, so that the fractional delay is changed to 1 DAC clock cycle. Aiming at the situation that the integer delay is increased due to the configuration of the decimal delay, the integer configuration part needs to be corrected, and the real-time FIFO delay can be ensured to be the same as the configuration value.
By adjusting the read pointer to configure the integer delay, as shown in fig. 4, after detecting the change of the integer delay, the read pointer is obtained according to the current write pointer and the newly configured integer delay. When the decimal delay does not generate carry for the integer delay, the new read pointer value is the current write pointer minus the integer delay value required to be set; when carry is generated, the size between the read-write pointers is increased by 1 write clock cycle, the integer delay is increased by 1, and then the new read pointer is added with 1 by subtracting the integer delay value required to be set from the current write pointer, so as to correct the carry. Fig. 5 shows a FIFO read pointer change flow chart.
The configuration of the FIFO delay can be correctly realized by combining the FIFO delay calculation module and the FIFO delay configuration module, which is described as an example below. Assuming that the current interpolation is 8, the FIFO delay is 51 as the read-back value, wherein 5 represents 5 FIFO integer delays, i.e. 5 status differences of the read and write pointers, and 1 represents 1 FIFO fractional delay, i.e. 1 DAC clock cycle, i.e. the phase difference between the write clock and the read clock is TDAC(comprising) -2TDAC(not included) wherein TDACFor one DAC clock cycle, the size less than 1 DAC clock cycle is ignored, and the FIFO delay value is newly configured to be 30. Firstly, FIFO fractional delay is configured, the variation of the fractional delay is 7, so a read clock delays 7 DAC clock cycles, the fractional delay plus 7 is changed into 8, and since the fractional delay range is 0-7 DAC clock cycles under the condition of 8 times of interpolation, the fractional delay is actually 0 when the fractional delay is 8, and a carry is generated to give the integer delay at the same time. Then configuring FIFO integer delay, using the carry generated by subtracting the newly set integer delay and the decimal delay from the current write pointer to obtain the correct read pointer value,the configuration of the integer delay is completed.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (6)

1. The asynchronous FIFO circuit with configurable delay is characterized by comprising a storage module, an FIFO read-write control module, an FIFO delay calculation module and an FIFO delay configuration module;
the storage module provides corresponding storage space for data according to the indication of the control signal, when the FIFO writing rate is the same as the FIFO reading rate, the size of the real-time occupied storage space is kept unchanged, and when the effective edge of the clock arrives, data of one unit is written into or read from the storage module;
the FIFO read-write control module is used for generating a read-write address, a read-write pointer and a synchronous read-write pointer of the FIFO, and generating an FIFO full-empty identifier to be fed back to the system to ensure correct data transmission;
the FIFO delay calculation module calculates the current FIFO delay, feeds back the current delay value to the register and reads the current delay value by the SPI; the calculation method of the FIFO delay calculation module for fractional delay comprises the following steps: determining the clock period of the DAC with the decimal delay range of 0-m-1 according to different interpolation multiples m, then sampling the write clock by using m/2 sampling clocks with the same frequency as the read clock, and determining the phase difference between the write clock and the read clock; wherein m/2 sampling clocks are sequentially offset by one DAC clock period, and the read clock is in phase with the first sampling clock, wherein m is 2, 4, 8, 16 … …; the calculation method of the FIFO delay calculation module for the integer delay comprises the following steps: synchronizing the writing pointer in the form of the Gray code by using a read clock, synchronizing the writing pointer to a read clock domain, wherein the difference value between the synchronized writing pointer and the synchronous reading pointer is the integer delay;
the FIFO delay configuration module can configure a delay value required to be set by the SPI, extract the newly configured delay value, compare the newly configured delay value with a real-time delay value, adjust according to a comparison result, and configure the delay of the FIFO to the set value.
2. The delay-configurable asynchronous FIFO circuit of claim 1, wherein the memory module is a double-ended RAM with a FIFO depth of 2nIn total, 2nA plurality of memory cells, n being a positive integer; reading two memory cell data in one reading clock period, and dividing the data into odd and even paths, wherein the reading and writing clock of the asynchronous FIFO circuit has the frequency relation according to the requirement of an external circuit: f. ofwclk＝2frclk，fwclkFor writing clock frequency, frclkFor read clock frequency, data is written from one channel and read from two channels.
3. The delay configurable asynchronous FIFO circuit of claim 2 wherein said FIFO read write control module has a read write address bit width of n ranging from 0 to 2n-1, 2 in FIFOnA plurality of memory cells; the bit width of the read-write pointer is n +1, and the read-write pointer consists of a read-write address and a most significant bit in a range of 0-2n+1-1, representing the read and write pointers traversing the FIFO twice.
4. The delay configurable asynchronous FIFO circuit of claim 3, wherein the FIFO read write control module determines the empty state by: comparing the read pointer with a write pointer synchronized to a read clock domain, and if the read pointer and the write pointer are equal, judging that the read pointer is empty; and comparing the write pointer with the read pointer synchronized to the write clock domain, and if the highest bits of the write pointer and the read pointer are opposite and the rest bits are equal, judging that the write pointer is full.
5. The delay-configurable asynchronous FIFO circuit of claim 4, wherein the configuration of the fractional delay by the FIFO delay configuration module is achieved by adjusting a phase of a read clock: and subtracting the current real-time decimal delay value from the newly configured delay value to obtain the variation which is the DAC clock period needing to be delayed by the read clock, so that the phase difference between the write clock and the read clock is changed.
6. The delay-configurable asynchronous FIFO circuit of claim 5, wherein the setting of the integer delay by the FIFO delay configuration module is achieved by changing a value of a read pointer: firstly, judging whether the decimal delay preset value minus the current decimal delay is positive or negative, and if the result is positive, changing a read pointer into a write pointer of a synchronous read clock domain minus a preset value of integer delay; the result is negative, the read pointer becomes the write pointer synchronized to the read clock domain minus the preset value of the integer delay plus 1, thereby changing the difference between the write pointer and the read pointer.
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